Christian Mesina Jared Acosta CSE 310

Lab 10 Mini Register File

1. Verilog Programming

Source Code: reg_fil.v module Register_File( output [3:0] dataOut,input [3:0] data_in, input [1:0] read_add, input read_en, input [1:0] write_add, input write_en, output a, b, c, dd, e, f, g, output [3:0] EN); wire [3:0] read_sel, write_sel; dec2x4 Dec_Read(read_sel, read_en, read_add); dec2x4 Dec_Write( write_sel, write_en, write_add); Nibble_Reg Reg_0(dataOut, data_in, write_sel[0],read_sel[0]); Nibble_Reg Reg_1(dataOut, data_in, write_sel[1],read_sel[1]); Nibble_Reg Reg_2(dataOut, data_in, write_sel[2],read_sel[2]); Nibble_Reg Reg_3(dataOut, data_in, write_sel[3],read_sel[3]); seg7 display (a, b, c, dd, e, f, g, EN, dataOut[3], dataOut[2], dataOut[1], dataOut[0]); endmodule module Nibble_Reg(data_out, data_in, load, out_en); input [3:0] data_in; input load, out_en; output [3:0] data_out; wire [3:0] dff_out; wire [3:0] Qn; wire rst;

assign rst = 0; bufif1 tri3 (data_out[3], dff_out[3], out_en); bufif1 tri2 (data_out[2], dff_out[2], out_en); bufif1 tri11 (data_out[1], dff_out[1], out_en); bufif1 tri00 (data_out[0], dff_out[0], out_en); Dff Reg_Bit_3(dff_out[3], Qn[3], load, rst, data_in[3]); Dff Reg_Bit_2(dff_out[2], Qn[2], load, rst, data_in[2]); Dff Reg_Bit_1(dff_out[1], Qn[1], load, rst, data_in[1]); Dff Reg_Bit_0(dff_out[0], Qn[0], load, rst, data_in[0]); endmodule module Dff( output reg Q, Qn, input ck, rst, D ); always @(posedge ck, posedge rst) if ( rst != 0) begin Q<= 1'b0; Qn <= 1'b1; end else begin Q <= D; Qn <= ~D; end endmodule module dec2x4 (output [3:0] Y, input EN, input [1:0] A ); assign Y[0] = ~A[1] & ~A[0] & EN; assign Y[1] = ~A[1] & A[0] & EN; assign Y[2] = A[1] & ~A[0] & EN; assign Y[3] = A[1] & A[0] & EN; endmodule module dec3x8 (output [7:0] Y, input [2:0] A); dec2x4 dec0 ( Y[3:0], ~A[2], A[1:0] );

dec2x4 dec1 ( Y[7:4], A[2], A[1:0] ); endmodule module seg7( output a, b, c, d, e, f, g, output [3:0] EN, input W, X, Y, Z );

wire a0, b0, c0, d0, e0, f0, g0; assign a0 = Y && X || !W && Y || !X && !Z || !W && X && Z || W && !X && !Y || W && !Z; assign b0 = !W && Y && Z || !X && !Y || !X && !Z || !W && !Y && !Z || W && !Y && Z; assign c0 = W && !X || !W && X || !Y && Z || !X && !Y || !X && Z; assign d0 = W && !Y || !X && Y && Z || !W && !X && !Z || X && !Y && Z || X && Y && !Z; assign e0 = W && X || Y && !Z || !X && !Z || W && !X && Y; assign f0 = W && !X || !W && X || !Y && !Z || W && Y; assign g0 = W && !X || Y && !Z || W && Z || !W && X && !Y || !X && Y; assign a = ~a0; assign b = ~b0; assign c = ~c0; assign d = ~d0; assign e = ~e0; assign f = ~f0; assign g = ~g0; assign EN = 4'b1110; endmodule reg_fil_tb.v module regfil_test; reg[3:0] data_in; reg[1:0] read_add; reg read_en; reg[1:0] write_add; reg write_en;

wire[3:0] dataOut; Register_File regf(.dataOut(dataOut), .data_in(data_in), .read_add(read_add), .read_en(read_en), .write_add(write_add), .write_en(write_en)); initial begin $display("time \t Data in \t read en \t read add \t write en \t write add \t data out"); $monitor("%g \t %4b \t\t %b \t %2b \t %b \t %2b \t %4b", $time, data_in, read_en, read_add, write_en, write_add, dataOut); end initial begin // Initialize inputs data_in = 4'b0000; read_add = 2'b00; read_en = 0; write_add = 2'b00; write_en = 0; #100; // write 0001 into register 00 #10 write_en = 1'b1; write_add = 2'b00; data_in = 4'b0001; // write 0010 into register 01 #10 write_add = 2'b01; data_in = 4'b0010; // write 0011 into register 10 #10 write_add = 2'b10; data_in = 4'b0011; // write 0100 into register 11 #10 write_add = 2'b11; data_in = 4'b0100; // read data from register 00 #10 write_en = 0;

read_en = 1; read_add = 2'b00; // read data stored in register 01, 10 and 11 sequentially #10 read_add = 2'b01; #10 read_add = 2'b10; // write 1110 into register 01 and read data stored in register 01 simultaneously #10 write_en = 1; write_add = 2'b01; data_in = 4'b1110; read_add = 2'b01; #10 $finish; end endmodule Output:

2. Spartan-3 Programming

Dff.v `timescale 1ns / 1ps module Register_File( output [3:0] dataOut,input [3:0] data_in, input [1:0] read_add, input read_en, input [1:0] write_add, input write_en); wire [3:0] read_sel, write_sel; dec2x4 Dec_Read(read_sel, read_en, read_add); dec2x4 Dec_Write( write_sel, write_en, write_add); Nibble_Reg Reg_0(dataOut, data_in, write_sel[0],read_sel[0]); Nibble_Reg Reg_1(dataOut, data_in, write_sel[1],read_sel[1]); Nibble_Reg Reg_2(dataOut, data_in, write_sel[2],read_sel[2]); Nibble_Reg Reg_3(dataOut, data_in, write_sel[3],read_sel[3]); endmodule module Nibble_Reg(data_out, data_in, load, out_en); input [3:0] data_in; input load,out_en;

output [3:0] data_out; wire [3:0] dff_out; wire [3:0] Qn; wire rst; assign rst = 0; bufif1 tri3 (data_out[3], dff_out[3], out_en); bufif1 tri2 (data_out[2], dff_out[2], out_en); bufif1 tri11 (data_out[1], dff_out[1], out_en); bufif1 tri00 (data_out[0], dff_out[0], out_en); Dff Reg_Bit_3(dff_out[3], Qn[3], load, rst, data_in[3]); Dff Reg_Bit_2(dff_out[2], Qn[2], load, rst, data_in[2]); Dff Reg_Bit_1(dff_out[1], Qn[1], load, rst, data_in[1]); Dff Reg_Bit_0(dff_out[0], Qn[0], load, rst, data_in[0]); endmodule module Dff( output reg Q, Qn, input ck, rst, D ); always @(posedge ck, posedge rst) if ( rst != 0) begin Q<= 1'b0; Qn <= 1'b1; end else begin Q <= D; Qn <= ~D; end endmodule module dec2x4 (output [3:0] Y, input EN, input [1:0] A );

assign Y[0] = ~A[1] & ~A[0] & EN; assign Y[1] = ~A[1] & A[0] & EN; assign Y[2] = A[1] & ~A[0] & EN; assign Y[3] = A[1] & A[0] & EN; endmodule module dec3x8 (output [7:0] Y, input [2:0] A); dec2x4 dec0 ( Y[3:0], ~A[2], A[1:0] ); dec2x4 dec1 ( Y[7:4], A[2], A[1:0] ); endmodule Register_File.ucf NET "data_in[0]" LOC = "F12"; NET "data_in[1]" LOC = "G12"; NET "data_in[2]" LOC = "H14"; NET "data_in[3]" LOC = "H13"; NET "read_add[0]" LOC = "J14"; NET "read_add[1]" LOC = "J13"; NET "write_add[0]" LOC = "K14"; NET "write_add[1]" LOC = "K13"; NET "read_en" LOC = "M13"; NET "write_en" LOC = "M14"; NET "dataOut[0]" LOC = "K12"; NET "dataOut[1]" LOC = "P14"; NET "dataOut[2]" LOC = "L12"; NET "dataOut[3]" LOC = "N14";

3. (Extra Credit) 7-seg LED display

Dff.v `timescale 1ns / 1ps module Register_File( output [3:0] dataOut,input [3:0] data_in, input [1:0] read_add, input read_en, input [1:0] write_add, input write_en, output a, b, c, dd, e, f, g, output [3:0] EN); wire [3:0] read_sel, write_sel; dec2x4 Dec_Read(read_sel, read_en, read_add); dec2x4 Dec_Write( write_sel, write_en, write_add); Nibble_Reg Reg_0(dataOut, data_in, write_sel[0],read_sel[0]); Nibble_Reg Reg_1(dataOut, data_in, write_sel[1],read_sel[1]); Nibble_Reg Reg_2(dataOut, data_in, write_sel[2],read_sel[2]); Nibble_Reg Reg_3(dataOut, data_in, write_sel[3],read_sel[3]); seg7 display (a, b, c, dd, e, f, g, EN, dataOut[3], dataOut[2], dataOut[1], dataOut[0]); endmodule module Nibble_Reg(data_out, data_in, load, out_en);

input [3:0] data_in; input load, out_en; output [3:0] data_out; wire [3:0] dff_out; wire [3:0] Qn; wire rst; assign rst = 0; bufif1 tri3 (data_out[3], dff_out[3], out_en); bufif1 tri2 (data_out[2], dff_out[2], out_en); bufif1 tri11 (data_out[1], dff_out[1], out_en); bufif1 tri00 (data_out[0], dff_out[0], out_en); Dff Reg_Bit_3(dff_out[3], Qn[3], load, rst, data_in[3]); Dff Reg_Bit_2(dff_out[2], Qn[2], load, rst, data_in[2]); Dff Reg_Bit_1(dff_out[1], Qn[1], load, rst, data_in[1]); Dff Reg_Bit_0(dff_out[0], Qn[0], load, rst, data_in[0]); endmodule module Dff( output reg Q, Qn, input ck, rst, D ); always @(posedge ck, posedge rst) if ( rst != 0) begin Q<= 1'b0; Qn <= 1'b1; end else begin Q <= D; Qn <= ~D; end endmodule module dec2x4 (output [3:0] Y, input EN, input [1:0] A ); assign Y[0] = ~A[1] & ~A[0] & EN;

assign Y[1] = ~A[1] & A[0] & EN; assign Y[2] = A[1] & ~A[0] & EN; assign Y[3] = A[1] & A[0] & EN; endmodule module dec3x8 (output [7:0] Y, input [2:0] A); dec2x4 dec0 ( Y[3:0], ~A[2], A[1:0] ); dec2x4 dec1 ( Y[7:4], A[2], A[1:0] ); endmodule module seg7( output a, b, c, d, e, f, g, output [3:0] EN, input W, X, Y, Z );

wire a0, b0, c0, d0, e0, f0, g0; assign a0 = Y && X || !W && Y || !X && !Z || !W && X && Z || W && !X && !Y || W && !Z; assign b0 = !W && Y && Z || !X && !Y || !X && !Z || !W && !Y && !Z || W && !Y && Z; assign c0 = W && !X || !W && X || !Y && Z || !X && !Y || !X && Z; assign d0 = W && !Y || !X && Y && Z || !W && !X && !Z || X && !Y && Z || X && Y && !Z; assign e0 = W && X || Y && !Z || !X && !Z || W && !X && Y; assign f0 = W && !X || !W && X || !Y && !Z || W && Y; assign g0 = W && !X || Y && !Z || W && Z || !W && X && !Y || !X && Y; assign a = ~a0; assign b = ~b0; assign c = ~c0; assign d = ~d0; assign e = ~e0; assign f = ~f0; assign g = ~g0; assign EN = 4'b1110; endmodule

Register_File.ucf NET "data_in[0]" LOC = "F12"; NET "data_in[1]" LOC = "G12"; NET "data_in[2]" LOC = "H14"; NET "data_in[3]" LOC = "H13"; NET "read_add[0]" LOC = "J14"; NET "read_add[1]" LOC = "J13"; NET "write_add[0]" LOC = "K14"; NET "write_add[1]" LOC = "K13"; NET "read_en" LOC = "M13"; NET "write_en" LOC = "M14"; NET "dataOut[0]" LOC = "K12"; NET "dataOut[1]" LOC = "P14"; NET "dataOut[2]" LOC = "L12"; NET "dataOut[3]" LOC = "N14"; NET "EN[0]" LOC = "D14"; NET "EN[1]" LOC = "G14"; NET "EN[2]" LOC = "F14"; NET "EN[3]" LOC = "E13"; NET a LOC = "E14"; #segment a NET b LOC = "G13"; NET c LOC = "N15"; NET dd LOC = "P15"; NET e LOC = "R16"; NET f LOC = "F13"; NET g LOC = "N16"; #segment g

4. Report - For this lab, we created a mini register file (memory) using Verilog and the Spartan-3

board. We created a D flip-flop that holds 1 bit of data, and it only changes its data when the clock changes. We also created a module to hold our four bit register, which functions in the same way as IC 74374 we used in previous labs; and we just renamed clk as load. We also created a 3x8 decoder using 2x4 decoders. Also, we created a module shown in the page of the lab and followed the test bench that the instructor displayed for us. We believe we got a 30/20 for this lab because we did everything correctly and the instructor checked us off for all three experiments.