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Lab 8 Control Area Network

Fall 2019

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Lab 8: Controller Area Network

• For a general description of CAN, see the document posted on the course website

• Lab 8 has two parts:– Part 1: you will write a program that

communicates with a neighboring lab station to implement the virtual wall on adjacent haptic wheels

– Part 2: Each haptic wheel is connected to adjacent wheels with virtual springs and dampers. When all groups are online, moving your wheel will push and pull on the wheels of your immediate neighbors, and if no one is holding the other wheels, all the wheels in the lab can be moved from just one lab station.

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S32K144 FlexCAN

• 3 FlexCAN Modules

– We will use FlexCAN0, which has 32 message buffers.

– Each buffer holds the message ID, data, timestamp and control bits used to activate the buffer and receive or transmit data.

• Implement CAN 2.0B protocol with standard and extended identifiers and the CAN FD (Flexible Data rate) protocol with up to 64 bytes data payload.

– We will use CAN 2.0B with standard identifiers.

• We will set up one receive and one transmit buffer to share wheel angle and torque information across the bus.

• See Chapter 53 of Reference Manual

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S32K144 FlexCAN Arbitration

• S32K144 may have many messages in message buffers waiting to be transmitted– All buffers programmed as transmit buffers are

scanned to find the lowest ID, lowest buffer number, or the highest priority based on certain control register and buffer bit fields

– Whichever message is selected must then compete with messages from other nodes in conformance with normal CAN protocol: lowest ID = highest transmission priority

– We will not use this feature of the FlexCAN module in Lab 8 (we should have only one message ready to transmit at any time)

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FlexCAN Configuration Registers

/** CAN - Size of Registers Arrays */

#define CAN_RAMn_COUNT 128u

...

/** CAN - Register Layout Typedef */

typedef struct {

__IO uint32_t MCR; /* Module Configuration Register, offset: 0x0 */

__IO uint32_t CTRL1; /* Control 1 register, offset: 0x4 */

__IO uint32_t TIMER; /* Free Running Timer, offset: 0x8 */

...

__IO uint32_t IMASK1; /* Interrupt Masks 1 register, offset: 0x28 */

...

__IO uint32_t IFLAG1; /* Interrupt Flags 1 register, offset: 0x30 */

...

__IO uint32_t RAMn[CAN_RAMn_COUNT]; /* Embedded RAM, array offset: 0x80,

array step: 0x4 */

...

} CAN_Type, *CAN_MemMapPtr;

• FlexCAN may be configured using struct and #define items in

NXP supplied header file

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FlexCAN Module Configuration Register (MCR)

• MDIS: enables (0) or disables (1) the FlexCAN module.

• SOFTRST: resets some of the FlexCAN registers.

• FRZ, HALT, FRZACK, NOTRDY: bitfields used when FlexCAN module goes

into “Freeze” mode during initialization.• MAXMB: selects number of message buffers to initialize. Set to 0xF to initialize

16 buffers – we only use buffers 0-3

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Control 1 Register (CTRL1)

• CLKSRC: sets clock source. Use 0 for SOSCDIV2_CLK = 8 MHz

• PRESDIV, RJW, PSEG1, PSEG2, PROPSEG: used to set number of time

quanta for a CAN bit. Must add up to 0.002 msec for 500kbps CAN. (more later)• SMP: Use either 1 or 3 samples to determine value of bit read from bus

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Free Running Timer (TIMER)

• TIMER: a 16 bit free running timer

- the timer value is captured when the 2nd bit of a message ID is written

onto the CAN bus.

- used for a time stamp when a message is transmitted or received.- after a message is read from a RX buffer, it is necessary to read TIMER in

order to unlock the buffer for the next message reception

9Interrupt Masks 1 and Flags 1 Registers

(IMASK1 and IFLAG1)

• BUFn: enables (1) or disables (0) the message buffer interrupt for buffer n.

• BUFn: set by the FlexCAN module on successful TX or RX from buffer n.

- if IMASK1 bit is also set, an interrupt is generated.

- must be cleared in SW by writing a 1 to BUFn.

IMASK1

IFLAG1

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Embedded RAM (RAMn)

• Area of memory allocated to CAN message buffers.

• CAN FD allows up to 64 bytes data – we use at most 8 bytes.

• Enough RAM for 32 message buffers with 8 bytes data

• Message buffer memory map

CAN_MB * mailbox = (CAN_MB *)&(CAN0->RAMn[4 * buff_num]);

• Pointer mailbox to message buffer buff_num:

8 bytes

of data

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Message Buffer Structure

• Each 8 byte message buffer requires four 32 bit registers.

• The first 32 bit register is the Control and Status Word.

• The second register is the ID.

• The 3rd and 4th registers contain the data.

• Message buffers may be accessed using struct and #define items

in flexcan.c

typedef struct{

volatile uint32_t CAN_MB_HD1; \* control and status word *\

volatile uint32_t CAN_MB_HD2; \* identifier *\

volatile uint8_t CAN_MB_DATA[8]; \* will only need 2 data registers *\

}CAN_MB;

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Message Buffer Bitfields

Field Description

ID Extended (IDE) Should be set to ‘1’ for extended frames, ‘0’ for standard.

Remote Transmission

Request (RTR)

0: Current MB has a data frame to be transmitted

1: Current MB has a remote frame to be transmitted

Data Length (DLC) Length of data in bytes.

TIME STAMP Contains a copy of the free running timer, captured for Tx and Rx

frames at the time when the beginning of the Identifier fields

appears on the CAN bus.

Frame Identifier (ID) Standard format: 11 most significant bits (28 to 18) are used,

others are ignored. Extended format: all bits are used.

DATA Up to 8 bytes of data.

CODE Activates buffer and indicates status.

• Some bitfields we won’t need:- EDL, BRS, ESI: used only with CAN FD.

- PRIO: used for arbitration between multiple messages in a FlexCAN module.

- SRR: used only for messages with extended IDs

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Message Transmission• Transmit Process: to prepare a message buffer for TX, the CPU must

– Write CODE = 0b1000 to deactivate TX buffer.

– Set IDE = 0 (standard CAN 2.0B msg)

– Write ID of message to be sent

– Set RTR = 0 (data frame)

– Write DLC (data length in bytes)

– Clear IFLAG1 bit (write a 1)

– Write DATA to be transmitted into TX buffer

– Write CODE = 0b110 to activate TX buffer

• Information used for TX is first placed in a struct; see flexcan.h

typedef struct txinfo

{

uint8_t txbuff_num; /* msg buffer to use for TX */

uint32_t id; /* message id */

uint8_t length; /* length of data (bytes) */

uint8_t data[8]; /* data for TX */

} CAN_TXINFO;

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FlexCAN Tx Mailbox

int can_txmsg(CAN_TXINFO *txinfo)

{

CAN_MB * mailbox = (CAN_MB *)&(CAN0->RAMn[4 * txinfo->txbuff_num]);

mailbox->CAN_MB_HD1 = CAN_MB_HD1_CODE(0x8) // disable TX buffer

| CAN_MB_HD1_IDE(0) // standard msg identifier

| CAN_MB_HD1_RTR(0) // data frame

| CAN_MB_HD1_DLC(txinfo->length); // length of data in bytes

mailbox->CAN_MB_HD2 = CAN_MB_HD2_ID(txinfo->id); // message identifier

// clear flag

CAN0->IFLAG1 = 0b1 << txinfo->txbuff_num;

// copy data into message buffer

volatile_memcpy(mailbox->CAN_MB_DATA, txinfo->data, txinfo->length % (8+1));

mailbox->CAN_MB_HD1 |= CAN_MB_HD1_CODE(0xC); // enable TX buffer

return 0;

}

• The function can_txmsg()defined in flexcan.c configures a TX message buffer

and transmits a CAN message

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Message Reception

• When a message is received over CAN, an ISR is called that reads the

message buffer containing the message and processes the data.

• Three functions must be called in sequence, two for setup,

and one to read the msg:

– can_set_rxisr(volatile isr_t rx_ISR): takes as argument the name of

the ISR to be called when a message is received. Sets interrupt priority

and enables interrupts.

– can_rxbuff_init(int rxbuff_num, int id, int useIRQ): takes as

arguments the number of the message buffer and the ID of the message to be received. Set useIRQ = 1 to use a message received interrupt.

– can_rxmsg(CAN_RXINFO *rxinfo): called within the ISR to read the msg.

buffer. The user supplies the number of the RX message buffer

and the remaining members of rxinfo are read from the buffer.

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RX Message Buffer Initialization

• To prepare message buffer buff_num for RX, the CPU must

– Write CODE = 0b0000 to deactivate RX buffer.

– Set IDE = 0 (standard CAN 2.0B msg)

– Write ID = id of message to be received

– Write CODE = 0b0100 to activate RX buffer

– Set IMASK1 bit for buff_num to enable interrupts after msg. receivedint can_rxbuff_init(int buff_num, int id, int useIRQ){

CAN_MB * mailbox = (CAN_MB *)&(CAN0->RAMn[4 * buff_num]); /* CAN msg buffer */

mailbox->CAN_MB_HD1 = CAN_MB_HD1_CODE(0) /* buffer inactive */

| CAN_MB_HD1_IDE(0); /* use standard 11-bit ID */

mailbox->CAN_MB_HD2 = CAN_MB_HD2_ID(id); /* specify message identifier */

mailbox->CAN_MB_HD1 |= CAN_MB_HD1_CODE(0b0100); /* activate RX buffer */

if ( useIRQ ) {

// if we are using a message received interrupt

CAN0->IMASK1 |= 1<<buff_num; /* set IMASK1 bit for the buffer to enable ISR

when message is received */

} return 0;

}

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Reading the RX Message Buffer

• When a message is received an ISR is called.

• The IFLAG1 bits of all relevant RX buffers are checked to see which

one has the message.

• Set rxbuff_num = the number of the RX buffer with the message.

• Call can_rxmsg(CAN_RXINFO *rxinfo).

– First the Code and Status Register must be read to lock the buffer.

– The FlexCAN module will set the BUSY BIT = CODE(0)if it is writing to the

buffer.

– Must wait until FlexCAN clears CODE(0) before reading buffer.

• The remaining fields of rxinfo are filled from the RX message buffer:

typedef struct rxinfo

{

uint8_t rxbuff_num; /* msg buffer to use for RX*/

uint8_t length; /* length of received msg data (bytes) */

uint32_t id; /* id of received msg */

uint8_t data[8]; /* data read from msg buffer */

uint16_t frt; /* free running timer */

} CAN_RXINFO;

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FlexCAN RX Mailbox

• The function can_rxmsg()reads an RX message buffer

int can_rxmsg(CAN_RXINFO *rxinfo){

CAN_MB * mailbox = (CAN_MB *)&(CAN0->RAMn[4 * rxinfo->buff_num]);

/* Read Control and Status word to activate lock on the buffer (mandatory).

Check if CODE(0) is set and wait until it is cleared. */

while((mailbox->CAN_MB_HD1 >> CAN_MB_HD1_CODE_SHIFT) & 0b1);

/* Read the ID field of the received msg. */

rxinfo->id = (mailbox->CAN_MB_HD2 & CAN_MB_HD2_ID_MASK) >> CAN_MB_HD2_ID_SHIFT;

/* Get length of data (DLC) from RX msg buffer*/

rxinfo->length = (mailbox->CAN_MB_HD1 & CAN_MB_HD1_DLC_MASK)>>CAN_MB_HD1_DLC_SHIFT;

/* Get the data. Mandatory step. */

volatile_memcpy(rxinfo->data, mailbox->CAN_MB_DATA, rxinfo->length);

/* Read the free running timer to unlock buffer (mandatory). */

rxinfo->frt = CAN0->TIMER;

/* Clear IFLAG1 */

can_clear_buff_flag(rxinfo->buff_num);

return 0;

}

CAN Timing

• Each bit on the CAN bus is divided into

4 segments.

– Synchronization Segment

– Propagation Segment

– Phase Segment 1

– Phase Segment 2

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1 CAN bit

CAN Timing

• The Synchronization Segment is always one

quantum long, and is used for synchronization of the

clocks.

– A bit edge is expected to take place here when the data

changes on the bus.

• The Propagation Segment compensates for the delay

in the bus lines.

• The bus level is sampled at the border between

Phase Segment 1 and Phase Segment 2.

– The Phase Segments may be shortened or lengthened by

the CAN controller to keep the clocks in sync.

– Resync Jump Width (RJW) sets maximum number of time

quanta that Phase Segments may be adjusted

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CAN Timing21

FlexCAN Oscillator Clock = SOSCDIV2_CLK = 8 MHz.

We use prescalar = 1 so CAN System Clock = 8 MHz.

CAN Timing

• CAN system clock speed, Propagation

Segment, Phase Segment 1, Phase

Segment 2, and Resync Jump Width are

programmable

• It is the user’s responsibility to ensure

the bit time settings are in compliance

with the CAN standard

• CAN timing is set in the FlexCAN Control

Register (CTRL1)

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CAN Timing23

CAN Timing

• For more information on CAN bit timing:

– Chapter 53.5.9.7 of the Reference Manual

– NXP Application Note AN1798, CAN Bit

Timing Requirements

– Kvaser Website

http://www.kvaser.com/about-can/the-can-

protocol/can-bit-timing/

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FlexCAN Control 1 Register (CTRL1)

• PRESDIV: Prescaler Division Factor

– (CAN oscillator frequency)/(PRESDIV + 1) = CAN clock frequency

• PSEG1 — Phase Segment 1

• PSEG2 — Phase Segment 2

• CLK_SRC — CAN Engine Clock Source (0 = SOSCDIV2_CLK = 8 MHz )

• PROPSEG — Propagation Segment

CAN_0.CTRL.B.PRESDIV = 0;CAN_0.CTRL.B.RJW = 3;

CAN_0.CTRL.B.PSEG1 = 5;CAN_0.CTRL.B.PSEG2 = 5;CAN_0.CTRL.B.PROPSEG = 2;

# of time quanta = SYNC_SEG + (PROPSEG + PSEG1 + 2) + (PSEG2 + 1)

CAN clock frequency = 8 MHz / 1 = 8 MHz

Bit rate = (CAN clock frequency )/(# of time quanta) = 8MHz/16 = 500 kbps

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Lab 8: Software

• Good news: FlexCAN driver software has

been written for you for Lab 8:

– See flexcan.h and flexcan.c

– Lab documentation describes the sequence of

operations required

• You need to write the software for the virtual

wall and virtual chain

– We will transmit/receive wheel angle and torque

data at fixed interrupt frequency

– Use LPIT and FlexTimer QD and PWM code

from previous labs

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Lab 8: Virtual Wall Software

• LPIT ISR of User A reads its wheel angle in degrees as a 32-bit

float (use a 1kHz interrupt frequency) and transmits a 4-byte

wheel angle message onto the CAN bus.

• User B's CAN message-received ISR is called when User A's

message is received

– Extracts the wheel angle

– Calculates the virtual spring-wall torque in N-mm

– Transmits a 4-byte message with the torque value

• User A's CAN message-received ISR updates the motor torque

with the value received from User B.

• Might you expect any performance issues with this distributed

virtual wall?

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Lab 8: Virtual Chain Software

• Each wheel does this:– Read the wheel angle.

– Estimate the wheel velocity.

– Transmit an 8-byte message with the wheel angle and velocity, each as 32-bit float values.

– Compute the torque based on the most recent wheel angles and velocities from the two neighboring lab stations.

– Update the motor torque.

qi,qiq,q q j ,q j

29Lab 8: How to Calculate Virtual Chain

Torque?

• Spring torque acting on middle wheel:

• Damping torque acting on middle wheel:

• Total torque

• How do you estimate velocity?

qi,qiq,q q j ,q j

Ts = K qi -q( ) + K q j -q( )

Td = B qi -q( ) + B q j -q( )= Ts +Td

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Lab 8: Vector CANalyzer*

• Messages on the bus

- ID

- Size

- Data

- Units

• Bus utilization

* http://vector.com/vi_canalyzer_en.html