Lab Report:FPGA

Group members (WRK STATION 1):Section 7-C

Zohaib Ali Farhat100183Abdul Rehman Wali100393Hamzah Khan 100128Ali Adil Buttar100318

Date: 8/12/2013

LAB # 1Xilinx ISE 7.1 TutorialObjective:The goal of this lab is for you to become familiar with the Xilinx ISE by making a project in ISE and then to simulate it on Xilinx ISE Simulator.Instruction:The main emphases will be to make you learn, how the tools works to implement a Verilog code on FPGA.Procedure: Create an ISE project for a Spartan-3 FPGA device. Create a top-level HDL design and verify that your HDL code uses the correct syntax. Create a test bench waveform to be used in simulation of the design. Create a User Constraints File. Apply timing and pin location constraints to the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the placed and routed design in FPGA Editor. View the area groups of the design in Floor-planner. Create a configuration bit-stream.Code:module lab1(a, b, y);input a, b;output y;assign y=a&b;endmoduleRTL Diagram:

Results:

Lab # 2Implementation of 4-to-1 Line Multiplexer on FPGA Kit Objective:This lab is an introduction to Digilent Nexys2 Board. The goal of this lab is for you to design a 4-to-1 line multiplexer, simulate it and implement it on FPGA Kit.Instruction:Implement 4-to-1 line multiplexer using Behavioural Modelling. After you have simulated the code you will implement it on FPGA so as to exercise your implementation skills.Procedure: Use Xilinx ISE to make your project. You have to design a 4-to-1 line multiplexer and simulate it. Create a top-level HDL design and verify that your HDL code uses the correct syntax. Create a test bench to be used in simulation of the design. Create a User Constraints File. Apply pin location constraints to the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the area groups of the design in Floor-planner. Create a configuration bit-stream. Implement the design on Digilent Nexys2 Training BoardCode:module mux(Y,A,B,C,D,S0,S1);input A,B,C,D,S0,S1;output Y;assign Y= S0?(S1?A:B):(S1?C:D);endmoduleRTL Diagram:

Results:

LAB # 3To Implement Combinational Circuit and Simulate the Required Result in Model-SimObjective:This lab is an introduction to Model-Sim. The goal of this lab is for you to learn how to code hardware architecture, simulate it on Model-Sim and implement it on FPGA Kit.Instruction:Implement the Architecture using module instantiation and write a simulator as per following instructions. After you have simulated the code on Model-Sim you will implement it on FPGA so as to exercise your implementation skillsProcedure: Use Xilinx ISE to make your project. Code Figure 1 as Hardware Architecture.v file and its simulator as Test-bed.v Create a top-level HDL design and verify that your HDL code uses the correct syntax. Create a test bench to be used in simulation of the design. Create a User Constraints File. Apply pin location constraints to the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the area groups of the design in Floor-planner. Create a configuration bit-stream. Implement the design on Digilent Nexys2 Training Board.

Code:module mux(C1,a0,b0,s1);input [3:0] a0,b0;output [3:0] C1;input s1;assign C1=s1?a0:b0;endmodule

module function (Cout,s5,a0,b0,a1,b1,a2,b2,a3,b3,s1,s2,s3,s4);input [3:0] a0,b0,a1,b1,a2,b2,a3,b3;input s1,s2,s3,s4;output [7:0] Cout;output s5;wire [3:0] C1,C2,C3,C4;wire [7:0] w1,w2,w3,w4;mux m1(C1,a0,b0,s1),m2(C2,a1,b1,s2),m3 (C3,a2,b2,s3),m4 (C4,a3,b3,s4);assign w1={c2,c1},w2={c4,c3},w3=w1+w2,w4=w1-w2;assign Cout =s5?w4:w3;endmoduleRTL Diagram:

Results:

LAB # 4Implementation and Comparison of 8-bit Ripple Carry Adder and Carry Look Ahead Adder

Objective:To understand the delays in digital circuits and its effects by implementation of two different types of Adder circuit on FPGAs.

Requirement before entering into the Lab:You must read the Hardware algorithm of Carry Look Ahead adder and Ripple Carry Adder. You must bring your Text-Book which will help you in coding.

Instructions:The delay in digital circuits is evident when we implement big combinational clouds. These delays lead to Hazards in digital logic circuits. One type of circuit where the effect of gate delays is particularly clear is an ADDER. In this lab you will simulate and measure the delay of ripple carry adder and carry look-ahead adder.

Procedure:1. Make separate projects for both ripple carry adder and carry-look-ahead adder.1. Simulate functional model of both the adders using Model-Sim.1. The carry-look-ahead adder should be made as in the figure-4. First make 4-bit adder and then replicate as given in the figure.1. Do Timing Simulation after you have implemented the circuit. Check out the results.

Code (Ripple carry adder):module binary_adder (c8,s,a,b,c0);input [7:0] a,b;input c0;output [7:0] s;output c8;wire c1,c2,c3,c4,c5,c6,c7;fulladder FA0 (s[0],c1,a[0],b[0],c0);fulladder FA1 (s[1],c2,a[1],b[1],c1);fulladder FA2 (s[2],c3,a[2],b[2],c2);fulladder FA3 (s[3],c4,a[3],b[3],c3);fulladder FA4 (s[4],c5,a[4],b[5],c4);fulladder FA5(s[5],c6,a[5],b[5],c5);fulladder FA6(s[6],c7,a[6],b[6],c6);fulladder FA7(s[7],c8,a[7],b[7],c7);endmodulemodule fulladder (s1,c,x,y,z);input x,y,z;output s1,c;assign s1= x^y^z;assign c=x&y|y&z| z&x;endmoduleRTL Diagram:

Code (carry look ahead adder):module CLA (a,b,c0,s,c8);input [7:0] a,b;input c0;output [7:0] s;output c8;wire c1,c2,c3,c4,c5,c6,c7;wire [7:0] p,g;halfadder HA0(p[0],g[0],a[0],b[0]);halfadder HA1(p[1],g[1],a[1],b[1]);halfadder HA2(p[2],g[2],a[2],b[2]);halfadder HA3(p[3],g[3],a[3],b[3]);halfadder HA4(p[4],g[4],a[4],b[4]);halfadder HA5(p[5],g[5],a[5],b[5]);halfadder HA6(p[6],g[6],a[6],b[6]);halfadder HA7(p[7],g[7],a[7],b[7]);assign c1=g[0]|(p[0]&c0);assign c2=g[1]|(p[1]&c1);assign c3=g[2]|(p[2]&c2);assign c4=g[3]|(p[3]&c3);assign c5=g[4]|(p[4]&c4);assign c6=g[5]|(p[5]&c5);assign c7=g[6]|(p[6]&c6);assign c8=g[7]|(p[7]&c7);assign s[0]=(p[0]^c0);assign s[1]=(p[1]^c1);assign s[2]=(p[2]^c2);assign s[3]=(p[3]^c3);assign s[4]=(p[4]^c4);assign s[5]=(p[5]^c5);assign s[6]=(p[6]^c6);assign s[7]=(p[7]^c7);endmodule

module halfadder (s1,c,x,y);input x,y;output s1,c;assign s1=x^y;assign c=x&y;endmodule

RTL Diagram:

Comparison:8 bit ripple carry adder:Delay in case of ripple carry adder is 19.756 ns

8 bit carry look ahead adder:Delay in case of 8 bit carry look ahead adder is 21.234 ns.

LAB # 5Wallace Tree Multiplier

Objective:This lab is an introduction to Model-Sim. The goal of this lab is to learn how to code Wallace tree multiplier, simulate it on Model-Sim.Procedure: Use Xilinx ISE to make your project. Code Wallace tree multiplier. Create a top-level HDL design and verify that your HDL code uses the correct syntax. Create a test bench to be used in simulation of the design. Perform behavioral simulations on the design. Synthesize and implement your design. View the area groups of the design in Floor-planner. Create a configuration bit-stream.

Code:module Wallace_tree (a,b,w);input [3:0] a,b;output [7: 0] w;integer i,j;wire s1,s2,s3,s4,s5,s6,s7,s8,s10,s11,s12,s13;wire c1,c2,c3,c4,c5,c6,c7,c8,c10,c11,c12,c13; reg [3:0]p[0:3];always @ (a or b)beginfor (i=0; i