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    Systems Research Laboratory at the University of Houston

    OPERATING GAS STOVEREGULATOR WITHOUTHUMAN INTERVENTION

    USING DE2 BOARD

    Sri Sai Datta Kiran SistlaSrinivas Manne Gajanand

    Prudhvi Chandra SimhadriAvinash Suravarapu

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    NIOS II Introduction

    Alteras Nios II is a soft processor, dened in a hardware description

    language, which can be implemented in Alteras FPGA devices.

    The Nios II processor can be used with a variety of other components to

    form a complete system. These components include a number of standard

    peripherals, but it is also possible to dene custom peripherals.

    Alteras DE-II boards contain several components that can be integrated

    into a Nios II system.

    This tutorial provides comprehensive information that will help you

    understand how to create an Altera FPGA design and run it on your

    development board.

    2

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    A Nios II system on DE2 Board

    DE2 Board

    FPGA

    FlashSdram I/O

    SDRAMController

    Tri-statebridge

    Flash MemoryInterface (CFI)

    Nios II

    Processor

    USB Blaster

    JTAG UART

    Interface

    Parallel I/O

    PLL

    System Interconnect Fabric

    Host MainComputer

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    Hardware Required

    Create a NIOS II hardware system and run some example code on it.

    Begin the tutorial by creating a new Quartus II project is a set of files that maintaininformation about your FPGA design. The Quartus II settings file (.qsf) and QuartusII project File (.qpf) files are the primary files in a Quartus II project.

    Hardware Requirements:

    * one computer

    * one DE2 board

    * one Arduino board

    * one Servo motor

    * A USB cable connected between computer and USB blaster port on DE2 board.

    * Power Supply connected to DE2 board.The following figure in the next slide displays the connections between the Hostmain computer, USB Blaster port connected to the DE2 board and power supplygiven to the board.

    5

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    Hardware Connections

    6

    DE2 Board

    Host Main Computer

    USBcable

    PowerSupply FPGA

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    Links to Download the Software

    7

    Altera Quartus II 12.1 Web Edition Download Link:

    http://download.altera.com/software/acdsinst/12.1/177/standalone/12.1_177_quart

    us_free_windows.exe

    or

    https://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-

    PC&l=en

    The Altera Quartus II software includes Syetem on a Programmable Chip

    Builder(SOPC) Builder and Nios II Software Build Tools for Eclipes

    Install the required software.

    Determine that the development board functions properly and is connected to yourcomputer. Install the USB Blaster driver which enables to connect the DE2 board

    with the host computer.

    http://download.altera.com/software/acdsinst/12.1/177/standalone/12.1_177_quartus_free_windows.exehttp://download.altera.com/software/acdsinst/12.1/177/standalone/12.1_177_quartus_free_windows.exehttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttps://www.altera.com/servlets/download3?swcode=WWW-SWD-QII-WE-121-PC&l=enhttp://download.altera.com/software/acdsinst/12.1/177/standalone/12.1_177_quartus_free_windows.exehttp://download.altera.com/software/acdsinst/12.1/177/standalone/12.1_177_quartus_free_windows.exe
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    System Design Flow

    8

    Define system

    BuildFPGA Project

    Build Nios IISystem on FPGA

    Hardware Design Embedded Design

    control the hardware

    Pin Assignment

    Software Design Add and Edit

    source file

    Build Software Application

    Run/Debug

    Add Nios II coreand Peripherals

    GenerateNios II systemProgrammer

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    Nios II System Development Flow

    9

    Steps involved in the System Development Flow:

    Open the Quartus II software to create a new project.

    Defining and Generating the System in SOPC Builder .

    Integrating the SOPC System into the Quartus II Project.

    Developing Software with the Nios II Software Build Tools for Eclipse

    Running Software on the DE2 Board

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    Quartus II 12.1--Create new project

    11

    b) Choose your project folder path and name it DE2NIOSII , then click Next

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    Quartus II 12.1--Create new project

    12

    c) Choose the Family and Available devices shown in the image and click "Next".

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    Quartus II 12.1--Create new project

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    e) In the Summary page and click "Finish".

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    SOPC Builder---Create New Nios II System

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    Start SOPC Builder from Quartus II: Tools => SOPC Builder and name thesystem NIOSII, choose Verilog as the implementation language.

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    SOPC Builder---Set the Clock

    Device Family Cyclone II and the External Clock frequency = 50 MHz.Because the frequency of the crystal oscillator on the DE2 board is 50 MHz.

    16

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    SOPC Builder---Processor

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    From the Component Library , select Processors => Nios II Processor In the Core Nios II tab, select Nios II/e for the processor core. Click "Fini and rename it cpu.

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    SOPC Builder---Flash

    Flash is the hard disk of the Nios II system. The data and

    program will store in it without losing even after the power of

    our DE2 Board is unplugged.Nios II

    System

    Flash

    DATA Width 8 bits

    Address Width22 bits

    FlashMemoryInterface

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    SOPC Builder---Flash

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    From the Component Library , select Memories and Memory Controllers =>External Memory Interfaces => Flash Interfaces => Flash Memory interface (CFI) .In the Attributes tab , set Address Width to 22 and Data Width to 8.

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    SOPC Builder---Tristate Bridge

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    Why do we connect Flash to Tristate Bridge?

    A tristate bridge connects off-chip devices to the system

    interconnect fabric .

    Flash

    Tri-statebridge

    Flash MemoryInterface

    Nios II

    Processor

    System Interconnect Fabric

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    SOPC Builder Tristate Bridge

    22

    From the Component Library , select Bridges => Memory-Mapped => Avalon-MMTristate Bridge . Select the Registered option, and click Finish . Then rename itext_ram_bus .

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    SOPC Builder Connect tristate bridge and flash

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    connect tristate bridge and flash

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    SOPC Builder---SDRAM Controller

    The system requires a large, fast memory block tostore executable code and some data buffers.

    Nios IISystem

    SDRAM

    DATA Width 16 bits

    Address WidthRow 12 bits

    Column 8 bitsSDRAMController

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    SOPC Builder SDRAM Controller

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    From the Component Library , select Memories and Memory Controllers => ExternalMemory Interfaces => SDRAM Interfaces => SDRAM Controller .i) In the Memory Profile tab , set as the following image.ii) In the Timing tab , set as the following image.

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    SOPC Builder JTAG UART

    The JTAG UART provides a convenient way to communicate character data with

    the Nios II processor through the USB Blaster download cable.

    NiosII system

    USB Blaster

    Jtag Uart

    Interface

    HostComputer

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    Nios II system

    SOPC Builder---Parallel I/O

    28

    Parallel I/O provide an easy method for Nios II processor systems to

    receive Input stimuli and drive Output signals.

    Our Nios II system uses PIO signals to drive LEDs on the board.

    I/O (LEDs on DE2 Board)

    I/O Parallel

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    SOPC Builder Parallel I/O

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    From the Component Library , select Peripherals => Microcontroller Peripherals =>PIO (Parallel I/O) . Set the Width to 18 and Direction to Output .Rename it buttonpush.

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    SOPC Builder LCD

    From the component library, select peripherals=>display=> Character LCD . Click finish and renameit lcd_0

    30

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    SOPC builder ------------- Expansion Header Pins

    From the component library, select peripherals=> Microcontroller peripherals=>PIO(parallel I/O) . Select the data width as 4 and select the mode as output.

    Click finish and rename it pin

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    Adding Interrupt

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    Add the Interrupt as [1] as per the Image.

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    SOPC Builder Phase Locked Loop(PLL)

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    33

    PLL is a component in Nios II system which can genereate different

    clock frequency and phase for the system.

    The Input clock of PLL comes from the external oscillator on DE2

    Board.

    DE2 BoardFPGA

    externaloscillator Nios II system

    PLL

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    SOPC Builder PLL

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    From the Component Library, select PLL => Avalon ALTPLL.In the Parameter Settings => General/Modes tab, set the frequency of the inclk0to 50.000 MHz .

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    SOPC Builder PLL

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    In the Parameter Settings => Inputs/Lock tab, uncheck all the checkbox.

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    SOPC Builder PLL

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    In the Output Clocks => clk c0 tab, use the default settings.

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    SOPC Builder PLL

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    In the Output Clocks => clk c1 tab, check the checkbox to Use this clock , set theclock phase shift to -3.00 ns. Click Finish and rename it pll.

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    SOPC Builder Rename all clocks

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    Rename the clock signals as following image.Then click in the Clock column for all components except thepll component and change their driving clocks to sys_clk .Chose the driving clock of pll to clk.

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    SOPC Builder Assign base address and interrupt numbers

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    Click System on the menu and click Assign Base Address & Assign Interrupt Numbers

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    SOPC Builder set reset and exception vector

    40

    Double- click on the cpu component, select sdram for the Reset Vector andsdram for the Exception Vector .

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    SOPC Builder---System Generation

    41

    Go to the System Generation tab and click Generate . There will be Errors shownas the image below. That is a system bug of Quartus II software. Just close theSOPC Builder and open it again, and the problem will be fixed automatically.

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    SOPC Builder System Generation

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    You will see the problem has been fixed automatically, then go to theSystem Generation tab and click Generation . There will be info: Systemgeneration was successful.

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    Quartus II 12.1--Add a Block diagram file

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    Add a new Block diagram file to the project by clicking File => New => BlockDiagram/Schematic File , save it as DE2NIOSII .bdf .

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    Quartus II 12.1 Add to the project

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    Double click the blank area of the bdf file and add the system NIOSII to theproject. NIOSII is the system just being built on the SOPC Builder .

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    Quartus II 12.1 Generate Pins

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    Right click the NIOSII system just added and choose Generate Pins for Symbol Ports .Rename all the ports exactly the same as the following image. Pay attention to thatport name is case-sensitive . Then Compile the project.

    RightClickoverNIOSIIsystem

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    Quartus II 12.1--Generate Pins

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    FPGA project

    Nios IIsystem

    Assign Pins for Nios II systemMake a connection between FPGA and the project

    FPGAPins Connection

    FPGA

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    Quartus II 12.1 DE2.qsf file

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    The .qsf file is to indicate which FPGA pin youhave assigned to the project.set_global_assignment -name DEVICE EP2C35F672C6set_global_assignment -name FAMILY "Cyclone II"

    set_location_assignment PIN_N25 -to SW[0]set_location_assignment PIN_N26 -to SW[1]set_location_assignment PIN_P25 -to SW[2]set_location_assignment PIN_AE14 -to SW[3]set_location_assignment PIN_AF14 -to SW[4]set_location_assignment PIN_AD13 -to SW[5]set_location_assignment PIN_AC13 -to SW[6]set_location_assignment PIN_C13 -to SW[7]

    set_location_assignment PIN_B13 -to SW[8]set_location_assignment PIN_A13 -to SW[9]set_location_assignment PIN_N1 -to SW[10]set_location_assignment PIN_P1 -to SW[11]set_location_assignment PIN_P2 -to SW[12]

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    Quartus II 12.1 Pins assignments

    48

    Click Assignments => Import Assignments and choose the file DE2.qsf to dothe pin assignments. Then the block diagram will be shown as following image.

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    LCD Pin Assignments

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    Quartus II 12.1 Programmer

    50

    Before Download program to FPGA, please check that the USB blaster

    has been connected to your computer. Before running the software: turn

    off the board , and make sure that the program switch " SW19 " is on

    "PROG " mode!

    DE2 BoardComputer

    USBcable

    USBBlaster

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    Quartus II 12.1--USB Blaster Driver

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    The computer will recognize the new hardware

    connected to its USB port, but it will be unable to

    proceed if it does not have the required driver alreadyinstalled.

    If USB Blaster driver is not already installed, the New

    Hardware Wizard will appear like the following image

    in the next slide.

    Follow the installation process as it follows on the

    screen.

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    Quartus II 12.1--USB Blaster Driver

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    Click Next to choose installation option.

    Quartus II 12 1 USB Blaster

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    Quartus II 12.1 USB BlasterDriver

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    Click Next to finish the installation.

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    NIOS II Software Build Tools for Eclipes

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    b) Click File => New => Nios II Application and BSP fromTemplate .

    Load the NIOSII.sopcinfo file from your project folder,set the Project name

    Hello_World and choose Hello World as theTemplate. Then click Finish.

    Check thatthe projectnamesdoesn texist inworkspacealready

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    Introduction to Arduino boardThe output from the expansion header of theDE2 board is given as the input to the Arduinoboard.The Arduino board used in our project isArduino Uno.The Aurdino Uno is a microcontroller boardbased on the ATmega 328 (datasheet) . Itconsists of 14 input/output pins (of which 6can be used as PWM outputs), 6 analoginputs, a 16 MHz ceramic resonator, a USBconnection, a power jack, an ICSP header,and a reset button . It contains everything itneeds to support the microcontroller; to getstarted simply connect it to computer with aUSB cable or power it with a AC-to_DCadapter or battery.

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    Software code ------- LCD

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    In the following screenshot printf command is used to display the desiredcharacters on the LCD.

    Selecting LCD as the Standard Output from the Eclipse software

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    Selecting LCD as the Standard Output from the Eclipse softwareRight click on the motor1_bsp file=> properties=>NIOSII BSP properties=> BSP editor. When the BSP

    editor is launched, from the dropdown menu of stdout select lcd_0 s the output.

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    NIOS II Software C code

    /* Program for Translation of languages using LCD */

    #include

    #include

    #include

    #include

    #include "priv/alt_legacy_irq.h

    int key_flag = 0;

    Count=0x00001

    int i,j,x;

    void key_ISR(void *context, alt_u32 id)

    {

    key_flag =IORD_ALTERA_AVALON_PIO_DATA(BUTTONPUSH_BASE);

    IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTONPUSH_BASE, 0x0);

    62

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    NIOS II Software C code

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    switch (key_flag) {

    case 0x1:{IOWR_ALTERA_PIO_DATA(LEDR_BASE, 0x1);printf (Regulator turned \n); printf ( ON \n);

    IOWR_ALTERA_A_PIO_DATA(PIN_BASE, 0x1);break;}

    case 0x2:{IOWR_ALTERA_PIO_DATA(LEDR_BASE, 0x2);printf (Regulator turned \n); printf ( Off \n); IOWR_ALTERA_A_PIO_DATA(PIN_BASE, 0x0);break;

    }

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    NIOS II Software C code

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    , , ,

    #include "priv/alt_legacy_irq.h are the header files required in thestarting of the program.

    altera_avalon_pio_regs.h is a header file. If you want to operate I/O pins in the

    software, you should add this header file into your C code.IOWR_ALTERA_AVALON_PIO_DATA (BASE, data) is a instruction means

    write data into the base address register.

    Nios II system distributes the Parallel I/O addresses. The software(C code) write

    data into these PIO address to implement the PIO control.

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    NIOS II Software C code

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    Nios II system on FPGA

    I/O controller

    NiosII processor

    PIO have a base

    Address

    Other

    component

    C source Code

    I/O(BUTTONPUSH) on DE2 Board

    Control LED bywriting of readingdata from their

    Address

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    NIOS II Software Build Tools for Eclipes

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    Before running the software: turn off the boad ,and make sure that the program switch " SW19 " is on " RUN " mode!Then turn on the board

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    NIOS II Software Build Tools for Eclipes

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    c) Right click Hello_world_bsp and build the project.The following image is a comparison between thecontaining files ofthe unbuilt project and the built project

    After build project

    NIOS II S f B ild T l f E li

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    NIOS II Software Build Tools for Eclipes

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    d) Copy the example code into Hello_world.c in the strikers project .Right click strikers and build the project and thenright click strikers => Run as => Nios II Hardware

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    NIOS II Software Build Tools for Eclipes

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    e) Wait for a moment then you can see the following image alerting you thatNo Nios II target connection paths were located .Select the Target Connection tab, and c heck the two boxes below

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    NIOS II Software Build Tools for Eclipes

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    f) Select the Target Connection tab, and then click Refresh Connections.Click Apply, then click Run.

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    NIOS II Software Build Tools for

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    Eclipes

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    When the push button 2 is pressed the motor of the shaft will turn back to 0 degreesAnd the regulator turns OFF.


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