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Laboratoire de l’Accélérateur Linéaire (IN2P3-CNRS) Orsay, France
LHCb upgrade meeting
PackingPacking
Chiche RonicCaceres ThierryDuarte Olivier
Olivier Duarte LHCb upgrade meeting 2
SSchedule for SPECS developmentchedule for SPECS developmentCROC prototype tests : CROC prototype tests : sschedulecheduleData flow and firmware architectureData flow and firmware architecture
BXId
12
1 byte
February 11th 2011
ADC 12b@40MSPS
ADC 12b@40MSPS
ADC 12b@40MSPS
ADC 12b@40MSPS
ADC 12b@40MSPS
ADC 12b@40MSPS
ADC 12b@40MSPS
ADC 12b@40MSPS
12
12
12
12
12
12
12
A3PE1500 FPGA
BXId and Energy calculation
Energy Mapping 8 Shorts ADC
1 byte 1 byte 5 bytes 2 bytes
2 long ADC
8 to 16 byte @40MSPS
Data compression
Dat
a re
gist
erD
ata
regi
ster
Mux
Buffe
r RAM
Packing
Optical link
..
..
GBTMulti-Gb/sData Transmission
..
..10 byte @80MSPS
10 byte @40MSPS
Output data format :Bu
ffer R
AM
Event counter (350)
Formatting ADC datas(pipeline)
Olivier Duarte LHCb upgrade meeting 3
SSchedule for SPECS developmentchedule for SPECS developmentCROC prototype tests : CROC prototype tests : sschedulecheduleFirmware architecture and data sizeFirmware architecture and data size
February 11th 2011
(x8) ADC 12b@40MSPS
Short
12 12 12 12 12 12 12 12
Packing
Comparator
Long Mapping
Shift
BXId and Energy calculation
BXId
1 byte
Energy Mapping 8 Shorts ADC
1 byte 1 byte 5 bytes 0 to 8 bytes
long ADC
8 to 16 bytes @40MSPS
Short (
5 bit)
Pedestal -8
Pedestal +23
Long (12 bit)
Comparator
Formatting ADC datas
Olivier Duarte
Firmware : data flow packing Firmware : data flow packing proposal proposal
LHCb upgrade meeting 4February 11th 2011
16
12
8
15
Circular buffer (32 x 8 bits)
State Machine@ 80Mhz
P : Wr pointerN : length word I : Rd pointer
P I
10 b
ytes
regi
ster
10 b
ytes
regi
ster
RAM
buff
er
BXId
1 by
te
Ener
gyM
appi
ng8
Shor
ts A
DC
1 by
te1
byte
5 by
tes
0 to
8 b
ytes
long
AD
C
N = 8 to 16 bytes
10 bytes @80MSPS
RAM
buff
er
Form
atting
AD
C da
tas
Event Data flow
Mux
GBTM
ux
40Mhz 80Mhz 40Mhz
PN
I
N
PN-1
PN+1
350 Events
350 Events
? Data ?
Olivier Duarte
Firmware : State Machine Firmware : State Machine - Rd/Wr circular buffer - Rd/Wr circular buffer
- Wr RAM buffer, Rd ? - Wr RAM buffer, Rd ?
LHCb upgrade meeting 5February 11th 2011
t0
t1
t2t3 t4
Idle
- Rd de la longueur du mot N- Wr du mot de longueur N dans buffer circulaire- Calcul de S = P + N – I comparé à 10, 20; Avec P : Pointeur de Wr N : Longueur du mot Wr I : pointeur de Rd
S 10 10 ≤ S 20 S ≥ 20
Start Acq
Stop Acq
- Lecture de 10 bytes du buffer circulaire- Increment (I + 10)
- Lecture de 2x 10 bytes du buffer circulaire- Increment (I + 20)
Clock state machine 80 Mhz Clock event 40 Mhz
Calcul " longueur d’occupation S "
Olivier Duarte LHCb upgrade meeting 6
SPARESPARE
December 10th 2010
Olivier Duarte LHCb upgrade meeting 7
SSchedule for SPECS developmentchedule for SPECS developmentCROC prototype tests : CROC prototype tests : sschedulecheduleADC comparator to short, longADC comparator to short, long
February 11th 2011
Short (
5 bit)Pedestal
Pedestal -8
Pedestal +23
Long (12 bit)
Long (12 bit)
t0
t1
t2t3 t4
S = P + N – I
S 10
10 ≤ S 20S ≥ 20
Start Acq
Stop Acq
Rd 10 bytes(I + 10)
Rd 20 bytes(I + 20)