Laboratories and Materials Teaching Hardware-Software Co-Design

8/2/2001 NSF-CCLI Seminar

University of Missouri-Rolla

Laboratories and Materials Laboratories and Materials Teaching Hardware-Teaching Hardware-Software Co-DesignSoftware Co-Design

D.G. Beetner and H.J. PottingerD.G. Beetner and H.J. PottingerElectrical and Computer EngineeringElectrical and Computer Engineering

University of Missouri-RollaUniversity of Missouri-Rolla

8/2/2001 NSF-CCLI Seminar, sld 2


OutlineOutline

Background and MotivationBackground and Motivation OverviewOverview Introductory ExampleIntroductory Example Laboratory ExercisesLaboratory Exercises Detailed ExampleDetailed Example EvaluationEvaluation



BackgroundBackground Hardware and software developed Hardware and software developed

separately in pastseparately in past Increasingly riskyIncreasingly risky

– Systems on a ChipSystems on a Chip– Short market windowsShort market windows– Difficult to partition hardware and Difficult to partition hardware and

softwaresoftware Co-Design reduces number of Co-Design reduces number of

prototypes and time-to-marketprototypes and time-to-market Rapidly growing demandRapidly growing demand



BackgroundBackground

Hardware-Software Co-design Hardware-Software Co-design fundamental to digital systems fundamental to digital systems designdesign

Undergraduates in CpE, EE, and CS Undergraduates in CpE, EE, and CS should be introduced to this conceptshould be introduced to this concept

Developed software and laboratories Developed software and laboratories which introduce Co-design at the which introduce Co-design at the junior leveljunior level



Laboratory ObjectiveLaboratory Objective Teach concepts of microcontrollers Teach concepts of microcontrollers

and hardware-software co-designand hardware-software co-design– Hardware-Software partitioningHardware-Software partitioning– Re-use of intellectual property (IP)Re-use of intellectual property (IP)– Hardware-Software co-simulationHardware-Software co-simulation– Embedded software in C and ASMEmbedded software in C and ASM– Communication with external devicesCommunication with external devices– Real-time systemsReal-time systems



Course DesignCourse Design Associated courseAssociated course

– Junior levelJunior level– Focused on 8051 microcontrollerFocused on 8051 microcontroller– Mix of CpE, EE, and CS studentsMix of CpE, EE, and CS students– Lab is not requiredLab is not required

Student backgroundStudent background– C++C++– Electronic design automation toolsElectronic design automation tools– Rapid prototyping with FPGAsRapid prototyping with FPGAs



Experiment OutlineExperiment Outline

Develop and simulate softwareDevelop and simulate software Develop and simulate hardwareDevelop and simulate hardware Co-simulate hardware and Co-simulate hardware and

softwaresoftware Verify design in hardwareVerify design in hardware



Laboratory EquipmentLaboratory Equipment

Keil Software Keil Software DevelopmenDevelopment Toolst Tools– C and ASMC and ASM– 8051 8051

software software simulationsimulation

– Free Free evaluation evaluation softwaresoftware



Laboratory EquipmentLaboratory Equipment Mentor Graphics Mentor Graphics

design design automation toolsautomation tools

8051 simulation 8051 simulation modelmodel– Clock-cycle Clock-cycle

accurateaccurate– Executes Executes

compiler-compiler-generated codegenerated code

– Complete Complete functionalityfunctionality



Laboratory EquipmentLaboratory Equipment Mentor Graphics Mentor Graphics

design design automation toolsautomation tools

8051 simulation 8051 simulation modelmodel– Clock-cycle Clock-cycle

accurateaccurate– Executes Executes

compiler-compiler-generated codegenerated code

– Complete Complete functionalityfunctionality



Laboratory EquipmentLaboratory Equipment

XS40 board by XS40 board by Xess Xess corporationcorporation– 8031 8031

microcontrollermicrocontroller– Xilinx FPGAXilinx FPGA– VGA portVGA port– 7-segment LED7-segment LED– Generous pin-Generous pin-

probe pointsprobe points



ExperimentsExperiments

Several labs developedSeveral labs developed– Introduction to Hardware-Software Co-Introduction to Hardware-Software Co-

SimulationSimulation– Hardware-Software Co-VerificationHardware-Software Co-Verification– Extending the 8051 with External Extending the 8051 with External

HardwareHardware– Design with intellectual property: Design with intellectual property:

Creating a VGA displayCreating a VGA display– Bi-directional serial communication with Bi-directional serial communication with

interruptsinterrupts



ProjectsProjects

Digital LCD Digital LCD alarm clockalarm clock

Virtual petVirtual pet MP3 player MP3 player

controllercontroller ““Pong” gamePong” game Automatic pet Automatic pet

feederfeeder Simon gameSimon game



Introductory Example: Introductory Example: 7SegDisp7SegDisp

Objectives:Objectives:– Instructor’s overview of:Instructor’s overview of:

8051 model usage8051 model usageCo-verification methodologyCo-verification methodology

– Extension to exclusive VHDL approachExtension to exclusive VHDL approach Implement:Implement:

– 8051 address latch8051 address latch– Seven segment display output portSeven segment display output port



7SegDisp Overview7SegDisp Overview

Similar to UMR Lab Exercise #4Similar to UMR Lab Exercise #4– A collage of labs 1, 4, and 5A collage of labs 1, 4, and 5– Construct an eight bit latch for use as:Construct an eight bit latch for use as:

Address latch for 8051 expanded modeAddress latch for 8051 expanded mode Output port for seven segment display on XS40Output port for seven segment display on XS40

– Construct an address decoder for output port at Construct an address decoder for output port at 0x7F550x7F55

– Interface to XS40 starting frame model Interface to XS40 starting frame model – Write and test C program to display messageWrite and test C program to display message– Simulate entire system and test on XS40 Simulate entire system and test on XS40

hardwarehardware



Block Diagram of Block Diagram of 7SegDisp7SegDisp

FPGA

P2

P0

ALE

WRnDecoder8051

Display

Sram

CSOE

A D

PSEN

PSEN

A15

Latch8

Latch8

G

G P0

A(15:0)

D

D

Q

Q

=7F55H



7SegDisp Specifications7SegDisp Specifications

Must execute 8051 code from XS40 Must execute 8051 code from XS40 SramSram

Sram is 32k bytes from 0x0000 to Sram is 32k bytes from 0x0000 to 0x7FFF0x7FFF

Latch data for seven segment displayLatch data for seven segment display Display port in xdata at address 0x7F55Display port in xdata at address 0x7F55 Software to display “0123456789” Software to display “0123456789”

continuously at one second intervalscontinuously at one second intervals



Lab Sequence OverviewLab Sequence Overview

1.1. Eight bit latch designEight bit latch design2.2. Intro to H/W S/W Co-simulationIntro to H/W S/W Co-simulation3.3. Hardware verification of Gnome S/WHardware verification of Gnome S/W4.4. Extending the 8051Extending the 80515.5. Single chip memory spaces for 8051Single chip memory spaces for 80516.6. Design with IP – a VGA controllerDesign with IP – a VGA controller7.7. Bidirectional Serial I/O using Bidirectional Serial I/O using

interruptsinterrupts



Ex 1: Eight Bit Latch Ex 1: Eight Bit Latch DesignDesign

8-bit parallel port using an FPGA8-bit parallel port using an FPGA Re-familiarize with Design ArchitectRe-familiarize with Design Architect Simulate hardware with QuicksimSimulate hardware with Quicksim Familiarization with XS40 boardFamiliarization with XS40 board Use a PC to provide stimulus to Use a PC to provide stimulus to

hardwarehardware Compare hardware and simulation Compare hardware and simulation

model responsemodel response



Ex 2: Intro to Co-Ex 2: Intro to Co-simulationsimulation

Write assembly program to multiply Write assembly program to multiply two 4-bit numberstwo 4-bit numbers

Hand assemble and create Intel hex Hand assemble and create Intel hex filefile

Verify using a hardware modelVerify using a hardware model Illustrate importance of simulationIllustrate importance of simulation Currently using Xess’ GNOME Currently using Xess’ GNOME

processorprocessor



Ex 3: Hardware Ex 3: Hardware VerificationVerification

Familiarization with XS40 BoardFamiliarization with XS40 Board Tradeoffs between simulation and Tradeoffs between simulation and

hardware testinghardware testing Use of oscilloscope and logic analyzerUse of oscilloscope and logic analyzer ‘‘Fix’ unexpected change in hardwareFix’ unexpected change in hardware Infer internal behavior by observing Infer internal behavior by observing

external signalsexternal signals



Ex 4: Extending the 8051Ex 4: Extending the 8051

Add address latch and external output Add address latch and external output portport

Improve hardware-software design skillsImprove hardware-software design skills Demultiplex 8051 address/data busDemultiplex 8051 address/data bus Observe timing of 8051 bus signalsObserve timing of 8051 bus signals Introduce 8051 simulation modelIntroduce 8051 simulation model More familiarization with XS40 boardMore familiarization with XS40 board



Ex 5: Single Chip Memory Ex 5: Single Chip Memory SpacesSpaces

Implement xdata and code space in SRAMImplement xdata and code space in SRAM– Xdata at 0x5000Xdata at 0x5000– Code at 0x0000Code at 0x0000

Write message display program in assembly Write message display program in assembly languagelanguage

Use of software development toolsUse of software development tools Illustrate importance of hardware/software co-Illustrate importance of hardware/software co-

verificationverification Students write software and make small Students write software and make small

modification to previous hardware designmodification to previous hardware design



Ex 6: Design with IPEx 6: Design with IP

Develop interface to a VGA controller soft Develop interface to a VGA controller soft macromacro– VGA core implements 16 x 8 character displayVGA core implements 16 x 8 character display

Write message display program in C for Write message display program in C for 80518051

Reinforces importance of co-verificationReinforces importance of co-verification– VGA core is a ‘non-standard’ 8051 peripheralVGA core is a ‘non-standard’ 8051 peripheral– Need to verify both HW and SW operating Need to verify both HW and SW operating

togethertogether



Ex 7: Serial Ex 7: Serial CommunicationCommunication

Bi-directional comm with two serial Bi-directional comm with two serial portsports

Design system that can communicate Design system that can communicate with another group’s XS40 boardwith another group’s XS40 board

Use interrupts to service serial portUse interrupts to service serial port Design re-use (modification of lab 6)Design re-use (modification of lab 6) Re-inforce co-verification techniquesRe-inforce co-verification techniques Improve C programming skillsImprove C programming skills



HW-SW Co-design ProcessHW-SW Co-design Process

Specification

Edit Compile Debug

Capture Simulate

Integrate Hardware and Software

Place and Route

Hardware Verification




Specification

Edit Compile Debug

Capture Simulate


Place and Route


Keil vision:• IDE• C51• dScope




Specification

Edit Compile Debug

Capture Simulate


Place and Route


Mentor:• Design Arch• Quicksim




Specification

Edit Compile Debug

Capture Simulate


Place and Route


QuicksimPro:• Quicksim &• Modeltech




Specification

Edit Compile Debug

Capture Simulate


Place and Route


XilinxAlliance



Hello World ProgramHello World Program

#define SEG7 XBYTE[0x7F55]void main (){static code char msgtxt[]= "0123456789";char code *cptr;TMOD=0x01; /* 16bit timer mode */while (1) { cptr= msgtxt; while(*cptr){ SEG7= decode(*cptr++);// pause between characters#ifndef SIMULATION delay(2); SEG7= 0; delay(1);#endif } /* while (*cptr) */ } /* while(1) */}

Specification:Display each char of message for two secondsWith a one second pause in betweenSeven segment display port at 0x7f55Bit 0 is segment a, bit 6 is segment g

Get next char

Lookup segment values

Pause if not simulating

Done?no



Keil Keil vision IDEvision IDE



Keil Keil vision Debuggervision Debugger



Lab 4 Starting FrameLab 4 Starting Frame

Archive file with simulation model etc.Archive file with simulation model etc.– XS40 schematic modelXS40 schematic model

8051 model8051 model32k sram model32k sram modelClock, seven segment display, etc modelsClock, seven segment display, etc models

– XC4005 FPGA starting frameXC4005 FPGA starting frame Hello world hex object file: Hello world hex object file: hello.hexhello.hex Results of previous lab: Results of previous lab: eight bit latcheight bit latch

XS40 Schematic modelXS40 Schematic model



8051 Model8051 Model

8051 Schematic symbol is linked to 8051 Schematic symbol is linked to an underlying VHDL behavioral an underlying VHDL behavioral modelmodel



Sram model (1)Sram model (1)

Sram symbol

Sram wrapper

Address map



Sram model (2)Sram model (2)

SRAM model is a modified version SRAM model is a modified version of Andre Klindworth’s VHDL modelof Andre Klindworth’s VHDL model



XC4005 Starting FrameXC4005 Starting Frame



Address latch sample Address latch sample solutionssolutions

Typical student solution

The answer book!



Sample solution for Sample solution for mydecodermydecoder

Finished FPGA schematic Finished FPGA schematic modelmodel

Screen shot of finished xc4005Screen shot of finished xc4005



Closeup of finished Closeup of finished schematicschematic



Linking program file to Linking program file to modelmodel

Closeup of Closeup of file file property, property, hello.hex, hello.hex, and dir and dir listinglisting



QSPro SimulatorQSPro Simulator

Mixed Mixed Schematic and Schematic and VHDL modelsVHDL models

Gate level plus Gate level plus VHDL VHDL simulatorsimulator

QSPro startup QSPro startup

QSPro Simulation EnvironmentQSPro Simulation Environment

Screenshot of A typical simulation Screenshot of A typical simulation setupsetup



8051 Startup Timing8051 Startup Timing



7SegDisp Write Cycle7SegDisp Write Cycle

Screen shot of cycle showing a Screen shot of cycle showing a write to 7f55write to 7f55



Lab EquipmentLab Equipment

A picture of a typical A picture of a typical lab setuplab setup



Comparison of Hardware Comparison of Hardware and Simulation Resultsand Simulation Results

Simulation trace

Scope trace



A VHDL-basedA VHDL-basedHW-SW Co-design ProcessHW-SW Co-design Process

Specification

Edit Compile Debug

Edit vsim


Place and Route


software

hardwarevcom

LogicSynthesis



Evaluation Evaluation

Technical accuracy of modelsTechnical accuracy of models Educational effectiveness of labsEducational effectiveness of labs



Evaluation of ModelsEvaluation of Models

Standard software-testing Standard software-testing methodologiesmethodologies– White-box testingWhite-box testing– ASM and VHDL testbenchesASM and VHDL testbenches– Code coverage (line coverage, Code coverage (line coverage,

decision coverage, etc)decision coverage, etc) Evaluation in lab by students and Evaluation in lab by students and

instructors instructors Bugs found and eliminatedBugs found and eliminated



Evaluation of LabsEvaluation of Labs

Compared students who took the lab VS Compared students who took the lab VS those who did notthose who did not

Students who took the lab:Students who took the lab:– Performed 33% better on evaluation examPerformed 33% better on evaluation exam– Received 20-30% higher final grade in Received 20-30% higher final grade in

lecture course lecture course About 1 letter grades higher on testsAbout 1 letter grades higher on tests

Little difference between students in Little difference between students in other CpE coursesother CpE courses



AcknowledgementsAcknowledgements

National Science Foundation Course National Science Foundation Course Curriculum and Laboratory Curriculum and Laboratory Improvement program, DUE-9952540Improvement program, DUE-9952540

Mentor GraphicsMentor Graphics Keil SoftwareKeil Software Jim Frenzel, University of IdahoJim Frenzel, University of Idaho Dave Van Den Bout, XESS Corp.Dave Van Den Bout, XESS Corp. XilinxXilinx



Mentor Graphics Higher Mentor Graphics Higher Education Program (HEP)Education Program (HEP)

Includes all of Mentor Graphics’ EDA Includes all of Mentor Graphics’ EDA toolstools

$2100 per year for 10 seats$2100 per year for 10 seats Free training classesFree training classes Very active university support groupVery active university support group Contact: Contact:

[email protected][email protected] post to [email protected] post to [email protected]



Xilinx University Program Xilinx University Program (XUP)(XUP)

Contact: Contact:

[email protected]@xilinx.comor http://www.xilinx.com/univ/or http://www.xilinx.com/univ/



Questions/Comments ?Questions/Comments ?

Submit questions/commentsSubmit questions/comments– Using “chat” screenUsing “chat” screen– Via email:Via email:

[email protected]@[email protected]@umr.edu

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Laboratories and Materials Teaching Hardware-Software Co-Design

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