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Lag Controller Design

Date post: 30-Jan-2016
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Lag Controller Design. z/p=40. z/p=20. z/p=10. z = w gcd /5. w gcd. z/p=5. Kill PM by 10 to 12 deg. z/p=40. z/p=20. z/p=10. z = w gcd /10. w gcd. z/p=5. Kill PM by 5 to 7 deg. z/p=40. Want these: DC gain boosting. z/p=20. z/p=10. z = w gcd /20. z/p=5. w gcd. - PowerPoint PPT Presentation
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lag lag p s z s K s C ) ( Lag Controller Design 0 0 K p z lag lag K p z K p j z j K j C lag lag lag lag 0 ) ( ing destabiliz p z j C lag lag , 0 ) ( tan ) ( tan ) ( 1 1
Transcript
Page 1: Lag Controller Design

lag

lag

ps

zsKsC

)(

Lag Controller Design

00 Kpz laglag

Kp

zK

pj

zjKjC

lag

lag

lag

lag

0)(

ingdestabilizpz

jClaglag

,0)(tan)(tan)( 11

Page 2: Lag Controller Design

0

10

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40M

agn

itu

de

(dB

)

10-4

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-30

0

Ph

ase

(deg

)Bode Diagram

Frequency (rad/sec)

gcd

zgcd/5

Kill PM by 10 to 12 deg

z/p=5

z/p=10

z/p=20

z/p=40

Page 3: Lag Controller Design

0

10

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40M

agn

itu

de

(dB

)

10-4

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0

Ph

ase

(deg

)Bode Diagram

Frequency (rad/sec)

gcd

zgcd/10

Kill PM by 5 to 7 deg

z/p=5

z/p=10

z/p=20

z/p=40

Page 4: Lag Controller Design

0

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35M

agn

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(dB

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10-5

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ase

(deg

)Bode Diagram

Frequency (rad/sec)

gcd

zgcd/20

Kill PM by 2 to 3 deg

z/p=5

z/p=10

z/p=20

z/p=40

Want these:DC gain boosting

Don’t want these:PM reduction!

Page 5: Lag Controller Design

Lag and lead-lag Design Steps• From plant, draw Bode plot

• From specs => PMd and gcd

– If there is speed or BW req, gcd, • In this case, if PM not enough, design PD or lead

– Otherwise, choose gcd to have PM>PMd

• Find K to enforce gcd:

• Find Kp,v,a-have with K and C above

• Find Kp,v,a-des from ess specs

• zlag/plag = Kp,v,a-des/Kp,v,a-have

• Let zlag= gcd/5~20, depending on PM room

• Compute plag

1gcd )(

jCGK

Page 6: Lag Controller Design

Lag design example• Plant transfer function is given by:

• Desired design specifications are:– Step response overshoot <= 10%– Steady state tracking error to ramp input is

<=0.01

)1)(1(

1)(

501

51

sss

sG

Note: no speed or BW requirement, so just choose wgcd to have enough PM

Page 7: Lag Controller Design

n=[1]; d=[1/5/50 1/5+1/50 1 0];figure(1); clf; margin(n,d);%proportional control design:figure(1); hold on; grid; V=axis;Mp = 10/100;zeta = sqrt((log(Mp))^2/(pi^2+(log(Mp))^2));PMd = zeta * 100 + 3;semilogx(V(1:2), [PMd-180 PMd-180],':r');%get desired w_gcx=ginput(1); w_gcd = x(1);K = 1/abs(polyval(n,j*w_gcd)/polyval(d,j*w_gcd));Kva = K*n(end)/d(end-1); ess=0.01; Kvd=1/ess;z = w_gcd/5; p = z/(Kvd/Kva);ngc = conv(n, Kp*[1 z]); dgc = conv(d, [1 p]);figure(1); hold on; margin(ngc,dgc);[ncl,dcl]=feedback(ngc,dgc,1,1);figure(2); step(ncl,dcl); grid;figure(3); margin(ncl*1.414,dcl); grid;

Page 8: Lag Controller Design

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Mag

nit

ud

e (d

B)

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ase

(deg

)

Bode DiagramGm = 34.8 dB (at 15.8 rad/sec) , Pm = 77.8 deg (at 0.981 rad/sec)

Frequency (rad/sec)

Page 9: Lag Controller Design

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(deg

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Bode DiagramGm = 26 dB (at 15 rad/sec) , Pm = 51.7 deg (at 2.31 rad/sec)

Frequency (rad/sec)

Page 10: Lag Controller Design

0 2 4 6 8 10 120

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1.4Step Response

Time (sec)

Am

plit

ud

e

Page 11: Lag Controller Design

n=[1]; d=[1/5/50 1/5+1/50 1 0];figure(1); clf; margin(n,d); hold on; grid; V=axis;Mp = 10/100; zeta = sqrt((log(Mp))^2/(pi^2+(log(Mp))^2));PMd = zeta * 100 + 3;semilogx(V(1:2), [PMd-180 PMd-180],':r');x=ginput(1); w_gcd = x(1); %get desired w_gcK = 1/abs(polyval(n,j*w_gcd)/polyval(d,j*w_gcd));Kva = K*n(end)/d(end-1); ess=0.01; Kvd=1/ess;z = w_gcd/10; p = z/(Kvd/Kva);ngc = conv(n, K*[1 z]); dgc = conv(d, [1 p]);figure(1); hold on; margin(ngc,dgc);[ncl,dcl]=feedback(ngc,dgc,1,1);figure(2);step(ncl,dcl); grid;figure(3); margin(ncl*1.414,dcl); grid;

Page 12: Lag Controller Design

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(dB

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(deg

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Bode DiagramGm = 27.7 dB (at 15.5 rad/sec) , Pm = 60.2 deg (at 2.01 rad/sec)

Frequency (rad/sec)

Page 13: Lag Controller Design

0 5 10 15 20 250

0.2

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1.4Step Response

Time (sec)

Am

plit

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Page 14: Lag Controller Design

clear all; n=[1]; d=[1/5/50 1/5+1/50 1 0];figure(1); clf; margin(n,d); grid; V=axis; hold on; Mp = 10/100; zeta =sqrt((log(Mp))^2/(pi^2+(log(Mp))^2));PMd = zeta * 100 + 7;semilogx(V(1:2), [PMd-180 PMd-180],':r');x=ginput(1); w_gcd = x(1); %get desired w_gcK = 1/abs(polyval(n,j*w_gcd)/polyval(d,j*w_gcd));Kva = K*n(end)/d(end-1); ess=0.01; Kvd=1/ess;z = w_gcd/10; p = z/(Kvd/Kva);ngc = conv(n, K*[1 z]); dgc = conv(d, [1 p]);figure(1); hold on; margin(ngc,dgc);[ncl,dcl]=feedback(ngc,dgc,1,1);figure(2);step(ncl,dcl); grid;figure(3); margin(ncl*1.414,dcl); grid;

Page 15: Lag Controller Design

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Bode DiagramGm = 31.2 dB (at 15.6 rad/sec) , Pm = 66.9 deg (at 1.42 rad/sec)

Frequency (rad/sec)

Page 16: Lag Controller Design

0 5 10 15 20 250

0.2

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1

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1.4Step Response

Time (sec)

Am

plit

ud

e

Page 17: Lag Controller Design

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(deg

)

Bode DiagramGm = 27.9 dB (at 15.6 rad/sec) , Pm = 98.2 deg (at 2.18 rad/sec)

Frequency (rad/sec)

Page 18: Lag Controller Design

Lead-Lag design example• Plant transfer function is given by:

• Desired design specifications are:– Step response overshoot <= 16%– Step response rise time <= 2 sec– Steady state tracking error to unit acceleration

input is <=1

)5(

1)(

2

sssG

Note: we have all three types of specs: speed, relative stability, and tracking

Page 19: Lag Controller Design

Strategy

• First do a lead design to fix speed and overshoot requirement

• Then do a lag design to fix the ess.

Page 20: Lag Controller Design

n=[1]; d=[1 5 0 0];figure(1); clf; margin(n,d); grid; hold on;Mp=16/100; zeta = sqrt((log(Mp))^2/(pi^2+(log(Mp))^2));PMd = zeta * 100 + 5;tr = 2; wn = 1.8/tr; w_gcd = wn*0.8;PM = pi+angle(polyval(n,j*w_gcd)/polyval(d,j*w_gcd));phimax = PMd*pi/180-PM;alpha=(1+sin(phimax))/(1-sin(phimax));zlead=w_gcd/sqrt(alpha); plead=w_gcd*sqrt(alpha);K=sqrt(alpha)/(abs(evalfr(tf(n,d),j*w_gcd)));ngc = conv(n, K*[1 zlead]); dgc = conv(d, [1 plead]);figure(1); margin(ngc,dgc);[ncl,dcl]=feedback(ngc,dgc,1,1);figure(2); step(ncl,dcl); grid;figure(3); margin(ncl*1.414,dcl); grid;

Page 21: Lag Controller Design

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Bode DiagramGm = 20.1 dB (at 3.74 rad/sec) , Pm = 55.4 deg (at 0.72 rad/sec)

Frequency (rad/sec)

Page 22: Lag Controller Design

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Page 23: Lag Controller Design

Overshoot is too large.

Plus, we know the lag controller will further deteriorate Mp.

So, redesign for better Mp.

Page 24: Lag Controller Design

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Bode DiagramGm = 22.4 dB (at 4.89 rad/sec) , Pm = 65.4 deg (at 0.72 rad/sec)

Frequency (rad/sec)

Page 25: Lag Controller Design

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Bode DiagramGm = 18.7 dB (at 4.89 rad/sec) , Pm = 96.5 deg (at 1.14 rad/sec)

Frequency (rad/sec)

Page 26: Lag Controller Design

0 5 10 15 20 25 30 35 400

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About 12% overshoot.So, let’s go ahead with lag design.

Page 27: Lag Controller Design

Kaa = ngc(end)/dgc(end-2); ess=1; Kad=1/ess;zlag = w_gcd/20; plag = zlag/(Kad/Kaa);ngcc = conv(ngc, [1 zlag]); dgcc = conv(dgc, [1 plag]);figure(1); margin(ngcc,dgcc);[ncl,dcl]=feedback(ngcc,dgcc,1,1);figure(4); step(ncl,dcl); grid;figure(5); margin(ncl*1.414,dcl); grid;

We don’t have too much room to spare for Mp, so choose 20 so that the lag controller only kills about 3 degrees of PM.

Page 28: Lag Controller Design

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Bode DiagramGm = 22.3 dB (at 4.86 rad/sec) , Pm = 62.7 deg (at 0.721 rad/sec)

Frequency (rad/sec)

Page 29: Lag Controller Design

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Bode DiagramGm = 18.6 dB (at 4.86 rad/sec) , Pm = 93.4 deg (at 1.17 rad/sec)

Frequency (rad/sec)

Page 30: Lag Controller Design

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