Large Signal Amplifiers v2011 - Explore RF

Department of Electrical and Electronic Engineering

Large Signal Amplifiers Design

Laboratory

Electronics 2

1 Introduction

When viewed as a system component, an amplifier is a device whose function is to increase

the level of a signal. Many amplifiers are required to operate only at low signal power levels,

where both the power drain from the DC supply and also the power dissipation within the

amplifier circuit itself are of little consequence.

An amplifier can also be viewed as an energy converter, where energy is drawn from a DC

supply and converted into signal energy that is delivered to the load. Inevitably this

conversion process is imperfect, and some energy is dissipated within the amplifier circuit as

heat. When an amplifier is required to deliver appreciable signal power to the load, the

efficiency of the conversion process assumes considerable importance because of the need to

remove the heat generated within the amplifier, and, in the case of battery powered equipment

especially, because of the need to minimise the power drawn from the supply.

In this project, you are required to design and investigate the behaviour of both class A and

class B output stages.

2 General remarks on the project

Two sessions are available for the completion of this project. During the first session you

should build the class A amplifier, measure and analyse its large signal behaviour, and

develop design equations which enable the circuit to be optimised to work at a different

maximum power level. In the second session, the design of the complimentary class B

amplifier should be considered, and comparisons can then be made with the performance of

the class A stage. Record in your lab book all experimental work, results and

observations. Your lab book is to be handed in on the Thursday after you have attended

both lab sessions.

In this project, we are interested in comparing the two circuits primarily in terms of their

output efficiency, defined in Appendix 1. Also, it is important to calculate the power

dissipated in the circuit components so that adequate power ratings can be specified. For the

sake of simplicity we will ignore the power consumed by the base biasing arrangements for

each circuit, since optimum design of these component values raises the question of bias point

stability.

3 The class A amplifier

3.1 Experiments

Design a common collector (emitter follower) class A amplifier and construct it on the

prototyping board. This amplifier should be designed to operate from a 12V supply with a

quiescent current IC of approximately 50mA. The transistor which should be used in your

designs is shown with its lead arrangement in Figure 1.

CB

E

Figure 1 Transistor connections

The amplifier circuit diagram is shown in Figure 2, you should calculate the values of R1 and

R2 to achieve the specified bias conditions. The digital multi meter should be connected to the

collector circuit and should be set to DC current mA, with the auto ranging function activated.

+VCC

0V

A

RLRE vE

vL

vCE

iC

- ++

- +

+

-

+

-

C1

C2

V =12VCC

R =150E ΩR =100L Ω

C =C =10 F1 2 µ

R1

R2

Figure 2 Class A Emitter Follower

E-Line Outline

ZTX 651 (npn)

ZTX 751 (pnp)

3.1.1 Set the power supply to +12V, and record the quiescent values of vB, vE, and IC with

zero input signal.

VCC = V

vB = VBQ = V

vE = VEQ = V

iC = ICQ = mA

vBE = vB – vE = V

Apply a sinusoidal input signal at 3kHz with an input amplitude which is sufficiently

large to produce a voltage at the output of 2V peak to peak. Referring to the

definitions in Appendix 1, calculate the following power components.

Supply power PSS = mW

Load signal power PL = mW

Emitter resistor dissipation

(a) Due to bias, PEB = mW

(b) Due to signal, PES = mW

Transistor dissipation, PT = mW

Efficiency, η = %

3.1.2 Increase the amplitude of the input signal until vE and vL just become non-sinusoidal

on the negative-going excursion.

Note the peak load voltage, LMV∧

, that can be obtained before distortion becomes

apparent:

LMV∧

= V

Observe the average collector current reading as the output signal amplitude is

adjusted over the range 0 < L

^

v < LMV∧

Calculate the power components for the peak undistorted output signal, LMV∧

.

PSS = mW

PL = mW

(a) PEB = mW

(b) PES = mW

PT = mW

η = %

3.1.3 Referring to Figure 3, and taking measurements of vE and vL from the CRO screen,

draw one cycle of the current waveforms iL, i1 and iE to scale using a common axes.

0V

RLREvE

vL

+

-

+

-

iE

iL

i1

Figure 3 Class A emitter follower load circuit

3.1.4 Observe vE and vL, using DC coupled oscilloscope channels, as the input signal

amplitude is increased still further so that ‘approximately’ linear sections appear in

the distorted part of the output waveforms. Figure 4 shows the type of distortion to

expect.

Draw one cycle of vE and vL on common axes, paying particular attention to the form

of the distorted section of the waveforms.

Examine the relationship between iL, i1 and iE in the distorted section of the

waveforms.

To explain the circuit behaviour it will also be helpful to observe the transistor base

and emitter voltages simultaneously (using DC coupling and a common 0V reference

on the oscilloscope screen) so that the base-emitter voltage variation, vB – vE, can be

deduced.

Figure 4 Emitter Follower output voltage waveforms

3.2 Discussion

It should be clear that the distortion occurs on the negative waveform excursion when iE = 0,

whence i1 = -iL.

What circuit conditions would give rise to clipping on the positive waveform excursion?

In practice, the quiescent bias point would be chosen so that vCE never reduces below some

minimum level, VCEM, on the positive waveform excursion. Typically, VCEM > 1V.

0V

VCEM

vE

VCC

vEMAX

vEMIN

allowable variation of vE

Figure 5 Allowable variation of vE

Figure 5 shows the limits on the variation of vE, in relation to VCC, to avoid clipping the output

waveform.

vE vL

A design specification includes the load resistance, RL, and the maximum load power

requirement, PLMAX. On the basis that the amplifier operates at its best efficiency when the

maximum signal variation required in the load also corresponds to the maximum signal

variation obtainable without clipping, the task of the designer is to determine an appropriate

bias condition for the transistor.

We have,

L

2

LM

LMAXR2

VP

∧

= (1)

from the statement above,

LMEMINEMAX V2∧

=− vv (2)

At the onset of negative clipping, 0E =i , L1 ii −=∴ , and

L

LMLMMIN1

R

V∧

∧

=

−−= Ii

Now EMIN1EMIN Riv =

∴ L

ELMEMIN

R

RV ⋅=∧

v (3)

From Figure 5,

( ) CEMEMINEMAXEMINCC VV +−+= vvv

Substituting from (2) and (3) gives

CEMLM

L

ELMCC VV2

R

RVV ++⋅=

∧∧

(4)

Also, the quiescent conditions are

LMEMINEQ VV∧

+= v

i.e.

+=

L

ELMEQ

R

R1VV (5)

and

+⋅==

∧

LE

LM

E

EQ

EQR

1

R

1V

R

VI (6)

The supply power, CCCSS iVP−

⋅=

i.e. ECCSS iVP−

⋅≈

∴ EQCCSS IVP ⋅≈ (7)

If CCV is specified by other elements in a system, then the supply power can only be

minimised within this constraint by choosing the minimum value of EQI . From equation (6),

since LMV∧

and LR are specified, ER should be as large as possible to minimise EQI . This

means that EQv is as large as possible, from (5). This condition was used in the derivation of

equation (4) so a value of ER derived from equation (4) will indeed lead to the minimum

supply power requirement, given that CCV is fixed.

If the design is not constrained by the predetermined supply voltage, then the question arises:

is there a value of supply voltage that minimises the supply power that is necessary to provide

the specified maximum load power? This question is particularly important in the design of

battery portable equipment, and the answer is that an optimum value of CCV can be

calculated, and so the best standard battery voltage can be specified. It can be shown that the

maximum efficiency for a capacitively coupled loads, assuming that 0VCEM = and that the

optimum supply voltage is used, is 8.5%!

3.3 Design example

Redesign the class A emitter follower output stage so that it will deliver a maximum power of

5mW into a capacitively coupled 100Ω load. Assuming that V5.1VCEM = , choose the

battery voltage (in increments of 1.5V) to minimise the power drain, and note the

corresponding optimum value of ER .

Calculate the power components specified in Appendix 1 and compare them with the results

obtained for a 12V supply, listed in sections 3.1.2 and 3.1.3. Construct and verify the

behaviour of your amplifier

[Hint: Use equations (7), (4) and (6) as the starting point of your analysis to determine a value

of ER that minimises supply power.]

4 The class B emitter follower

4.1 Introduction

The essential features of a class B emitter follower design are shown in Figure 6. The single

transistor and emitter resistor, which were used in the class A design, have been replaced by a

symmetrical configuration of two complimentary transistors. This arrangement has the

interesting property that the relationship between EI vv − and load current, Li , can be made

more or less linear, depending on the chosen base-emitter bias voltage V, for both positive

and negative load current.

+VCC

0V

V

V

iE1

iE2

vIvE vL

iL+

-

+

-

+

-

vBE1

vBE2

Figure 6 Class B emitter follower

It is necessary to operate both transistors in forward bias under zero signal conditions to

reduce ‘crossover distortion’ to an acceptable level. But the quiescent current is only a small

fraction of the maximum signal current required by the load, so the ‘no signal’ power

dissipation is relatively low unlike the class A stage. Also, when a signal is applied, the npn

transistor supplies current to the load on the positive excursion, and the pnp transistor

conducts only a small current (dependent on the bias, V) and thus dissipates relatively little

power. The roles of the two transistors are reversed on the negative signal excursion, resulting

in a practical output efficiency in the region of 70%. This type of operation, which is not

strictly class B because each transistor conducts to some extent for more than 50% of the

signal cycle, is called class AB.

4.2 A practical class B amplifier

Build the circuit shown in Figure 7 on the prototyping board. For experimental purposes, the

values of bias resistors have been chosen so that the base-emitter bias voltage on both

transistors can be varied simultaneously over the range 7.05.0 → Volts simply by adjusting

the supply voltage CCV over the range 1511→ Volts approximately.

+VCC

0V

vI

+

-

vL

+

-A

10 Fµ

10 Fµ

- ++ -

T1

T2

27kΩ

2.7kΩ

2.7kΩ

27kΩ

100Ω

Figure 7 A practical class B amplifier

Set the digital multimeter to DC mA auto ranging and observe the changes in bias

current as the supply voltage is varied over the range 1511→ Volts.

4.2.1 Apply a sine wave input signal, Iv , of amplitude 1V peak at 3kHz. Increase CCV

gradually from 5V whilst observing the form of Lv . Make two or three sketches of

the distorted waveform at different values of CCV , noting the reduction in the

distortion as CCV increases.

Figure 8 Example of cross-over distortion

An example of this ‘cross-over’ distortion is shown in Figure 8. It occurs when one

transistor ceases to conduct before the other starts to conduct.

4.2.2 When the distortion in Lv just disappears, note the value of CCV ; reduce the input

signal, Iv , to zero and measure the collector current.

=CCV V

== CQICi mA

Also, use the digital multimeter to measure the base-emitter voltage of each

transistor.

=1BEv V

=2BEv V

4.2.3 Remove the ammeter and insert a 10Ω resistor in series with each collector. Apply an

input signal and use your observations of the voltages developed at the collector of

each transistor to sketch the form of 1Ci and 2Ci , noting their time relationship.

[make sure that the probe ‘earth’ clip is attached to the 0V rail of the supply for both

measurements].

4.2.4 Reverting to the circuit shown in Figure 7, alter the component values so that the

amplifier will work from a supply voltage in the region of 6V (use preferred value

VCC = 9V

vL

vI

resistors). In this experiment you may vary CCV over a small range to assist in

setting up the desired bias current, but remember that this would be unacceptable in a

practical design. In fact this method of biasing depends critically on the

characteristics of the particular transistors used, and the bias current also varies with

temperature.

Suggest an improvement to the biasing arrangement.

Record the following:

=CCV V

=CQI mA

=∧

LMV V

When LML VV∧∧

= , calculate:

=SSP mW

=LP mW

=η %

Appendix 1

Power definitions for the class A amplifier

In the following definitions, -

v indicates the mean value of the variable v, and ∧

V indicates

the peak amplitude of a sinusoidal variation.

1. Supply power

CCCCCCCSS VVP−−

⋅≈⋅= ii

where =CCV power supply voltage,

=CCi power supply current, and

=Ci collector current

Note that this definition ignores the power consumed by the earlier stages in the amplifier.

2. Load signal power

L

2

L

L

LR2

V

RP ==

2

Lv

3. Emitter resistor dissipation

E

E

RP

2

Ev=

where eEQE V vv +=

Here, =EQV quiescent emitter bias voltage, and

=ev signal voltage variation.

It can be shown that

ESEBE PPP += when 0e =v

where ==E

2

EQ

EBR

VP the emitter bias power dissipation, and

==E

2

eES

R2

VP power dissipation due to the signal across ER .

Note that Lvve= when the effect of the coupling capacitor is negligible.

4. Transistor power dissipation

( )ELSST PPPP +−=

5. Output efficiency

%100P

P

SS

L ×=η

Appendix 2

Resistor Colour Codes

Four Band Resistors

Silver - - 0.01 10%

Gold - - 0.1 5%

Black 0 0 1 -

Brown 1 1 10 1%

Red 2 2 100 2%

Orange 3 3 1k -

Yellow 4 4 10k -

Green 5 5 100k 0.5%

Blue 6 6 1M 0.25%

Purple 7 7 10M 0.1%

Grey 8 8 - -

White 9 9 - -

Colour Significant Figures Multiplier Tolerance

Appendix 3

Transistor Data Sheets

NPN SILICON PLANAR

MEDIUM POWER TRANSISTORSISSUE 2 JULY 94

FEATURES

* 60 Volt VCEO

* 2 Amp continuous current

* Low saturation voltage

* Ptot

=1 Watt

ABSOLUTE MAXIMUM RATINGS.

PARAMETER SYMBOL ZTX650 ZTX651 UNIT

Collector-Base Voltage VCBO 60 80 V

Collector-Emitter Voltage VCEO 45 60 V

Emitter-Base Voltage VEBO 5 V

Peak Pulse Current ICM 6 A

Continuous Collector Current IC 2 A

Power Dissipation at Tamb=25°Cderate above 25°C

Ptot 15.7

WmW/°C

Operating and Storage Temperature Range Tj:Tstg -55 to +200 °C

ELECTRICAL CHARACTERISTICS (at Tamb = 25°C unless otherwise stated).

PARAMETER SYMBOLZTX650 ZTX651

UNIT CONDITIONS.MIN. TYP. MAX. MIN. TYP. MAX.

Collector-BaseBreakdown Voltage

V(BR)CBO 60 80 V IC=100µA

Collector-EmitterBreakdown Voltage

V(BR)CEO 45 60 V IC=10mA*

Emitter-BaseBreakdown Voltage

V(BR)EBO 5 5 V IE=100µA

Collector Cut-OffCurrent

ICBO 0.1

100.1

10

µAµAµAµA

VCB=45VVCB=60VVCB=45V,T

amb=100°C

VCB=60V,Tamb

=100°C

Emitter Cut-OffCurrent

IEBO 0.1 0.1 µA VEB=4V

Collector-EmitterSaturation Voltage

VCE(sat) 0.120.23

0.30.5

0.120.23

0.30.5

VV

IC=1A, IB=100mA*IC=2A, IB=200mA*

Base-Emitter Saturation Voltage

VBE(sat) 0.9 1.25 0.9 1.25 V IC=1A, IB=100mA*

Base-Emitter Turn-On Voltage

VBE(on) 0.8 1 0.8 1 V IC=1A, VCE=2V*

ZTX650ZTX651

3-219

C B E

E-Line

TO92 Compatible


UNIT CONDITIONS.

MIN. TYP. MAX. MIN. TYP. MAX.

TransitionFrequency

fT 140 175 140 175 MHz IC=100mA, VCE=5Vf=100MHz

Switching Times ton 45 45 ns IC=500mA, VCC=10VIB1=IB2=50mA

toff 800 800 ns

Output Capacitance Cobo 30 30 pF VCB=10V f=1MHz

*Measured under pulsed conditions. Pulse width=300µs. Duty cycle ≤ 2%

THERMAL CHARACTERISTICS

PARAMETER SYMBOL MAX. UNIT

Thermal Resistance:Junction to Ambient1Junction to Ambient2Junction to Case

Rth(j-amb)1Rth(j-amb)2

Rth(j-case)

17511670

°C/W°C/W°C/W

Device mounted on P.C.B. with copper equal to 1 sq. Inch minimum.

ZTX650ZTX651

-40 0.0001

Derating curve

T -Temperature (°C)

Max

Pow

er D

issi

patio

n -

(Wat

ts)

Maximum transient thermal impedance

Pulse Width (seconds)

The

rmal

Res

ista

nce

(°C

/W)

10 10010.10.01-20 0 20 40 60 80 100 120 200180160140 0.0010

100

200

D=0.2

D=0.1

Single Pulse

D=0.5

t1

tP

D=t1/tP

1.0

0.5

2.0

1.5

Case temperature

2.5

Ambient temperature

0

D=1 (D.C.)

3-220

NPN SILICON PLANAR


FEATURES

* 60 Volt VCEO



* Ptot

=1 Watt



Collector-Base Voltage VCBO 60 80 V

Collector-Emitter Voltage VCEO 45 60 V

Emitter-Base Voltage VEBO 5 V

Peak Pulse Current ICM 6 A

Continuous Collector Current IC 2 A

Power Dissipation at Tamb=25°Cderate above 25°C

Ptot 15.7

WmW/°C





Collector-BaseBreakdown Voltage

V(BR)CBO 60 80 V IC=100µA

Collector-EmitterBreakdown Voltage

V(BR)CEO 45 60 V IC=10mA*

Emitter-BaseBreakdown Voltage

V(BR)EBO 5 5 V IE=100µA


ICBO 0.1

100.1

10

µAµAµAµA

VCB=45VVCB=60VVCB=45V,T

amb=100°C

VCB=60V,Tamb

=100°C


IEBO 0.1 0.1 µA VEB=4V


VCE(sat) 0.120.23

0.30.5

0.120.23

0.30.5

VV

IC=1A, IB=100mA*IC=2A, IB=200mA*


VBE(sat) 0.9 1.25 0.9 1.25 V IC=1A, IB=100mA*

Base-Emitter Turn-On Voltage

VBE(on) 0.8 1 0.8 1 V IC=1A, VCE=2V*

ZTX650ZTX651

3-219

C B E

E-Line

TO92 Compatible


UNIT CONDITIONS.

MIN. TYP. MAX. MIN. TYP. MAX.

TransitionFrequency

fT 140 175 140 175 MHz IC=100mA, VCE=5Vf=100MHz

Switching Times ton 45 45 ns IC=500mA, VCC=10VIB1=IB2=50mA

toff 800 800 ns

Output Capacitance Cobo 30 30 pF VCB=10V f=1MHz





Rth(j-amb)1Rth(j-amb)2

Rth(j-case)

17511670

°C/W°C/W°C/W


ZTX650ZTX651

-40 0.0001

Derating curve


Max

Pow

er D

issi

patio

n -

(Wat

ts)



The

rmal

Res

ista

nce

(°C

/W)

10 10010.10.01-20 0 20 40 60 80 100 120 200180160140 0.0010

100

200

D=0.2

D=0.1

Single Pulse

D=0.5

t1

tP

D=t1/tP

1.0

0.5

2.0

1.5

Case temperature

2.5

Ambient temperature

0

D=1 (D.C.)

3-220

ZTX650ZTX651

TYPICAL CHARACTERISTICS

VCE(sat) v IC

IC - Collector Current (Amps)

VC

E(sa

t) -

(Vol

ts)

IC -

Col

lect

or C

urre

nt (

Am

ps)

VCE - Collector Voltage (Volts)

Safe Operating Area

1 10 1000.01

0.1

1

10Single Pulse Test at Tamb=25°C

D.C. 1s 100ms 10ms

1.0ms 100µs

ZTX650/51-5

0.01 0.1 101


VBE(sat) v IC

VB

E(sa

t) -

(Vol

ts)


hFE v IC

hFE

- G

ain

0.01 100.1 1

VCE=2V

0.6

0.8

1.0

1.2


VBE(on) v IC

VB

E -

(Vol

ts)

Switching Speeds


Sw

itchi

ng ti

me

0.1 1

IB1=IB2=IC/10

0.01

ts

tf

td

tr

tsns

125

175

225

75

0

0.6

0.8

1.0

1.2

0.4

ZTX650

0

0.1

0.2

0.4

0.5

0.3

0.6

0.0010.0001

IC/IB=10

1.4

0.01 100.1 10.0001 0.001

IC/IB=10

0.01 100.1 10.0001 0.001

VCE=2V

0

tdtrtfns

100

120

40

20

60

80

140

0

1000

1200

400

200

600

800

1400

ZTX651

0.1

3-221

PNP SILICON PLANAR


FEATURES

* 60 Volt VCEO



* Ptot

= 1 Watt



Collector-Base Voltage VCBO -60 -80 V

Collector-Emitter Voltage VCEO -45 -60 V

Emitter-Base Voltage VEBO -5 V

Peak Pulse Current ICM -6 A

Continuous Collector Current IC -2 A

Power Dissipation: at Tamb=25°Cderate above 25°C

Ptot 15.7

WmW/°C





Collector-BaseBreakdownVoltage

V(BR)CBO -60 -80 V IC=-100µA

Collector-EmitterBreakdownVoltage

V(BR)CEO -45 -60 V IC=-10mA

Emitter-BaseBreakdownVoltage

V(BR)EBO -5 -5 V IE=-100µA


ICBO -0.1

-10-0.1

-10

µAµAµAµA

VCB=-45VVCB=-60VVCB=-45V,T

amb=100°C

VCB=-60V,Tamb

=100°C


IEBO -0.1 -0.1 µA VEB=-4V


VCE(sat) -0.15-0.28

-0.3-0.5

-0.15-0.28

-0.3-0.5

VV

IC=-1A, IB=-100mAIC=-2A, IB=-200mA


VBE(sat) -0.9 -1.25 -0.9 -1.25 V IC=-1A, IB=-100mA

ZTX750ZTX751

3-257

C B E

E-Line

TO92 Compatible




TransitionFrequency

fT 100 140 100 140 MHz IC=-100mA, VCE=-5Vf=100MHz

Switching Times ton 40 40 ns IC=-500mA, VCC=-10VIB1=IB2=-50mA

toff 450 450 ns

OutputCapacitance

Cobo 30 30 pF VCB=10V f=1MHz





Rth(j-amb)1Rth(j-amb)2 Rth(j-case)

17511670

°C/W°C/W°C/W


ZTX750ZTX751

-40 0.0001

Derating curve


Max

Pow

er D

issi

patio

n -

(Wat

ts)



The

rmal

Res

ista

nce

(°C

/W)

10 10010.10.01-20 0 20 40 60 80 100 120 200180160140 0.0010

100

200

D=0.2

D=0.1

Single Pulse

D=0.5

t1

tP

D=t1/tP

1.0

0.5

2.0

1.5

Case temperature

2.5

Ambient temperature

0

D=1 (D.C.)

3-258

PNP SILICON PLANAR


FEATURES

* 60 Volt VCEO



* Ptot

= 1 Watt



Collector-Base Voltage VCBO -60 -80 V

Collector-Emitter Voltage VCEO -45 -60 V

Emitter-Base Voltage VEBO -5 V

Peak Pulse Current ICM -6 A

Continuous Collector Current IC -2 A

Power Dissipation: at Tamb=25°Cderate above 25°C

Ptot 15.7

WmW/°C





Collector-BaseBreakdownVoltage

V(BR)CBO -60 -80 V IC=-100µA

Collector-EmitterBreakdownVoltage

V(BR)CEO -45 -60 V IC=-10mA

Emitter-BaseBreakdownVoltage

V(BR)EBO -5 -5 V IE=-100µA


ICBO -0.1

-10-0.1

-10

µAµAµAµA

VCB=-45VVCB=-60VVCB=-45V,T

amb=100°C

VCB=-60V,Tamb

=100°C


IEBO -0.1 -0.1 µA VEB=-4V


VCE(sat) -0.15-0.28

-0.3-0.5

-0.15-0.28

-0.3-0.5

VV

IC=-1A, IB=-100mAIC=-2A, IB=-200mA


VBE(sat) -0.9 -1.25 -0.9 -1.25 V IC=-1A, IB=-100mA

ZTX750ZTX751

3-257

C B E

E-Line

TO92 Compatible




TransitionFrequency

fT 100 140 100 140 MHz IC=-100mA, VCE=-5Vf=100MHz

Switching Times ton 40 40 ns IC=-500mA, VCC=-10VIB1=IB2=-50mA

toff 450 450 ns

OutputCapacitance

Cobo 30 30 pF VCB=10V f=1MHz





Rth(j-amb)1Rth(j-amb)2 Rth(j-case)

17511670

°C/W°C/W°C/W


ZTX750ZTX751

-40 0.0001

Derating curve


Max

Pow

er D

issi

patio

n -

(Wat

ts)



The

rmal

Res

ista

nce

(°C

/W)

10 10010.10.01-20 0 20 40 60 80 100 120 200180160140 0.0010

100

200

D=0.2

D=0.1

Single Pulse

D=0.5

t1

tP

D=t1/tP

1.0

0.5

2.0

1.5

Case temperature

2.5

Ambient temperature

0

D=1 (D.C.)

3-258

TYPICAL CHARACTERISTICS

VCE(sat) v IC


VC

E(sa

t) -

(Vol

ts)

0.01 0.1 101

10

0

0.1

0.2

0.4

0.5

0.3

0.6

0.0010.0001

IC/IB=10


hFE v IC

hFE

- G

ain

0.01 0.1 1

VCE=2V

125

175

225

75

0


VBE(sat) v IC

VB

E(sa

t) -

(Vol

ts)

0.6

0.8

1.0

1.2

1.4

0.01 100.1 10.0001 0.001

IC/IB=10


VBE(on) v IC

VB

E -

(Vol

ts)

0.6

0.8

1.0

1.2

0.40.01 100.1 10.0001 0.001

VCE=2V

Switching Speeds

IC - Collector Current (Amps) S

witc

hing

tim

e

0.1 1

IB1=IB2=IC/10

ts

tf

td

tr

tsns

0

tdtrtfns

100

120

40

20

60

80

140

0

500

600

200

100

300

400

700

IC -

Col

lect

or C

urre

nt (

Am

ps)

VCE - Collector Voltage (Volts)

Safe Operating Area

1 10 1000.01

0.1

1

10Single Pulse Test at Tamb=25°C

D.C. 1s 100ms 10ms

1.0ms 100µs

ZTX750ZTX751

0.1

ZTX750ZTX751

3-259

Date post:	26-Mar-2022
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