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EE141 EECS141 1 Lecture #4


New discussion session Fr 1-2pm

Homework #1 extension until Monday 5pm

Homework #2 to be posted later today

Labs start next week (Monday)

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Last lecture

Basic metrics for IC design

Manufacturing

Today’s lecture

Design Rules

Introduction to switch logic

Reading (2.3, 3.3.1-3.3.2)


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(well contacts)

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Interface between designer and process

engineer

Guidelines for constructing process masks

Unit dimension: Minimum line width

scalable design rules: lambda parameter

absolute dimensions (micron rules)


Intra-layer

Widths, spacing, area

Inter-layer

Enclosures, distances, extensions,

overlaps

Special rules (sub-0.25 m)

Antenna rules, density rules, (area)

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• Dimensionless layout entities

• Only topology is important

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Polysilicon

In Out

V DD

GND

PMOS 2

Metal 1

NMOS

Contacts

N Well

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Connect in Metal

Share power and ground

Abut cells


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|VGS|

An MOS Transistor

|VGS| |VT|

S D

Ron

A Switch!

S D

G


|VGS|

S D

G

|VGS| < |VT| |VGS| > |VT|

Ron

S D S D

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|VGS|

S D

G

|VGS| < |VT| |VGS| > |VT|

Ron

S D

Roff

S D


VGS > 0

S D

G

VGS < 0

S D

G

NMOS Transistor PMOS Transistor

Y=Z IF X=1 Y=Z IF X=0

Y Z

Ron X

Y Z

Ron X

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V in V out

C L

V DD

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VOL = 0

VOH = VDD VM = f(Rn, Rp)

V DD V DD

V in = V DD V in = 0

V out V out

R n

R p


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VOH =

VOL =

VIL =

VIH =

NMH =

NML =

VM =


VOH = VDD = 2.5V

VOL = 0V

VM = 1.2V

VIL = 1.05V

VIH = 1.45V

NMH =1.05V

NML = 1.05V

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t pHL = f(RonCL)

= 0.69 R n C L

(a) Low-to-high (b) High-to-low


Full rail-to-rail swing

Symmetrical VTC

Propagation delay function of load

capacitance and resistance of transistors

No static power dissipation

Direct path current during switching

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CL

In Out

For some given CL:

How many stages are needed to minimize delay?

How to size the inverters?

Anyone want to guess the solution?

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Get fastest delay if build one very big

inverter

So big that delay is set only by self-loading

Likely not the problem you’re interested in

Someone has to drive this inverter…


Need to have a set of constraints

Constraints key to: Making the result useful

Making the problem have a ‘clean’ solution

For sizing problem: Need to constrain size of first inverter

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You are given:

A fixed number of inverters

The size of the first inverter

The size of the load that needs to be driven

Your goal:

Minimize the delay of the inverter chain

Need model for inverter delay vs. size


tpHL = (ln 2) RNCL tpLH = (ln 2) RpCL Delay:

2W

W

Assume we want equal rise/fall delays

tpHL = tpLH

Need approximately equal resistances, RN = RP PMOS approximately 2 times larger resistance

for same size;

Must make PMOS 2 times wider, WP = 2WN = 2W

tp = (ln 2) (Rmin/W) CL with Rmin resistance of

minimum size NMOS

Loading on the previous stage: Cin = WCgmin = W(3CG)

CP = 2WCg

CN = WCg

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Cint CL

Replace ln(2) with k (a constant):

Delay = kR(Cint + CL)

Delay = k(Rmin/W)(WCdmin + CL)

2W

W

R = Rmin/W

Cint = (3W)Cd = WCdmin


Load

Delay

Delay = kR Cin(Cint/Cin+ CL /Cin)

= kRminCgmin[Cdmin/Cgmin + CL/(WCgmin)]

= Delay (Internal) + Delay (Load)

Cdmin/Cgmin = = Constant independent of size

Cint CL

Cin 2W

W

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Cint = Cin ( 1 for CMOS inverter)

f = CL/Cin – electrical fanout

tinv = kRminCgmin

tinv is independent of sizing of the gate!!!


CL

In Out

1 2 N

tp = tp1 + tp2 + …+ tpN

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Delay equation has N-1 unknowns, Cin,2 … Cin,N

To minimize the delay, find N-1 partial derivatives:


Result: every stage has equal fanout:

In other words, size of each stage is geometric

mean of two neighbors:

Equal fanout every stage will have same delay

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When each stage has same fanout f :

Effective fanout of each stage:

Minimum path delay:


CL= 8 C1

In Out

C1 1 f f 2

CL/C1 has to be evenly distributed across N = 3 stages:

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You are given: The size of the first inverter

The size of the load that needs to be driven

Your goal: Minimize delay by finding optimal number and sizes of gates

So, need to find N that minimizes:


For = 0, f = e, N = ln (CL/Cin)

Rewrite N in terms of fanout/stage f:

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Optimum f for given process defined by

0 0.5 1 1.5 2 2.5 3 2.5

3

3.5

4

4.5

5

f opt

fopt = 3.6

for = 1

e


Curves very flat for f > 2

Simplest/most common choice: f = 4

[Hodges, p.281]

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Textbook: page 210

( = 1)


1

1

1

1

8

64

64

64

64

4

2.8 8

16

22.6

N f tp

1 64 65

2 8 18

3 4 15

4 2.8 15.3

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Ignoring diffusion capacitance:

Ctot = Cin + f Cin + … + fN Cin

= Cin (1 + f + … + fN)

= Cin + Cin fN + Cin f (1 + f + … +

fN-2) Overhead !!! f(fN-1-1) / (f-1)

Example ( =0): CL = 20pF; Ci = 50fF N = 6

Fixed: 20pF

Overhead: 11.66pF !!!


Example: CL = 20pF; Cin = 50fF

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