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EE141 EECS141 1 Lecture #14
EE141 EECS141 2 Lecture #14
Hw 5 due Today. Hw 6 posted early next week. You get TWO
weeks for this one. Project phase 1 will be launched today Out of town next week
We lecture offered by Stanley Fr lecture cancelled – Make-up on Tu
March 16 at 3:30pm
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EE141 EECS141 3 Lecture #14
Last lecture Inverter energy Project launch
Today’s lecture Optimizing complex CMOS Pass Transistor Logic
Reading (Ch 5, 6)
EE141 EECS141 4 Lecture #13
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EE141 EECS141 5 Lecture #13
Techniques very similar to the inverter case
Logical Effort technique as the means for gate sizing and topology optimization
However … some other things to be aware of
EE141 EECS141 6 Lecture #13
D C B A
D: 01
C: 1
B: 1
A: 1 CL
C3
C2
C1
RC model:
2 2 2 2
4
4
4
4
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EE141 EECS141 7 Lecture #13
D C B A
D
C
B
A CL
C3
C2
C1
Distributed RC model (Elmore delay)
tpHL = 0.69 Reqn(C1+2C2+3C3+4CL)
Propagation delay deteriorates rapidly as a function of fan-in – quadratically in the worst case.
2 2 2 2
4
4
4
4
EE141 EECS141 8 Lecture #13
t p (p
sec)
fan-in
Gates with a fan-in greater than 4 should be avoided.
tpHL
quadratic
linear
tp
tpLH
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EE141 EECS141 9 Lecture #13
tpNOR2
t p (p
sec)
eff. fan-out = CL/Cin
All gates have the same drive current.
tpNAND2
tpINV
Slope is a function of “driving strength”
EE141 EECS141 10 Lecture #13
Fan-in: quadratic due to increasing resistance and capacitance
Fan-out: each additional fan-out gate adds two gate capacitances to CL
tp = a1FI + a2FI2 + a3FO
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EE141 EECS141 11 Lecture #13
Transistor sizing as long as fan-out capacitance dominates
Progressive sizing
InN CL
C3
C2
C1 In1
In2
In3
M1
M2
M3
MN
Distributed RC line
M1 > M2 > M3 > … > MN (the FET closest to the output is the smallest)
Can reduce delay by more than 20%; Be careful: input loading, junction caps, decreasing gains as technology shrinks
EE141 EECS141 12 Lecture #13
Transistor ordering
C2
C1 In1
In2
In3
M1
M2
M3 CL
C2
C1 In3
In2
In1
M1
M2
M3 CL
critical path critical path
charged 1
0→1 charged
charged 1
delay determined by time to discharge CL, C1 and C2
delay determined by time to discharge CL
1
1
0→1 charged
discharged
discharged
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EE141 EECS141 13 Lecture #13
Alternate logic structures F = ABCDEFGH
EE141 EECS141 14 Lecture #13
Isolating fan-in from fan-out using buffer insertion
CL CL
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EE141 EECS141 15 Lecture #13
Reducing the voltage swing
linear reduction in delay also reduces power consumption
But the following gate is slower! Or requires use of “sense amplifiers” on the
receiving end to restore the signal level (memory design)
tpHL = 0.5 (CL VDD) / IDSATn
= 0.5 (CL Vswing) / IDSATn
EE141 EECS141 16 Lecture #13
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EE141 EECS141 17 Lecture #13
EE141 EECS141 18 Lecture #13
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EE141 EECS141 19 Lecture #13
EE141 EECS141 20 Lecture #13
What is LE of “gate” shown below for A and B inputs? Hint: Can you answer this question with only the
information shown below?
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EE141 EECS141 21 Lecture #13
In CMOS, a “gate” is defined only when trace a connection all the way back to a supply Otherwise don’t know what drive resistance really is
EE141 EECS141 22 Lecture #13
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EE141 EECS141 23 Lecture #13
EE141 EECS141 24 Lecture #13
• Advantage: Full Swing • Restorer adds capacitance, takes away pull down current at X • Ratio problem
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EE141 EECS141 25 Lecture #13
• Upper limit on restorer size • Pass-transistor pull-down can have several transistors in stack
EE141 EECS141 26 Lecture #13
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EE141 EECS141 27 Lecture #13
EE141 EECS141 28 Lecture #13
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EE141 EECS141 29 Lecture #13
EE141 EECS141 30 Lecture #13
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EE141 EECS141 31 Lecture #13
EE141 EECS141 32 Lecture #13
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EE141 EECS141 33 Lecture #13
EE141 EECS141 34 Lecture #13
OUT = D + A • (B + C)
D A
B C
D
A B
C
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EE141 EECS141 35 Lecture #13
Standard Cells General purpose logic Used to synthesize RTL/HDL Same height, varying width
Datapath Cells For regular, structured designs (arithmetic) Includes some wiring in the cell
EE141 EECS141 36 Lecture #13
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EE141 EECS141 37 Lecture #13
EE141 EECS141 38 Lecture #13
M2
No routing channels VDD
GND M3
VDD
GND
Mirrored Cell
Mirrored Cell
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EE141 EECS141 39 Lecture #13
Cell boundary
N Well Cell height 12 metal tracks Metal track is approx. 3λ + 3λ Pitch = repetitive distance between objects
Cell height is “12 Mn pitch”
2λ
Rails ~10λ
In Out
V DD
GND
EE141 EECS141 40 Lecture #13
In Out
V DD
GND
In Out
V DD
GND
With silicided diffusion
With minimal diffusion routing
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EE141 EECS141 41 Lecture #13
A
Out
V DD
GND
B
2-input NAND gate
EE141 EECS141 42 Lecture #13
Contains no dimensions Represents relative positions of transistors
In
Out
V DD
GND
Inverter
A
Out
V DD
GND B
NAND2
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EE141 EECS141 43 Lecture #13
X
C A B A B C
X
VDD
GND
VDD
GND
EE141 EECS141 44 Lecture #13
C
A B
X = C • (A + B)
B
A C
i j
VDD X
X
i
GND
A B
C
PUN
PDN A B C
Logic Graph j
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EE141 EECS141 45 Lecture #13
j
VDD X
X
i
GND
A B
C
A B C
Has PDN and PUN
A B C
Has PUN, but no PDN
EE141 EECS141 46 Lecture #13
C
A B
X = (A+B)•(C+D)
B
A
D
VDD X
X
GND
A B
C
PUN
PDN
C
D
D
A B C D
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EE141 EECS141 47 Lecture #13
EE141 EECS141 48 Lecture #13
One finger Two fingers (folded)
Less diffusion capacitance
