IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40. NO. I . JANUARY 1993

Lateral Profiling of Oxide Charge and Interface Near MOSFET Junctions

Wenliang Chen, Student Member, IEEE, Artur Balasinski, and Tso-Ping Ma, Senior Member,

I87

Traps

IEEE

Abstract-A new technique to measure the lateral distribu- tions of both interface traps and trapped oxide charge near the source/drain junctions in MOSFET’s will be presented in de- tail. This technique derives from the charge pumping method, is easy to implement, and allows ready separation of the inter- face-trap and oxide charge components. This paper will cover the experimental details of this technique, along with some il- lustrative results. The various issues involved in its implemen- tation and its practical limitations will also be discussed.

I . INTRODUCTION OCALIZED damage in the vicinity of source /drain L junctions of small-geometry MOSFET’s has become

a well-recognized device reliability issue. Many attempts have been made to characterize such highly localized damage near the drain junction [1]-[3], with a primary focus on the spatial distribution of interface traps [N, , (x)] . However, as pointed out by many authors, the effect of localized oxide charge (No,) near the junction is at least as important as that of Ni, resulting from channel-hot-car- rier (CHC) induced damage [4], [ 5 ] , but it has not been adequately studied due to the lack of a good characteri- zation technique.

Recently we introduced a new technique based on charge pumping to measure the lateral profiles of both N i r ( x ) and oxide charge No,(x) [6]. This technique also eliminates some of the systematic errors in N I , (x) that may be incorporated in other charge-pumping-based tech- niques. In this paper, we give a fuller description of the techniques and address various issues in its implementa- tion and data analysis. The basic principle of the tech- nique is described below.

11. BASIC PRINCIPLE OF THE TECHNIQUE

This new technique is based on exactly the same phys- ical principles as those of the conventional charge pump- ing technique. During a typical charge pumping measure- ment, a pulse string is applied to the gate terminal of a

Manuscript received June 30, 1992; revised August 25, 1992. This work was supported by NRL and SRC under research grants. The review of this paper was arranged by Associate Editor Y. Nishi.

W. Chen was with the Center for Microelectronics Materials and Struc- tures, and the Department of Electrical Engineering. Yale University, New Haven, CT 06520-2157. He is now with Intel Corporation, Portland, OR.

A. Balasinski and T. P. Ma are with the Center for Microelectronic Ma- terials and Structures, and the Department of Electrical Engineering, Yale University, New Haven, CT 06520-2157.

IEEE Log Number 9204605.

MOSFET while the substrate current (commonly called the “charge pumping current”) is monitored. Since this current is a result of the recombination of majority car- riers (coming from the substrate when the gate is biased between flatband and accumulation) with the trapped mi- nority carriers at the interface (coming from the source/drain when the gate is biased to inversion), to first order the charge pumping current (I,,) is nonzero only if the high level (V,) and the base level (Vb) of the gate pulses cover both the threshold voltage (V, ) and the flatband volt-

The conventional charge pumping technique uses gate pulses with constant amplitude (v, - Vb) and varying V,. For uniformly distributed N I , (x) and No, (x), a maximum plateau in the Zrp versus V, plot is obtained in a range where maximum coverage of the channel is realized by the gate pulse. Typically the CHC-induced damage is highly localized, resulting in a distortion of the Icp versus V, curve. Although such a distorted curve contains much information of interest, it is often difficult to interpret [9].

The difficulty of the conventional technique arises from the fact that both the flatband voltage Vfl and threshold voltage V, are probed at the same time. Since they usually have different lateral distributions across the channel, it is difficult, if not impossible, to deconvolve the Irp versus V, curves to separate out Vfl (x) and V, (x).

To overcome this difficulty, instead of using fixed pulse height (V, - V,) and varying V,, our technique uses fixed V, and varying V,. As shown in Fig. 1, suppose the MOS- FET sample has laterally nonuniform distributions of VB and V, (both defined by carrier density) due to nonuniform distributions of oxide charge and interface traps. By vary- ing V,, only the part of the channel where V, is covered by V,, can contribute to lcp. A I/,-varying pulse train will thus give a charge pumping current IC,, as a function of Vh

age vfi) ~71 , (81.

[71

l ~ p ( ~ h ) = qwf sl Ni,(x)g[Vh - Vr(x>l (l)

where W is the channel width, f the gate pulse frequency, L the effective length of the channel that contributes to the charge pumping current, N,, (x) the distribution of inter- face traps along the channel, and g can be approximated as a step function which can be expressed as

1, i f y > O

i f y < 0 g ( y ) = 0 ,

0018-9383/93$03.00 0 1993 IEEE

I88 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. I . JANUARY 1993

Source1 Channel I Drain

I 7 ‘h

Fig. 1. Schematic illustration of the principle of the technique. Top: V, of the gate pulse string is lower than flatband voltage and the varying V, probes the interface traps in regions that have threshold voltages lower than Vh. Bottom: illustrative IC,, versus Vh curve and its derivative.

In other words, each incremental AV, covers an addi- tional incremental portion of the channel, which gives an incremental charge pumping current AZcp corresponding to the interface traps in that portion of the channel, and the voltage V, at which this increment occurs is the local VI of that portion of the channel. Thus the derivative of Zcp with respect to V,

where 6, the Dirac delta function, reflects the distribution of interface traps over the threshold voltage. While in the- ory a uniform channel should give a sharp peak of the [dZcp(Vh)]/dVh versus V, plot, in general this curve ex- hibits a finite width due to the laterally nonuniform dis- tribution of V,(x) (e.g., caused by N,,(x)) in the channel. In fact, in cases where charge trapping is highly localized with a significant magnitude, such as due to CHC-induced interface traps and oxide charge, one often observes a new peak superimposed on the original peak in the dZcp/dVh versus V, curve. By separating out and analyzing this new peak, one can obtain the amount of No, [4].

To obtain the spatial profiles of No, and Nit near the drain junction, one may vary the reverse drain bias to con- trol the junction depletion width, and hence the effective channel length for the charge pumping signal [l] . Sup- pose a reverse bias is applied to the drain junction such that the effective channel is shortened by U ( L -+ L - U) (for the moment let us assume that this bias does not affect the local threshold voltage profile V,(x)), then Zcp will decrease due to the exclusion of that portion of the Nit in the depleted region. The incremental decrease in Zcp is

4 - p = 4Wf Nir(x)g[V, - Vt(X11

= S Wf Nit (L’ )g [ V, - Vr (L’ )IU (3)

2 I - 1 z

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Fig. 2 . Threshold voltage (V , (x ) ) and flatband voltage (V,(x)) near the drain junction with drain biases Vd = 0 and 2 V, simulated with PISCES IIB. The origin of the X-axis is set at the left edge of the source which is 1.0 pm in length.

where L’ = L - U / 2 . The incremental decrease in the saturation value of Zcp is therefore

(4) Concurrently, a decrease also appears in the dZcp/dVg ver- sus Vh curve

N c p m a x = qwf Ni, (L’ )U-

= qwfNi,(L’)6[V, - Vf(L’)]AL. (5)

Equation ( 5 ) indicates that only when V, = Vt(L’) does A(dZcp/dV,) have a nonzero value. In other words, the location on the V, axis where dZcp/dVh decreases corre- sponds to Vr at x = L’. The oxide charge density at x = L‘ can then be calculated from this threshold voltage.

Based on the above analysis, to profile the lateral spa- tial distributions of Nit and No, near the junctions, one may apply a variable reverse bias on the source/drain junctions to vary the depletion width, and plot a series of Zcp and dZcp/dVh versus V, curves for different junction biases. From the incremental change of the ZcpmaX or the area un- der the dZcp/dVh versus V, curve, one can obtain Ni t@) , while the voltage on the V, axis where such change occurs provides the oxide trapped charge distribution No, (x).

However, the assumption made above that V, (x ) does not change with drain bias is not true due to an effect sim- ilar to the back bias effect in MOSFET. Fig. 2 shows the V,(x) and Vt(x) distributions near the drain junction of a 1 .O-pm NMOSFET with either no drain bias or 2-V drain reverse bias, simulated with PISCES IIB. Note that the origin of the X axis is set at the left edge of the source which is 1.0 pm in length. In this case Vr and Vfl are de- termined at electron and hole densities of l X l O I 7 cm-3 ( - channel doping), respectively. While V, lowers and shifts toward the center of the channel with increasing Vd, which effectively decreases the channel length for charge pumping current, Vr increases due to the body effect. Therefore, if a dc drain bias is used to change U, the Zcp and dZcp/dVh versus V, curves described in (3) and (5 ) will not be obtained correctly.

A ‘ ‘constant-field” approach introduced by Ancona et al . [l] can satisfactorily alleviate this problem. It is based on the fact that the depletion region edge is determined

CHEN er al . : LATERAL PROFILING OF OXIDE CHARGE AND INTERFACE TRAPS NEAR MOSFET JUNCTIONS

400

1200

1000

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by the majority-carrier density, hence only during accu- mulation half of the pulse cycle is the drain bias needed to modify the effective channel length. In this approach, a second pulse string ( Vdb) 180” out of phase with the gate pulses is applied on the junction so that the drain voltage remains 0 during the inversion (trap filling) half cycle to ensure that V,(x) does not change with the drain bias. Only during the trap emission cycle is the junction bias applied. Therefore, the drain pulse V,, only changes V@ during the accumulation half cycle but does not change V, during the inversion half cycle.

7 I I I I I I

NMOSFET 15W1.3 1300 Seconds @ Vd=BV, Vg=PV - _ _ _ - _ _ _ ___. . _.___

,_--- - - Pre-stress -

- -

Post-stress - - - - ,,,’

111. MEASUREMENT APPARATUS AND IMPLEMENTATION Fig. 3 is a schematic diagram of the experimental setup

for our charge pumping measurements. Two pulse gen- erators, an HP8115A and an HP8082A, are used to sup- ply the gate pulses and drain bias pulses, respectively. The gate pulses V,, supplied by the HP8115A function generator, have a fixed base level Vb and varying high level V, controlled by an analog voltage from an HP4145B parameter analyzer. The drain pulse V,,, supplied by the HP8082A, is externally triggered by V,, and adjusted to align with V g . Note that the drain bias pulses are only applied when one decides to obtain the lateral profiles of Nit and Nor. The inset in Fig. 3 shows the alignment of Vg and Vdb. The rise and fall times of Vg and Vdb are adjusted to be the same. The charge pumping current Zrp, typically in the range of a few nanoamperes, is measured by the. parameter analyzer. The dZcp/dVh versus V, curve can be conveniently calculated on the parameter analyzer as a user function. Because of the output impedance of the pulse generators, all pulses are terminated with 50 Q at the device terminals and monitoring oscilloscope. A long integration time on the HP4 145B parameter analyzer is used in most cases to reduce the noise.

In our experiments, we use square pulses with frequen- cies of 100 kHz to 1 MHz, rise/fall times of 50-200 ns, and a base level in the range -7--4 V. The test devices are MOSFET’s with a 150-pm channel width, 1.0-1.5- pm channel length, 25-nm oxide thickness, and no LDD structures.

As an illustrative example, Fig. 4 shows the Zrp and drP /dVh versus Vh curves measured with both source and drain grounded before and after CHC stress for 1300 s at V, = 8 V and V, = 2 V for a 150/1.3-pm NMOSFET. The gate pulses for the charge pumping measurement have a frequency of 100 kHz and a rise/fall time of 200 ns. While the Zrp curve (Fig. 4(a)) shows a large number of CHC-induced interface traps, the original peak in the dZcp/dVg versus V, curve (Fig. 4(b)) only increases slightly, suggesting that the bulk of the channel is almost unaffected. The large shoulder to the left of the main peak is due to the CHC-induced interface traps, which are as- sociated with a lower threshold voltage due to the positive oxide charge at the damage location.

When a 4-V drain-bias pulse is applied during the aforementioned ‘ ‘constant-field” charge pumping mea-

189

rp=--k Pulse Gen.

Trigger

HP4145B 6 Parameter Analyzer

Fig. 3 . Schematic diagram of the measurement setup. The inset shows proper alignment of the gate and drain pulses.

&&-J -4 -3 -2 -1 0 1 2 3 4

v h (v)

(b) Fig. 4. (a) IC,, versus V, and (b) dI,/dV, versus Vh curves of a 150/1.3 pm NMOSFET before stressing (solid curve) and after 1300-s CHC stress at Vd = 8 V, Vc = 2 V (dashed curve), measured at 0-V drain bias.

surement, Fig. 5(a) shows that the shoulder on the dZrp/dVh versus V, curve is reduced, due to the shortened effective channel which excludes a portion of the dam- aged region from contributing to the signal. In contrast, however, when the same 4-V junction-bias pulse is ap- plied to the source terminal, no effect can be observed in the dZrp/dVh versus V, curves (see Fig. 5(b)). In both cases, the main peak in the dIrp/dVh versus V, curves stays unchanged, indicating that the CHC-induced damage is indeed highly localized near the drain junction, and can be revealed clearly by this new charge pumping scheme.

The importance of selecting proper rise/fall times of the gate pulses to avoid the “geometric current” has been well addressed in [SI. In addition, proper alignment of Vg and Vdb is crucial to the accuracy of the measurement. If the pulses are misaligned, or the base level of Vdb is not zeroed properly, there could be a shift of the main peak

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 1, JANUARY 1993 190

loo0

9 1 Drainbias=OV- 1 5 600 Drain bias = 4V--

Drain bias = OV-

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t . . / , , d 200

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(b) Fig. 5. dIcp/dVh versus V,, curves of the stressed 150/1.3 pm NMOSFET measured at (a) drain bias Vd = 0 and 4 V, (b) source bias V, = 0 and 4 v.

of the dZcp/dVh versus V, curve along the V, axis when V& is applied.

IV. EXPERIMENTAL PROCEDURES AND ILLUSTRATIVE RESULTS

In this section we illustrate step-by-step the procedures for obtaining the lateral distribution of CHC-induced damage near the drain junction. For this purpose, a 150/1.0 p NMOSFET was stressed at V, = 8 V, Vg = 2 V for 1000 s to generate significant amounts of Nil and

Charge pumping measurements were done with gate pulses of 1 MHz in frequency, a 50-ns rise/fall time, and a -4-V base level. A set of drain-bias pulses with ampli- tudes ranging from 0 to 5.6 V were also applied in the “constant-field” configuration described earlier to obtain a series of IC,, and dZcp/dVh versus V, curves. The maxi- mum amplitude of the drain-bias pulses that can be ap- plied is essentially limited by two factors: 1) drain junc- tion leakage, and 2) unintentional hot-camer damage during measurement. In our case, this limit is below 6 V due to one of these factors.

Not *

A. Lateral Distributions of Threshold Voltages and Interface Traps

As shown in Fig. 6(a) and (b), both the Zfp and the dZcp/dVh versus V, curves decrease as the drain bias in- creases, due to the increased junction depletion width, as described in (3) and (5). We then took the difference of two adjacent dZcp/dVh versus V, curves for each incre- mental drain bias, as shown in Fig. 6(c). The peak posi-

16

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(C) Fig. 6. (a) I , versus V,,; (b) dI,,/dVh versus V,; and (c) A(dIcp/dVh) ver- sus vh curves (the difference of two adjacent dI,/dV, versus curves for each incremental drain bias) of a 150/1.0 pm NMOSFET before stressing (dotted curve) and after 1000-s CHC stressing at Vd = 8 V , Vc = 2 V , measured at various drain biases ranging from 0 to 4 V .

tions of the A(dZcp/dVh) curves give the threshold volt- ages at the particular physical locations being probed.

To obtain the corresponding effective channel length that contributes to the charge pumping current for each drain bias, we used a PISCES IIB model of the device to simulate the majority-canier distribution. The location where the effective channel ends is defined to be where V’ (to be defined in the next paragraph) is equal to V,, because in the region where Vfb is below V,, there is not enough majority carriers for the interface traps to contrib- ute significantly to Zcp. Since V near the drain junction is a strong function of the drain bias V&, one can thus vary V& to modulate the effective channel length for charge pumping.

It should be noted that our definition of V’ is based on the gate voltage at which there are insufficient majority carriers to contribute significantly to the charge pumping current, which is different from the conventional “flat- band” voltage (defined as the gate voltage at which the

f?

....

CHEN er ai.: LATERAL PROFILING O F OXIDE CHARGE AND INTERFACE TRAPS NEAR MOSFET JUNCTIONS 191

-1.5

surface majority-carrier concentration equals the channel dopant density). For a typical MOSFET the channel dop- ing density is rather high, and significant recombination does occur at the conventional flatband voltage. In our case, we set V' to be the gate voltage at which the ma- jority-carrier concentration equals the minority-carrier concentration at the peak of the dZcp/dVh versus V, curve, which corresponds to a concentration of - 1 x cm-3 for this device. In theory, this concentration depends on the charge pumping frequency, and can be estimated ac- cording to

- Junction

I 1 I I , i t

1 n = - (7rvth

where U is the mean capture cross section of the interface traps, r is the half period of the gate pulses, and z/th is the thermal velocity of the carriers.

Fig. 7 shows the simulated majority-carrier densities as a function of lateral position (with the location of drain junction indicated) for a set of drain biases ranging from 0 to 6 V with a fixed gate bias Vg = -4 V. It is evident that the edge of the majority-carrier distribution shifts away from the drain junction as the drain bias increases, resulting in a shorter effective channel which contributes to the charge pumping current. The values of AL in (3) can thus be obtained from Fig. 7 once the cutoff value of the majority-carrier concentration is determined.

After we have obtained the values of AZCpmax at various drain biases and the corresponding physical locations, the lateral distribution of the interface traps N i r ( x ) can be cal- culated using (4). The results are shown in Fig. 8 , where the threshold-voltage distribution is also plotted.

B. Lateral Distribution of Oxide-Trapped Charge In principle, the lateral distribution of oxide-trapping

charge Nu, (x) can be readily obtained from the difference in V,(x) caused by the presence of N o , @ ) (the effect of N j , ( x ) will be discussed later). In practice, the threshold voltage is not laterally uniform near the junction even in the absence of nonuniform distribution of oxide-trapped charge, due to the variation of the doping profile. In re- gions where the doping concentration is high and has a large gradient, significant errors in the determination of

(x) could easily be introduced without accurate knowl- edge of the doping profile, leading to large errors in the extracted Nu, (x). To minimize such errors, we use the de- vice before CHC stressing as a reference, and the change in V,(x) is then attributed to the CHC-induced N u , @ ) by assuming that the doping profile is not affected by the CHC stress.

Before the device has undergone CHC stress, the typ- ical charge-pumping signal is very weak due to the low interface-trap density. In this case, the alignment of Vg and Vdb is even more critical, because a slight shift of the dZ,,/dV, versus Vh curve due to the misalignment may cause a difference curve that is much larger than the actual difference resulting from the drain bias. Fig. 9 shows the

' " 1.76 1.78 1.8 1.82 1.84 1.86 1.88 1.9 1.92 Position ( pm)

Fig. 7. Majority-carrier concentration near the drain junction at V, = -4 V with various drain biases, simulated with PISCES IIB. The origin of the X-axis is set at the left edge of the source which is 1 .O pm in length.

l 6 L 14 Vb=-4V , f= lMHz - 0.4 - 0.2

- 0 5 - -0.2 3 - -

-0.4 -0.6

2 -0.8

1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88l Position (b m)

Fig. 8. Lateral distributions of interface traps and threshold voltages near the drain junction after CHC stress as deduced from the data in Fig. 6 but with finer drain-bias intervals

0.5

0

-0.5

' -1 -

V,(x) profiles for a device before and after CHC stress. We attribute the difference between them to the CHC-in- duced positive oxide charge. Also shown in Fig. 9 is the simulation result by the use of PISCES IIB which agrees reasonably well with the experimental data.

Fig. 10 shows the lateral distribution of the oxide- trapped charge after CHC stress as calculated from the difference of the two V, (x) profiles after and before stress- ing shown in Fig. 9.

C. Region Very Close to Drain In the region very close to the drain, V, (x) changes dra-

matically with position due to the large gradient of the dopant concentration. The doping profile near the drain region is also plotted in Fig. 10. A small error in deter-

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. I , JANUARY 1993 192

- 6 N

b 4

- 3 2 2

1

n

5 5

-

1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 Position ( ~ m )

z.

-2 1.88

Fig. 10. Lateral distribution of oxide trapped charge No,@) near the drain junction as extracted from the data in Fig. 9. The error bars are discussed in the text. The doping profile in that region is also shown as a reference. The origin of the X-axis is set at the left edge of the source which is 1.0 pm in length.

mining the lateral position in that region will translate into a large error in No,@). In addition, the presence of No, will also affect the lateral position of the depletion edge, which has not been taken into account in the simulation. Therefore, our measurement of No,(x) is limited to the region with moderate doping gradient. The error bars in Fig. 10 are estimated based on the uncertainty in deter- mining the lateral position. The errors may be reduced by properly taking into account the effect of oxide charge in the simulation. But in reality there are usually other un- certainties about the device parameters used in the com- puter model which make it questionable whether such ad- ditional effort is justified.

The difficulty of determining No,@) very close to the junction is better illustrated in Fig. 11, where V’(x) and V, (x) were simulated on two otherwise identical devices, one with 1 X 10l2 cmP2 of No, in the region near the drain junction (from 1.83 to 1.90 pm along the X-axis) and the other without. In the region where the doping gradient is high, the effect of No, on V, (x) is complicated by the large slope of V, (x) itself.

The localized oxide charge over the drain in devices with thin gate oxides can be measured with other tech- niques such as the gate-induced drain leakage (GIDL) current [lo], [ l l ] , but it remains a difficult task to accu- rately measure the lateral profiles of the oxide charge over the drain.

D. Correction to Nof(x) Due to Eflect of Nj, (x)

In the procedure described above to extract No, (x), the effect of interface traps on V,(x) was not taken into ac- count. It has been shown and now commonly believed that interface traps above midgap are acceptor-type and those below are donor-type [12]. Therefore, for an n- channel MOSFET the net charge of the interface traps is negative when the gate is biased to inversion, due to the charging of acceptor-type interface traps above midgap. This negative interface charge certainly affects V,(x) in the same way as the oxide charge does. In principle, one should be able to accurately compensate for the effect of the interface traps provided the energy distribution Dit ( E ) is known at all locations of interest. Without knowing the

-5

-6

- -

1.76 1.78 1.8 1.82 1.84 1.86 1.88 1.9 Position ( m)

= -1

-51 , , , , ’’?vi -6

1.76 1.78 1.8 1.82 1.84 1.86 1.88 1.9 -7

Position ( m) 1 1.92

Fig. 1 1 . Threshold voltage (V, (x ) ) and flatband voltage (VB ( x ) ) near the drain junction with and without localized oxide charge of 1 x 10’’ cm-’ uniformly distributed in the region specified, simulated with PISCES IIB. The origin of the X-axis is set at the left edge of the source which is 1 .O pm in length.

energy distribution of the interface traps, one may esti- mate the amount of interface charge Q, by assuming a uniform energy distribution, which yields Q, (x) = -qNit (x)/2. The corrected oxide charge distribution is thus N;,(X) = No, (x) - Ni, ( ~ ) / 2 .

E. Nonuniform Dopant Distribution In devices where the channel doping is intentionally

made nonuniform, the pre-stress dlcp/dVh versus V, curve will not necessarily exhibit a single peak as described ear- lier. One example is sub-half-micrometer MOSFET with LDD, which can show two peaks in the dlcp/dVh versus Vh curve because the channel and the LDD regions are of comparable size but have very different doping concentra- tions. In such cases, the extra “bumps” in the dZcp/dVh versus V, curves should not be interpreted as being due to oxide charge. In fact, by analyzing these bumps, it is pos- sible to estimate the doping difference in different parts of the channel in such devices. One can also obtain the lat- eral distributions of CHC-induced oxide charge and in- terface traps in such devices, although the analysis is more complicated due to the multiple bumps.

F. Selection of Vb for the Gate Pulses Previously we mentioned that the lateral extent this

technique can cover is limited by the maximum amplitude of the drain-bias pulses. Another parameter that can affect this lateral range is the base level of the gate pulses Vb. Fig. 12 shows the surface majority-carrier concentration distributions for a series of Vd’s simulated at Vg = -4 V and -7 V, respectively. With a lower Vb applied to the gate, the accessible region is shifted closer to the junc- tion.

We repeated the charge pumping measurement on the same device with Vb = -7 V and other parameters un- changed. As shown in Fig. 13, the Ni,(x) profile can be extended further over the drain junction when Vb of -7 V is used instead of -4 V. The overall N,, (x) profile shows a peak near the junction, which roughly coincides with the electric field peak under this stress condition. Such correlation has also been observed by other authors

CHEN er al.: LATERAL PROFILING OF OXIDE CHARGE A N D INTERFACE TRAPS NEAR MOSFET JUNCTIONS

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-1 0

193

90

$ - r 60 5 50- -0 40

30-

1.76 1.78 1.8 1.82 1.84 1.86 1.88 1.9 1.92 Position ( pm)

Fig. 12. Distributions of majority-camer concentration near the drain junction under a gate voltage of either -4 or -7 V with various drain biases, simulated with PISCES IIB. The origin of the X-axis is set at the left edge of the source which is 1.0 pm in length.

-

-

-

,

Pre-stress - Post-stress ....-.. -

1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89 1.9 Position (pm)

(a) 0.71 I 1 I I I I I I I I 0.6

0.5

0.4

0.3

0.2

NMOS 150/1 .O

(PISCES 116) Vd=8V, Vg=2V

0.1 1 ‘118 1.81 1.82 1.83 1.k 1.85 1.86 1.87 l.’k 1.89 l!9

Position (p m)

(b) Fig. 13. (a) Lateral distribution of interface traps near the drain junction for a virgin device and a CHC-stressed device. The origin of the X-axis is set at the left edge of the source which is 1 .0 pm in length. Two different base levels for the gate pulses V , = -4 V and V, = -7 V are used for the stressed device to cover a wider lateral range. (b) Electric field distribution in the same region during CHC stress at Vd = 8 V and V,! = 2 V, simulated with PISCES IIB.

[1]-[3]. Proper selection of V, has made such an obser- vation possible.

G. Application to PMOSFET’s In principle, this technique can be easily extended to

probe PMOSFET’s. Since PMOS has a negative Vr, one should use gate pulses with a fixed V, and varying V,. As an example, Fig. 14 shows the Zcp and dZcf / d V , versus V, curves measured on a 25/1.5 pm PMOSFET before and after CHC stressing at V, = -8 .6 V and Vg = -2 V. The gate pulses for the charge pumping measurement have a frequency of 100 kHz, rise/fall time of 200 ns, a fixed V,, = 8 V, and variable V,. The CHC-induced damage shows up as a separate peak in the dZcp/dVb curve, a few

PMOS 25/1.5 Stressed @I Vd=-8.6V. Vg=-PV

for 1000 sec

d 20

0 10

-4 -2 0 2 4 6 v b (v)

(b) Fig. 14. (a) I , and (b) dI,/dV, versus V,, curves before and after CHC stress at V, = -2 V , V , = -8.6 V for a 25/1.5 p m p-channel MOSFET.

volts away from the main peak. It suggests that a small portion of the channel has a high concentration of nega- tive oxide charge (approximately 2.8 X 10l2 cmP2).

By applying reverse bias on the drain, with properly selected V,, one should be able to obtain the lateral profile of Nit (x) according to the similar procedures described for the NMOSFET’s.

H . Projling of Negative Oxide Charge in NMOSFET’s

While CHC-induced positive oxide charge in NMOS- FET’s can be measured and profiled with the technique described earlier, the measurement of localized negative oxide charge in NMOSFET’s is more difficult, although CHC-induced negative charge is one of the major damage mechanisms in LDD NMOSFET’s. Its major conse- quence is that the electrons trapped in the spacer region cause a depletion of the n- region, which could increase the drain series resistance dramatically [ 131.

Using the charge pumping procedure described above, the localized negative charge should result in a bump on the right side of the main peak in the dZcf / d V , versus V, curve. However, because of the high IC,, there, the sensi- tivity is usually limited. This problem can be alleviated by arranging the gate pulse string as shown in Fig. 15(a), where the high level of the gate pulses (V,) is fixed and the base level (V,) is varied. In fact, this gate pulse ar- rangement is qualitatively the same as that used for PMOSFET’s as described above. With this Vb-varying gate pulse string, the localized negative charge and inter- face traps result in a bump on the right side of the dZCf /dV, curve, as shown in the lower part of Fig. 15(a).

194 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. 1 , JANUARY 1993

i r i ri r V h

1 - 1000

100

$ 10

E 1

0.1 4 .2 0 2 4

vb (v)

(b) Fig. 15. (a) Schematic illustration of V,-varying method. Top: Vh is above V, and the varying V, probes the interface traps in regions with V > V,. Bottom: illustrative Icp and dI,/dV, versus V, curves, where thz‘shoul- der” is due to the CHC-induced negative oxide charge. (b) Icp versus V, curves measured (using V,-varying method) on a 25/2.0 pm NMOSFET before and after stressing at V, = V, = -8.6 V .

As an example, a 25/2.0 pm NMOSFET was stressed at V, = Vd = 8.6 V for 500 s, and the pre-stress and post- stress Zcr and d&p/dVh versus Vh curves measured by the Vb-varying method are shown in Fig. 15(b). Note that the right-shifted shoulders in the post-stress Zcp and dZcp/dVb curves are due to trapped negative oxide charge. Our cal- culation indicates a density of negative oxide charge of 1.5 X 10l2 cm-2 in this case. Because only a small amount of interface traps are created, logarithmic scales are used to increase the visibility of the shoulders.

Lateral profiling of the negative oxide charge in NMOSFET’s using this Vb-varying charge pumping scheme, however, is much more difficult. This is because V’(x) and Vt(x) are affected by the drain bias in very dif- ferent ways (see Fig. 2), and it is much more difficult to determine the changes in the effective channel length when the threshold voltage distribution is varied by the drain bias while keeping V’ (x) unchanged.

In cases where a large number of negative charge and interface traps exist near the junctions, the standard Vh- varying method can still be used to obtain the profiles, although the sensitivity is limited, as discussed earlier.

V. COMPARISON WITH OTHER METHODS Thus far, we have demonstrated the ability and limita-

tions of this technique to profile the lateral distributions of both Not and Ni, near the drain/source junctions. There have been a number of other techniques published in the literature to measure the lateral distribution of CHC-in- duced Nit, but to our knowledge none has been shown to be capable of obtaining N,,(x). Therefore, we will only make brief comparisons concerning the measurement of Ni, (x) among some representative techniques.

A. Ancona et al. s Charge Pumping Technique [I] Similar to most conventional charge pumping measure-

ments, this technique uses gate pulses with a fixed ampli- tude and a varying base level. The authors apply drain- bias pulses of varying magnitude to obtain the lateral dis- tribution. The novel feature is their introduction of the “constant field” scheme with the drain pulses 180” out of phase with the gate pulses, which has also been adopted in our technique.

Therefore, the major difference between their technique and ours is in the gate pulses. In addition, we also take the derivative of the charge pumping current curve to ob- tain additional information (such as the oxide charge dis- tribution).

The major error introduced by their technique may arise from the fact that the base level of the gate pulses V,, which affects the depletion region width, is varied during their charge pumping measurement. We have shown in Fig. 7 that, in our devices, AL. can change by a significant amount when V, is changed from -7 V to -4 V. By fix- ing V,, out technique avoids this error.

B. Sur$ace Generation Current [2] Speckbacher et al. use surface generation current in a

slightly reverse-biased drain junction to probe the lateral distribution of generation centers [2]. By varying the gate voltage during the measurement, the lateral position at which interface defects contribute to the generation cur- rent can be changed, from which the lateral profile of the interface defects can be extracted. Since the generation current is typically very small (in the range of 1-100 fA), such a measurement is usually rather difficult. Further- more, as the authors have pointed out, the deep levels that are primarily responsible for generating the diode current are not necessarily the most relevant ones concerning MOSFET operation.

C. Su$ace Recombination Current [3] Asenov et al. measure surface recombination current of

the drain junction under low injection [3]. They also vary the gate voltage to probe the lateral distribution of surface recombination centers. Since recombination occurs at trap levels over a much wider range of energies than genera- tion, this technique is not confined to the probing of only deep levels, and is similar to the charge pumping tech- nique in this respect. The magnitude of the recombination current is also typically much higher than the generation current.

Methods described in Section V-B and -C require rel- atively simple measurements, but there are large uncer- tainties in the resulting interface-trap densities. The major problem is that, to extract interface-trap densities from the generatiodrecombination currents require the knowl- edge of the generatiodrecombination cross sections of the interface traps, which do not come out of such simple measurements. Additional measurements must be per- formed to obtain these capture cross sections. Although

CHEN et al.: LATERAL PROFILING OF OXIDE CHARGE AND INTERFACE TRAPS NEAR MOSFET JUNCTIONS 195

the average cross sections may be obtained by the charge pumping technique [8],[ 141, no one has yet demonstrated the measurement of such cross sections for highly non- uniformly distributed interface traps. In addition, it re- mains a question whether the cross sections measured by the charge pumping technique are the same as those in- volved in the generation/recombination processes under the conditions used in Section V-B or -C described above.

VI. SUMMARY We have described in detail a modified charge pumping

technique that allows lateral profiling of interface traps and oxide charge near the junctions of MOSFET’s. Its theoretical basis has been presented along with some il- lustrative examples. The experimental setup and physical principles are not significantly different from that of the widely used conventional charge pumping technique, and therefore it is easy to implement with good sensitivity.

If one is not interested in the lateral profiles, this tech- nique still offers the unique advantage of providing quan- titative information of the density of the oxide charge, either positive or negative, near the junctions of a MOS- FET.

The major limitatiop of this technique is the accessible lateral extent of the profiles. Very near or directly over the junction, it is limited by the rapidly changing dopant concentration, which makes it difficult to determine the threshold voltage distribution and the oxide charge profile in that region. In the other direction (toward the middle of the channel), it is limited by the magnitude of the drain bias that can be applied before the junction leakage or unintentional hot-carrier damage becomes unacceptable. Other limitations common to all charge pumping tech- niques, such as device geometry requirement, detectabil- ity of low interface-trap density, pulse shape, frequency range, etc., also apply to this technique.

ACKNOWLEDGMENT The authors wish to thank N. S. Saks for supplying the

samples.

~ E F E R E N C E S

[ l ] M. G. Ancona, N. S . Saks, and D. McCarthy, “Lateral distribution of hot-camer-induced interface traps in MOSFET’s,” IEEE Trans. Electron Devices, vol. 35, p. 2221, 1988.

[2] P. Speckbacher, A. Asenov, M. Bollu, F. Koch, and W. Weber, “Hot-camer-induced deep-level defects from gated-diode measure- ments in MOSFET’s,” IEEE Electron Device Lett . , vol. 11, p. 95, 1990.

[3] A. Asenov, J . Berger, P. Speckbacher, F. Koch, and W. Weber, “Spatially-resolved measurements of hot-carrier generated defects at the Si-SiO, interface,’’ in W. Eccleston and M. Uren, eds., Insulat- ing Films on Semiconductors, 1991 (Proc. 7th Biennial European Conk). Bristal, U.K., Adam Hilger, 1991, p. 247.

[4] W. Chen and T. P. Ma, “Channel-hot-carrier induced oxide charge trapping in NMOSFET’s,” in IEDM Tech. Dig . , 1991, p. 731.

[5 ] B. Doyle, M. Bourcerie, J . C. Marchetaux, and A. Boudou, “Inter- face state creation and charge trapping in the medium-to-high gate voltage range (Vd/2 2 V, 2 Vd) during hot-carrier stressing of n-MOS transistors,” IEEE Trans. Electron Devices, vol. 37. p. 744, 1990.

W. Chen and T. P. Ma, “A new technique for measuring lateral dis- tribution of oxide charge and interface traps near MOSFET junc- tions,” IEEE Electron Device Lett., vol. 12, p. 393, 1991. J . S. Brugler and P. G. A. Jespers, “Charge pumping in MOS de- vices,” IEEE Trans. Electron Devices, vol. ED-16, p. 297, 1969. G. Groeseneken, H. E. Maes, B. Bertran, and R. F. de Keers- maecker, “A reliable approach to charge pumping measurements in MOS transistors,” IEEE Trans. Electron Devices, vol. ED-31, p. 42, 1984. P. Heremans, J . Witters, G. Groeseneken, and H . E. Maes, “Anal- ysis of the charge pumping technique and its application for evalua- tion of MOSFET degradation,” IEEE Trans. Electron Devices, vol. 36, p. 1318, 1989. Y. Tada, C. Nagata, and M. Iwahashi, “Band-to-band tunneling as a probe for the hot-carrier effects,” in Proc. Solid State Device and Materials Conf., 1990, p. 315. K. T. San and T . P. Ma, “Determination of trapped oxide charge in FLASH EPROMs and MOSFETs with thin oxides,” IEEE Electron Device Lett., vol. 13, p. 439, 1992. G. A. Scoggan and T. P. Ma, “Effects of electron-beam radiation on MOS structures as influenced by the silicon dopant,” J . Appl. Phys., vol. 48, p. 294, 1977. S . Ogura, P. J. Chang, W. W. Walker, J . F. Shepard, and D. L. Critchlow, “Design and characteristics of the lightly-doped drain- source (LDD) insulated gate field effect transistor,” IEEE Trans. Electron Devices, vol. ED-27, p. 1359, 1980. W. Chen, A. Balasinski, B. Zhang, and T. P. Ma, “Hot-carrier ef- fects on interface-trap capture cross-sections in MOSFET’s as studied by charge pumping,” IEEE Electron Device Lett . , vol. 13, p. 201, 1992.

Wenliang Chen (S’91) was born in Wenzhou, China, on November 27, 1967. He received the B. S. degree in physics from Fudan University, Shanghai, China, in 1988, and the M.S., M.Phil., and Ph.D. degrees in applied physics from Yale University, New Haven, CT, in 1991, 1991, and 1992, respectively. His Ph.D. research was on hot-camer and radiation effects in MOS devices.

He developed several new characterization techniques for the study of hot-camer and radia- tion effects. He has published over a dozen tech-

nical papers in referred journals, and made several presentations in inter- national conferences. He was a co-op engineer at Cypress Semiconductor, San Jose, CA, during the summer of 1991, working on BiCMOS process integration. He is currently a senior device engineer at Intel Corporation, Portland, OR, involved in technology development for logic IC’s.

Artur Balasinski was born in Warsaw, Poland, on June 30, 1957. He received the M.S. degree for work on MOS solar cells in 1980, and the Ph.D. degree in 1987 for a study on radiation ef- fects in MOS structures, both from Warsaw Uni- versity of Technology, Institute of Microelec- tronics and Optoelectronics.

He worked at Warsaw University of Technol- ogy, as a staff member (1985-1986), research as- sistant (1986- 1988), and assistant professor (1988-1989) at the Faculty of Electronics. In

1987, he spent six months at Scientific-Production Semiconductor Center in Warsaw, participating in MOS device fabrication and measurements. In 1989, he joined the Department of Electrical Engineering, Yale University, New Haven, CT, to continue work on MOS device characterization and processing. He contributed to two book chapters, and about fifty publica- tions on radiation effects, process-induced defects, thin dielectric proper- ties, interface physics, and new measurement methods. In l987, he re- ceived an award for his research accomplishments from the Rector (President) of the Warsaw University of Technology. His current research interest is mainly in edge-effects in small-geometry MOSFET’s.

Dr. Balasinski is a member of the Electrochemical Society.

196 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 40, NO. I , JANUARY 1993

Tso-Ping Ma (S’72-M’74-SM’83) received the B.S. degree in electrical engineering in 1968 from the National Taiwan University and the M.S. and Ph.D. degrees from Yale University, New Haven, CT, in 1972 and 1974, respectively.

From 1974 to 1977 he was at IBM’s East Fish- kill Facility, Yorktown Heights, NY, where he worked on exploratory MOS devices, electron- beam lithography, process-induced radiation ef- fects, and RF plasma annealing technique. In 1976 he took a leave of absence from IBM, and joined

the Department of Engineering and Applied Science at Yale University, New Haven, CT, as a visiting lecturer. In 1977 he joined Yale faculty as an assistant professor, was promoted to associate professor in 1980, and since 1985 has been a professor in the Department of Electrical Engineer- ing at Yale University. He has served on many committees in the univer- sity, was Acting Chairman of the Department in 1988, and currently the Chairman. His research and teaching have focused on semiconductors,

MOS interface physics, ionizing radiation and hot-electron effects, and mi- croelectronidoptoelectronic materials and process. He received the Hard- ing Bliss Award at Yale University in 1975, was elected as a GE Whitney Symposium Lecturer in 1985, and received a Connecticut Yankee Inge- nuity Award in 1991, He is a patent holder, coeditor of a book, and con- tributed to several book chapters and over 150 research papers.

Dr. Ma was the Arrangement Chairman (1986), the Technical Program Chairman (1987), and the General Chairman (1988) of the IEEE Semicon- ductor Interface Specialists Conference, and served on the program com- mittees and as session chairman in numerous other conferences, including IEEE/DRC, IEEEINSREC, ESC, MRS, and International Symposium on VLSI. He was the Vice President (1986-1987) and the President (1987- 1988) of the Yale Chapter of the Sigma Xi Society. He has served on the Board of Directors of the New Haven Chinese School since 1981, and was the President of the New Haven Chapter of the Organization of Chinese Americans for 1989 and 1990. He is a member of APS, ECS, MRS, Sigma Xi, YSEA, and the Connecticut Academy of Science and Engineering.