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August 2012 Revision: EB43_01.2 LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
August 2012Revision: EB43_01.2
LatticeECP3 PCI Express Solutions Board – Revision A
User’s Guide
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
IntroductionAs PCI Express applications have emerged, the LatticeECP3™ FPGA family has become a well-suited solution for many system designs. The features of the LatticeECP3 PCI Express Solutions Board can assist engineers with rapid-prototyping and testing their designs. The board is an enhanced form-factor of the PCI Express add-in card specification. It allows for full x1 form-factor compliance and x4 is available for demonstration purposes with some non-standard form-factor issues. The flexibility to use the same board to demonstrate both x1 and x4 configurations is accomplished by simply changing the mounting hardware. The board has several debugging and analyzing fea-tures for complete evaluation of the LatticeECP3 device. This guide is intended to be referenced in conjunction with evaluation design tutorials to demonstrate the LatticeECP3 FPGA.
This user’s guide describes the LatticeECP3 PCI Express Solutions Board featuring the LatticeECP3 LFE3-95EA-FN672 FPGA. The stand-alone evaluation board provides a functional platform for development and rapid prototyp-ing of applications that require high-speed SERDES interfaces to demonstrate PCI Express capabilities using an add-on card form-factor. The board is manufactured using standard FR4 dielectric and through-hole vias. The nom-inal impedance is 50-ohm for single-ended traces and 85-ohm for differential traces.
Important: This document (including the schematics in the appendix) describes LatticeECP3 PCI Express Solu-tions Boards marked as Rev A. This marking can be seen on the silkscreen of the printed circuit board, under the Lattice Semiconductor logo.
Figure 1. LatticeECP3 PCI Express Solutions Board
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Features• PCI Express x1 and x4 edge connector interfaces
• Allows demonstration of PCI Express (x 1and x4) interfaces– x1 is form-factor compliant and will fit a standard PC-equipped PCI Express motherboard socket– x4 is non-compliant but will demonstrate x4 functionality by a simple change to the hardware
• Allows control of SERDES PCS registers using the Serial Client Interface (ORCAstra)
• On-board Boot Flash– Both Serial SPI Flash and Parallel Flash via MachXO™ programming bridge
• Shows interoperation with a high performance DDR2 memory component
• Includes driver based “run-time” device configuration capability via ORCAstra or PCI Express
• Switches, LEDs, displays for demo purposes
• Input connection for lab-power supply
• Power connections and power sources
• ispVM™ programming support
• On-board and external reference clock sources
The contents of this user’s guide include top-level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics of the board.
Figure 2. PCI Express Solutions Board Outline Drawing, Top Side
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 3. PCI Express Solutions Board Outline Drawing, Bottom Side
x1 and x4 PCI Express SupportPCI Express x1 and x4 is supported with the same PCB. This add-in PCB is designed to work in both types of motherboard slots. The PCB complies with the width and length dimensions of the PCI Express Card Electrome-chanical (CEM) Specification Revision 1.1. The only exclusion of the CEM specification is the component and back side of the add-in board may interfere with other boards in a fully-populated motherboard.
This board is easily interchanged from x1 to x4 configurations by removing the back-panel bracket and reinstalling it on the opposite side. This permits plug-in into PCI Express sockets on the motherboard and securing it in the chassis if desired. The back-panel bracket is shown below.
Figure 4. Back Panel Drawing
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
LatticeECP3 DeviceThis board features a LatticeECP3 FPGA with a 1.2V core supply. It can accommodate all pin compatible LatticeECP3 devices in the 672-ball fpBGA (1mm pitch) package. A complete description of this device can be found in the LatticeECP3 Family Data Sheet on the Lattice website at www.latticesemi.com.
Note: The connections referenced in this document refer to the LFE3-95EA-FN672 device. Available I/Os and associated sysI/O™ banks may differ for other densities within this device family.
Applying Power to the BoardThe LatticeECP3 PCI Express Solutions Board is ready to power on. The board can be supplied with power from an AC wall-type transformer power supply shipped with the board. Or it can be supplied from a benchtop supply via terminal screw connections. It also has provisions to be supplied from the PCI Express edge fingers from a host board.
To supply power from the factory-supplied wall transformer, simply connect the output connection of the power cord to J1 and plug the wall-transformer into an AC wall-outlet.
Power Supplies(see Appendix A, Figure 21)
The evaluation board incorporates an alternate scheme to provide power to the board. The board is equipped to accept a main supply via the TB1 connection. This connection is provided to use with a benchtop supply adjusted to provide a nominal +12V DC.
All input power sources and on-board power supplies are fused with surface-mounted fuses and have green LEDs to indicate power GOOD status of the intermediate supplies
Table 1. Board Power Supply Fuses (see Appendix A, Figure 21)
F1 12V Fuse
F2 1.2V Core Fuse
F3 3.3V Fuse
F4 1.8V Fuse
F5 1.2V Analog Supply
Table 2. Board Power Supply Indicators (see Appendix A, Figure 21)
D1 3.3V Source Good Indicator
D2 1.2V VCC Core Source Good Indicator
D3 1.8V Source Good Indicator
D4 1.2V Analog Source Good Indicator
D5 12V Input Good Indicator
External power can be alternatively connected rather than the wall transformer power pack.
Table 3. External Board Supply Input Terminal (see Appendix A, Figure 21)
TB1Screw terminal for +12V DCPin1 (square PCB pad): +12V DCPin2: Ground
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
PCI Express Power InterfacePower can be sourced to the board via the PCB edge-fingers (CN1 and CN2). This interface allows the user to pro-vide power from a PCI Express Host board.
Programming/FPGA Configuration(see Appendix A, Figure 23)
A programming header is provided on the evaluation board, providing access to the LatticeECP3 JTAG port.
ispVM Download InterfaceJ4 and J8 are 6-pin JTAG connectors used in conjunction with the ispVM USB download cable to program and con-trol the device. These connectors are available through the back-panel bracket as needed for x1 or x4 PCI Express configurations. These connectors are used in conjunction with the ispVM programming cable and software to pro-gram the configuration memory or FPGA directly.
Table 4. Standard ispVM Programming Cable Configuration
Pin 1 VCC
Pin 2 TDO
Pin 3 TDI
Pin 4 TMS
Pin 5 GND
Pin 6 TCK
After initial board setup, use the following procedure to program the evaluation board. Instructions assume ispVM software has been installed on a local PC.
Connect the ispDOWNLOAD cable rainbow colored flywires to the connector J4.
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Table 5. ispVM JTAG Connector (see Appendix A, Figure 21)
6 3 2 15 4Note: A dot denotes PIN 1 on the both the PCB or back-panel bracket.
Pin Function Color
1 PWR Red
2 TDO Brown
3 TDI Orange
4 TMS Purple
5 GND Black
6 TCK White
Figure 5. ispVM Programming Cable Connector
Programming the Daisy ChainThis board includes two Lattice Semiconductor programmable (U1=LFE3-95, U12=LCMXO1200) devices that can be programmed in a daisy chain.
Figure 6. JTAG Chain
LatticeECP3FPGA(U1)
MachXO1200CPLD(U13)
TCK TMS TDI TDO
TCK
TMS
TDI TDO
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Download ProceduresRequirements:
• PC with ispVM System v.17.7 (or later) programming management software, installed with appropriate drivers (USB driver for USB Cable, Windows NT/2000/XP parallel port driver for ispDOWNLOAD Cable).
Note: An option to install these drivers is included as part of the ispVM System setup.
• ispDOWNLOAD Cable (pDS4102-DL2A, HW7265-DL3A, HW-USB-1A, etc.)
JTAG DownloadThe LatticeECP3 device can be configured easily via its JTAG port. The device is SRAM-based; it must remain powered on to retain its configuration when programmed in this fashion.
1. Connect the LatticeECP3 PCI Express Solutions Board to the appropriate power sources and power up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J4 is used for the 1x6 connection. J8 is used in the same manner for x4 configurations.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LatticeECP3 and the MachXO1200 devices should be auto-matically detected.
Figure 7. ispVM Main Window
5. Double-click the device to open the device information dialog. In the device information dialog, click the Browse button located under Data File. Locate the desired bitstream file (.bit). Click OK to both dialog boxes.
6. To program only the LatticeECP3-95, place the LCMXO1200C device into BYPASS and the LFE3-95 should be in FAST PROGRAM mode.
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 8. ispVM Fast Programming Mode
Figure 9. ispVM Device Information Dialog Box
7. Add Data File.
8. Click the green GO button. This will begin the download process into the device. Upon successful download, the device will be operational.
Configuration Status Indicators(see Appendix A, Figure 23)
These LEDs indicate the status of configuration to the FPGA.
• D6 (red) illuminated, this indicates that the programming was aborted or reinitialized driving the INITN output low.
• D9 (green) is illuminated, this indicates the successful completion of configuration by releasing the open collector DONE output pin.
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
• D10 (green) will flash indicating TDI activity.
• D8 (red) illuminated, this indicates that PROGRAMN is low.
• D7 (red) illuminated, this indicates that GSRN is low.
PROGRAMN & GSRN(see Appendix A, Figure 23)
• These push-button switches assert/de-assert the logic levels on the PROGRAMN (SW3 or SW7) and GSRN (SW1 or SW6). Depressing the button drives a logic level “0” to the device.
• These push-buttons are accessible from the back panel if the evaluation board is mounted in a PCI Express slot of a PC.
CFG [2:0](see Appendix A, Figure 23)
• The FPGA CFG pins are set on the board for a particular programming mode via the SW2 DIP switch.
• JTAG programming is independent of the MODE pins and is always available to the user.
• Pushing in (depressing) the switch is ON and sets the value to 0.
Table 6. CFG Mode Selections
CFG2 CFG1 CFG0 Configuration Mode
0 (ON) 0 (ON) 0 (ON) SPI Flash
0 (ON) 1 (OFF) 0 (ON) SPIm
1 (OFF) 0 (ON) 1 (OFF) Slave Serial
1 (OFF) 1 (OFF) 1 (OFF) Slave Parallel
X (don’t care)
X (don’t care)
X (don’t care) ispJTAG™
On-Board Serial SPI Flash Memory(see Appendix A, Figure 23)
• One Serial SPI (16-pin tssop 64M) Flash memory device (U6) is on-board for non-volatile configuration memory storage. Either a STMicro M25P64VMF16 or Macronix MX25L6405 device is populated on-board.
• All CFG [2:0] need to be [000] depressed to read the Flash memory at power-up or after toggling the PRO-GRAMN pin.
• Install jumper across pins 2 and 4 on J2.
Programming Serial SPI Flash MemoryThe Serial SPI Flash memory device can be configured easily via its JTAG port. This mode enables the FPGA to be programmed at power-up or assertion of PROGRAMN with a bitstream stored in the memory device.
1. Connect the LatticeECP3 PCI Express Solutions Board to the appropriate power sources and power-up board.
2. Connect the ispDOWNLOAD cable to the appropriate header. J4 is used with the cable.
3. Start the ispVM System software.
4. Press the SCAN button located in the toolbar. The LFE3-95 and the LCMXO1200C devices should be automat-ically detected.
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Figure 10. Results of Scanning Board via ispVM
5. Double-click the Operation column for the LFE3-95 and the Device Dialog box shown below will open.
6. In the dialog box, select the SPI Flash Programming mode in the Device Access Options pull-down menu. This will open the SPI Serial Flash Dialog box.
Figure 11. Device Information Dialog Screen
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Figure 12. SPI Serial Flash Dialog Screen
7. The SPI Serial Flash Device dialog box will open. In this box select SPI Flash Erase, Program, Verify in the Operation pull-down menu.
8. Select SPI Serial Flash in the Device Family pull-down menu, STMicro under the Vendor pull-down menu, SPI-M2564 under the Device pull-down menu, and 16-lead SOIC under the Package submenu.
Figure 13. Select Device Dialog Box
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 14. Sample SPI Serial Flash Device Dialog Box
9. Click OK in the SPI Flash Device dialog box. Then click OK in the Select Device dialog box. You will then return to the main configuration screen. If you do not desire to load the LCMXO1200C device, this device should be placed in Flash Bypass mode by double-clicking the Operation column and selecting the Bypass operation shown below.
Figure 15. FLASH Bypass for LCMXO1200C Device
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 16. Programming Main Window
10.From the main programming window, select GO in the top toolbar. This will begin the SPI Serial Flash program-ming.
Figure 17. SPI Serial Flash Programming Status Window
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 18. Successful SPI Serial Flash Programming Session
On-Board Parallel SPI Flash Memory(see Appendix A, Figure 24)
• A 16-bit parallel Flash device is also available. This board uses a Lattice MachXO CPLD device to act as a pro-gramming bridge from the Flash device.
• The CFG [2:0] need to be [111], all up.
• Lattice ispVM programming software can be used to program either the serial SPI Flash or the parallel Flash devices. Application note AN8077, Parallel Flash Programming and FPGA Configuration, addresses the use of the parallel Flash implementation. Note: For parallel Flash loading, the board needs the appropriate connections of J2. J2 requires a jumper be installed between pins 1 and 3.
User-Defined General Purpose Clock Oscillator(see Appendix A, Figure 27, Y1)
A 100MHz oscillator is included on-board. It is fanned-out to several destinations on the board, as described in Table 7.
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Table 7. 100MHz Clock Destinations
Clock Destination PCB Designation Destination Pin
CPLD U12 A8
FPGA U1 P21-PCLKT2_0
FPGA U1 K3-LLUM0-GDLLT_IN
FPGA U1 M4-PCLKT7_0
SERDES (see Appendix A, Figure 25)
SERDES/FPGA Reference ClocksThe 50-ohm terminated SMA connectors are optionally provided to supply reference clocks directly to the LatticeECP3 device. Please contact the factory for information to populate the PCB with SMA connectors.
Table 8. SMA Inputs for External Clock Source
Connector SERDES Signal FPGA Pin
J6 FPGA_SMA_REFCLKP V20
J7 FPGA_SMA_REFCLKN W19
SERDES PCI Express Channels(see Appendix A, Figure 25)
This board is equipped to communicate directly as an add-on card to a PCI Express host. It is designed with edge-fingers (CN1 or CN2) that fit directly into a PCI Express host receptacle. Power can be supplied directly from the PCI Express host via the edge-finger connections.
Table 9. x1 PCI Express Connections
CML Pin Name FPGA Pin PCIE PCI Express Edge Description
PCSA_HDOUTP_0 AF21 PERp0 A16Integrated endpoint block transmit pair
PCSA_HDOUTN_0 AF20 PERn0 A17
PCSA_HDINP_0 AD21 PETp0 B14Integrated endpoint block receive pair
PCSA_HDINN_0 AD20 PETn0 B15
PCSA_REFCLKP AC17 PCIe_CLKp A13Integrated endpoint block differential clock pair
PCSA_REFCLKN AC18 PCIe_CLKn A14
PCIE_PERSETN U20 PERSTN A11 Fundamental PCI Express reset
Table 10. x4 PCI Express Connections
CML Pin Name FPGA Pin PCIE PCI Express Edge Description
PCSB_HDOUTP_0 AF13 PERp0 A16Integrated endpoint block transmit pair
PCSB_HDOUTN_0 AF12 PERn0 A17
PCSB_HDINP_0 AD13 PETp0 B14Integrated endpoint block receive pair
PCSB_HDINN_0 AD12 PETn0 B15
PCSB_HDOUTP_1 AF10 PERp1 A21Integrated endpoint block transmit pair
PCSB_HDOUTN_1 AF11 PERn1 A22
PCSB_HDINP_1 AD10 PETp1 B19Integrated endpoint block receive pair
PCSB_HDINN_1 AD11 PETn1 B20
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
FPGA Test Pins(see Appendix A, Figure 27)
General Purpose DIP Switch(see Appendix A, Figure 27, SW5)
General-purpose FPGA pins are available for user applications. FPGA pins are connected to a switch (SW5) which is an SPST side actuated DIP switch. The switch is physically located on the secondary side of the PCB along the back-panel edge. The switches are connected to a logic level 0 when depressed toward the board and a 1 when away from the board. The designated pins are connected according to Table 11.
Table 11. FPGA Test Pins (See Appendix A, Figure 26)
FPGA BGA SW5 Switch Position
D9 1
1 2 3 4 5 6 7 8
Logic 1
Logic 0
PCB
F9 2
G8 3
A6 4
A5 5
E9 6
E8 7
A7 8
PCSB_HDOUTP_2 AF9 PERp2 A25Integrated endpoint block transmit pair
PCSB_HDOUTN_2 AF8 PERn2 A26
PCSB_HDINP_2 AD9 PETp2 B23Integrated endpoint block receive pair
PCSB_HDINN_2 AD8 PETn2 B24
PCSB_HDOUTP_3 AF6 PERp3 A29Integrated endpoint block transmit pair
PCSB_HDOUTN_3 AF7 PERn3 A30
PCSB_HDINP_3 AD6 PETp3 B27Integrated endpoint block receive pair
PCSB_HDINN_3 AD7 PETn3 B28
PCSB_REFCLKP AC9 PCIe_CLKp A13Integrated endpoint block differential clock pair
PCSB_REFCLKN AC10 PCIe_CLKn A14
PCIE_PERSETN U20 PERSTN A11 Fundamental PCI Express reset
Table 10. x4 PCI Express Connections (Continued)
CML Pin Name FPGA Pin PCIE PCI Express Edge Description
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 19. 8-position DIP Switch (SW5) on Secondary PCB Side
General Purpose LEDs(see Appendix A, Figure 27)
LEDs are provided along the back panel edge of the PCB. These LEDs are connected to general-purpose FPGA I/Os. The LEDs are illuminated by the associated FPGA outputs being driven to a valid LOW level. The use of these LEDs is defined for PCI Express applications to observe the status of the PCI Express link during operation. The LEDs must be included in the FPGA design. These status LEDs are available in both x1 or x4 configurations. The back panel marking reflects PCI Express specific status.
Table 12. LED Definitions
PCI Express x1 PCI Express x4
FPGA Pin# PCB Designator FPGA Pin# PCB Designator Description
H11 D19 C10 D20 User defined
H10 D21 A9 D22 User defined
F11 D26 A10 D27 User defined
G11 D24 B10 D25 User defined
D10 D11 D10 D12 Data link up active
F10 D13 A8 D14 L0 state active
G9 D15 B8 D16 Polling state inactive
G10 D17 C9 D18 PLL locked
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
General-Purpose Header(see Appendix A, Figure 27, J5)
A 2x9 header (J5) provides a general-purpose connection to communicate with general purpose FPGA I/Os.
Table 13. General Purpose Header Connections
Header Pin FPGA Pin Header Pin FPGA Pin
1 GND 2 GND
3 C15 4 E15
5 B15 6 E14
7 C14 8 A20
9 D14 10 A19
11 B16 12 C17
13 C16 14 B17
15 F13 16 A18
17 F14 18 A17
17-Segment LED Display(see Appendix A, Figure 27, D13)
General-purpose FPGA pins are connected to a 17-segment display according to Table 14. These pins can be driven low to illuminate the display segments.
Table 14. 17-Segment LED Display
Segment BGA
A
B
C
D
E
F
G
H
K
M
N
P
R
S
T
U
DP
B7
F8
F7
A4
A3
H8
G7
C8
D8
B4
C5
C6
D6
C4
D5
C7
B6
A B
C
DG
F E DP
H
T S R
K M N
U P
Logic Analyzer Probe(see Appendix A, Figure 27, LA1)
An AMP/TYCO 767004 38-position .025 VERT SMD logic analyzer probe connection is provided for the user to uti-lize for test points. This connection provides 34 general I/O signals to be observed on a Logic Analyzer probe using Mictor connections such as the Agilent 5346A.
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LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Table 15. Logic Analyzer To FPGA Pin Reference
Signal FPGA Pin Signal FPGA Pin
LA1 AA25 LA2 Y24
LA3 W23 LA4 W22
LA5 AA26 LA6 AB26
LA7 W21 LA8 W20
LA9 AD26 LA10 AD25
LA11 AA24 LA12 AA23
LA13 AC26 LA14 AC25
LA15 Y19 LA16 Y20
LA17 AB24 LA18 AC24
LA19 Y22 LA20 AA22
LA21 AE25 LA22 AF24
LA23 AD24 LA24 AE24
LA25 AD23 LA26 AC23
LA27 AB20 LA28 AB21
LA29 AF23 LA30 AE23
LA31 W17 LA32 AB23
LA33 AB22 LA34 Y21
DDR2 Memory Devices(see Appendix A, Figure 26, U14)
• The LatticeECP3 PCI Express Solutions Board is equipped with a 84-ball BGA DDR2 SDRAM memory device such as a Micron MT47H16M16BG-3 device.
• The DDR2 memory interfaces include a 16-bit wide device.
• The evaluation board includes termination of address and command signals. It includes all power and external components needed to demonstrate the memory controller of the LatticeECP3 device.
CPLD Device(see Appendix A, Figure 24, U12)
The board includes a Lattice Semiconductor LCMXO-1200C CPLD. This device is used in conjunction with the par-allel Flash device for loading the configuration memory of the FPGA. It is also used for general-purpose board management functions. It has several connections to the FPGA and other devices on the PCB. It includes an active high, push-button (SW4) if needed for a user design.
Generic user-defined interconnections are defined in Table 16.
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Table 16. CPLD TO FPGA Interconnections
CPLD Pin FPGA Pin
M1 B2
P13 B3
P10 D4
N7 E4
N8 C3
P11 D3
N13 G5
N1 G6
N3 E3
N4 F4
P1 H6
M12 J6
M2 C2
M3 D2
M4 K8
M6 J7
Ordering Information
Description Ordering Part NumberChina RoHS Environment-Friendly
Use Period (EFUP)
LatticeECP3 PCI Express Development Kit(Includes LatticeECP3 PCI Express Solutions Board)
LFE3-95EA-PCIE-DKN
Technical Support AssistanceHotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision HistoryDate Version Change Summary
March 2010 01.0 Initial release.
December 2010 01.1 LED definitions table, L0 state changed from active to inactive.
Download Procedures section, changed ispVM requirement from ispVM v.17.4 (or later) to ispVM v.17.7 (or later).
August 2012 01.2 Updated document with new corporate logo.
Replaced Programming schematic.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Appendix A. SchematicFigure 20. Cover Page
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PCIe-X1
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CH0
CH3
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LOOPS
16- GPIO HEADER
LOGIC ANALYZER PROBE
JTAG/ISPVM
STATUS LEDs
16-SEGMENT DISPLAY
DIP SWITCH
100MHZ
GENERAL
OSC.
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Figure 21. Power Generation5 5
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boar
d
PO
WE
R IN
PU
T
3.3V
12V
IN G
OO
D+12VDC
GND
1.2V
Ana
log
PO
WE
R R
AIL
GO
OD
IND
ICA
TO
RS
1.2V
VC
C_C
OR
E1.
8V3.
3V1.
2VA
nalo
gT
P2
Tes
tPoi
nt
TP
2
Tes
tPoi
nt1
F3
F12
28C
T-N
D
5A F
ast-
Blo
SM
T S
ocke
ted
Fus
e
F3
F12
28C
T-N
D
5A F
ast-
Blo
SM
T S
ocke
ted
Fus
e
LP1 50
16
LP1 50
16
11
TB
1
Ter
min
al B
lock
/ED
1202
DS
TB
1
Ter
min
al B
lock
/ED
1202
DS
1 2
TP
4
Tes
tPoi
nt
TP
4
Tes
tPoi
nt1
R5
220R
-060
3SM
TR
522
0R-0
603S
MT
R2
1_8K
-120
6SM
TR
21_
8K-1
206S
MT
F1
F12
51C
T-N
D10
A F
ast-
Blo
SM
T S
ocke
ted
Fus
e
F1
F12
51C
T-N
D10
A F
ast-
Blo
SM
T S
ocke
ted
Fus
e
R13
12_1
K-0
603S
MT
R13
12_1
K-0
603S
MT
TP
6
Tes
tPoi
nt
TP
6
Tes
tPoi
nt1
R18
806R
-060
3SM
T
R18
806R
-060
3SM
T
LP3 50
16
LP3 50
16
11
G
D4
LED
-SM
T12
06_G
RE
EN
G
D4
LED
-SM
T12
06_G
RE
EN
+C
9
10U
F-1
6V-T
AN
TB
SM
T+
C9
10U
F-1
6V-T
AN
TB
SM
T
TP
8
Tes
tPoi
nt
TP
8
Tes
tPoi
nt1
F5
F12
28C
T-N
D5A
Fas
t-B
lo S
MT
Soc
kete
d F
use
F5
F12
28C
T-N
D5A
Fas
t-B
lo S
MT
Soc
kete
d F
use
R12
OP
EN
-080
5SM
TR
12O
PE
N-0
805S
MT
+C6
330U
F-F
KS
MT
+C6
330U
F-F
KS
MT
R9
0R-0
603S
MT
R9
0R-0
603S
MT
LP2 50
16
LP2 50
16
11
R3
1_8K
-120
6SM
TR
31_
8K-1
206S
MT
TP
10
Tes
tPoi
nt
TP
10
Tes
tPoi
nt1
R16
100R
-080
5SM
TR
1610
0R-0
805S
MT
+C5
330U
F-F
KS
MT
+C5
330U
F-F
KS
MT
+C8
330U
F-F
KS
MT
+C8
330U
F-F
KS
MT
+C
310
UF
-16V
-TA
NT
BS
MT
+C
310
UF
-16V
-TA
NT
BS
MT
TP
12
Tes
tPoi
nt
TP
12
Tes
tPoi
nt1
R8
10K
-060
3SM
T
R8
10K
-060
3SM
T
J1
22H
P03
7-2.
1mm
Mal
e P
ower
Jac
k 2.
1mm
J1
22H
P03
7-2.
1mm
Mal
e P
ower
Jac
k 2.
1mm
13
2
+C
147
0UF
-FK
SM
T
+C
147
0UF
-FK
SM
T
R14
2K-0
603S
MT
R14
2K-0
603S
MT
R19
1K-0
603S
MT
R19
1K-0
603S
MT
D33
SC
HO
TT
KY
/VIS
HA
Y-V
12P
10D
33S
CH
OT
TK
Y/V
ISH
AY
-V12
P10
Q3
2N22
22/S
OT
23Q3
2N22
22/S
OT
23
3
1
2
G
D1
LED
-SM
T12
06_G
RE
EN
G
D1
LED
-SM
T12
06_G
RE
EN
TP
1
Tes
tPoi
nt
TP
1
Tes
tPoi
nt1
Q1
2N22
22/S
OT
23Q1
2N22
22/S
OT
23
3
1
2
U5
SC
1592
U5
SC
1592
ILIM
1
IN2
CN
TL
3
GN
D4
OU
T5
SE
NS
E6
EN
7
TA
B8
R6
10K
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3SM
T
R6
10K
-060
3SM
T
U2
PT
H12
060L
U2
PT
H12
060L
GN
D1
VIN
2
INHIBIT# 3
ADJUST 4
SE
NS
E5
VO
UT
6
GND 7TRACK8
MDWN9
MUP10
R10
0R-0
603S
MT
R10
0R-0
603S
MT
TP
3
Tes
tPoi
nt
TP
3
Tes
tPoi
nt1
R4
1_8K
-120
6SM
TR4
1_8K
-120
6SM
T
Q2
2N22
22/S
OT
23Q2
2N22
22/S
OT
23
3
1
2
+C
210
0UF
-FK
SM
T
+C
210
0UF
-FK
SM
T
R11
OP
EN
-080
5SM
TR
11O
PE
N-0
805S
MT
R15
100R
-080
5SM
TR
1510
0R-0
805S
MT
R21
10K
-060
3SM
TR
2110
K-0
603S
MT
LP5 50
16
LP5 50
16
11
F4
F12
28C
T-N
D5A
Fas
t-B
lo S
MT
Soc
kete
d F
use
F4
F12
28C
T-N
D5A
Fas
t-B
lo S
MT
Soc
kete
d F
use
G
D3
LED
-SM
T12
06_G
RE
EN
G
D3
LED
-SM
T12
06_G
RE
EN
TP
5
Tes
tPoi
nt
TP
5
Tes
tPoi
nt1
G
D5
LED
-SM
T12
06_G
RE
EN
G
D5
LED
-SM
T12
06_G
RE
EN
R17
1K-0
603S
MT
R17
1K-0
603S
MT
TP
7
Tes
tPoi
nt
TP
7
Tes
tPoi
nt1
R1
1_8K
-120
6SM
TR1
1_8K
-120
6SM
T
+C
7
10U
F-1
6V-T
AN
TB
SM
T+
C7
10U
F-1
6V-T
AN
TB
SM
T
R20
2K-0
603S
MT
R20
2K-0
603S
MT
R7
10K
-060
3SM
T
R7
10K
-060
3SM
T
U3
PT
H12
060W
U3
PT
H12
060W
GN
D1
VIN
2
INHIBIT# 3
ADJUST 4
SE
NS
E5
VO
UT
6
GND 7TRACK8
MDWN9
MUP10LP
4 5016
LP4 50
16
11T
P9
Tes
tPoi
nt
TP
9
Tes
tPoi
nt1
+C
410
UF
-16V
-TA
NT
BS
MT
+C
410
UF
-16V
-TA
NT
BS
MT
U4
SC
1592
U4
SC
1592
ILIM
1
IN2
CN
TL
3
GN
D4
OU
T5
SE
NS
E6
EN
7
TA
B8
TP
11
Tes
tPoi
nt
TP
11
Tes
tPoi
nt1
G
D2
LED
-SM
T12
06_G
RE
EN
G
D2
LED
-SM
T12
06_G
RE
EN
+C10
330U
F-F
KS
MT
+C10
330U
F-F
KS
MTF2
F12
28C
T-N
D5A
Fas
t-B
lo S
MT
Soc
kete
d F
use
F2
F12
28C
T-N
D5A
Fas
t-B
lo S
MT
Soc
kete
d F
use
R22
10K
-060
3SM
TR
2210
K-0
603S
MT
24
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 22. Power Supplies5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
VC
C_C
OR
E
VC
C_C
OR
E
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C_P
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C_P
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Titl
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C12
1000
PF
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2SM
T
C12
1000
PF
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2SM
T
C83
1000
PF
-040
2SM
T
C83
1000
PF
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2SM
T
C75
100N
F-0
603S
MT
C75
100N
F-0
603S
MT
C31
100N
F-0
603S
MT
C31
100N
F-0
603S
MT
EC
P3-
672f
pBG
A
U1J
EC
P3-
672f
pBG
A
U1J
VC
CA
V13
VC
CA
V14
VC
CA
W12
VC
CA
W13
VC
CA
W14
VC
CA
W15
VC
CA
Y13
VC
CA
Y14
VC
CA
UX
J11
VC
CA
UX
J16
VC
CA
UX
J18
VC
CA
UX
J9
VC
CA
UX
L18
VC
CA
UX
L9
VC
CA
UX
T18
VC
CA
UX
T9
VC
CA
UX
V11
VC
CA
UX
V16
VC
CA
UX
V18
VC
CA
UX
V9
VC
CP
LL_L
M10
VC
CP
LL_L
R10
VC
CP
LL_R
M17
VC
CP
LL_R
R17
C82
100N
F-0
603S
MT
C82
100N
F-0
603S
MT
C54
10N
F-0
603S
MT
C54
10N
F-0
603S
MT
MH
2
M H
OLE
2
MH
2
M H
OLE
2
C64
1000
PF
-040
2SM
T
C64
1000
PF
-040
2SM
T
C22
10N
F-0
603S
MT
C22
10N
F-0
603S
MT
C71
1UF-16V-0805SMT
C71
1UF-16V-0805SMT
C17
1000
PF
-040
2SM
T
C17
1000
PF
-040
2SM
T
C56
1000
PF
-040
2SM
T
C56
1000
PF
-040
2SM
T
C80
10N
F-0
603S
MT
C80
10N
F-0
603S
MT
C35
100N
F-0
603S
MT
C35
100N
F-0
603S
MT
C63
1000
PF
-040
2SM
T
C63
1000
PF
-040
2SM
T
+C
69
22UF-16V_TANTBSMT
+C
69
22UF-16V_TANTBSMT
C24
10N
F-0
603S
MT
C24
10N
F-0
603S
MT
C46
100N
F-0
603S
MT
C46
100N
F-0
603S
MT
C34
1UF-16V-0805SMT
C34
1UF-16V-0805SMT
C77
1UF-16V-0805SMT
C77
1UF-16V-0805SMT
C14
1000
PF
-040
2SM
T
C14
1000
PF
-040
2SM
T
C37
1000
PF
-040
2SM
T
C37
1000
PF
-040
2SM
T
C21
10N
F-0
603S
MT
C21
10N
F-0
603S
MT
C57
1000
PF
-040
2SM
T
C57
1000
PF
-040
2SM
T
C26
1UF-16V-0805SMT
C26
1UF-16V-0805SMT
+C
81
22UF-16V_TANTBSMT
+C
81
22UF-16V_TANTBSMT
+C
29
22UF-16V_TANTBSMT
+C
29
22UF-16V_TANTBSMT
C65
1000
PF
-040
2SM
T
C65
1000
PF
-040
2SM
T
C30
100N
F-0
603S
MT
C30
100N
F-0
603S
MT
C38
1000
PF
-040
2SM
T
C38
1000
PF
-040
2SM
T
EC
P3-
672f
pBG
A
U1I
EC
P3-
672f
pBG
A
U1I
VC
CK
11
VC
CK
12
VC
CK
13
VC
CK
14
VC
CK
15
VC
CK
16
VC
CL1
0
VC
CL1
1
VC
CL1
2
VC
CL1
5
VC
CL1
6
VC
CL1
7
VC
CM
11
VC
CM
16
VC
CN
10
VC
CN
17
VC
CP
10
VC
CP
17
VC
CR
11
VC
CR
16
VC
CT
10
VC
CT
11
VC
CT
12
VC
CT
15
VC
CT
16
VC
CT
17
VC
CU
11
VC
CU
12
VC
CU
13
VC
CU
14
VC
CU
15
VC
CU
16
C78
100N
F-0
603S
MT
C78
100N
F-0
603S
MT
C45
100N
F-0
603S
MT
C45
100N
F-0
603S
MT
C51
10N
F-0
603S
MT
C51
10N
F-0
603S
MT
C13
1000
PF
-040
2SM
T
C13
1000
PF
-040
2SM
T
C39
1000
PF
-040
2SM
T
C39
1000
PF
-040
2SM
T
C36
1000
PF
-040
2SM
T
C36
1000
PF
-040
2SM
TC
28
100N
F-0
603S
MT
C28
100N
F-0
603S
MT
C55
10N
F-0
603S
MT
C55
10N
F-0
603S
MT
C41
10N
F-0
603S
MT
C41
10N
F-0
603S
MT
C40
1000
PF
-040
2SM
T
C40
1000
PF
-040
2SM
T
C47
10N
F-0
603S
MT
C47
10N
F-0
603S
MT
C20
10N
F-0
603S
MT
C20
10N
F-0
603S
MT
C74
100N
F-0
603S
MT
C74
100N
F-0
603S
MT
C62
1000
PF
-040
2SM
T
C62
1000
PF
-040
2SM
T
FB
1B
LM41
PG
600S
N1
FB
1B
LM41
PG
600S
N1
MH
1
M H
OLE
2
MH
1
M H
OLE
2
C43
10N
F-0
603S
MT
C43
10N
F-0
603S
MT
+C
27
22UF-16V_TANTBSMT
+C
27
22UF-16V_TANTBSMT
C42
100N
F-0
603S
MT
C42
100N
F-0
603S
MT
C59
1000
PF
-040
2SM
T
C59
1000
PF
-040
2SM
T
C50
10N
F-0
603S
MT
C50
10N
F-0
603S
MT
C19
10N
F-0
603S
MT
C19
10N
F-0
603S
MT
MH
3
M H
OLE
2
MH
3
M H
OLE
2
C48
1UF-16V-0805SMT
C48
1UF-16V-0805SMT
C61
1000
PF
-040
2SM
T
C61
1000
PF
-040
2SM
T
C85
1000
PF
-040
2SM
T
C85
1000
PF
-040
2SM
T
C15
1000
PF
-040
2SM
T
C15
1000
PF
-040
2SM
T
C72
100N
F-0
603S
MT
C72
100N
F-0
603S
MT
EC
P3-
672f
pBG
A
U1K
EC
P3-
672f
pBG
A
U1K
GN
DA
2
GN
DA
25
GN
DA
A13
GN
DA
A14
GN
DA
A18
GN
DA
A19
GN
DA
A21
GN
DA
A6
GN
DA
A8
GN
DA
A9
GN
DA
B19
GN
DA
B2
GN
DA
B25
GN
DA
B8
GN
DA
C11
GN
DA
C12
GN
DA
C13
GN
DA
C14
GN
DA
C15
GN
DA
C16
GN
DA
C19
GN
DA
C20
GN
DA
C21
GN
DA
C22
GN
DA
C5
GN
DA
C6
GN
DA
C7
GN
DA
C8
GN
DA
D22
GN
DA
D5
GN
DA
E1
GN
DA
E10
GN
DA
E11
GN
DA
E12
GN
DA
E13
GN
DA
E14
GN
DA
E15
GN
DA
E16
GN
DA
E17
GN
DA
E18
GN
DA
E19
GN
DA
E20
GN
DA
E21
GN
DA
E22
GN
DA
E26
GN
DA
E5
GN
DA
E6
GN
DA
E7
GN
DA
E8
GN
DA
E9
GN
DA
F2
GN
DA
F22
GN
DA
F25
GN
DA
F5
GN
DB
1
GN
DB
14
GN
DB
18
GN
DB
22
GN
DB
26
GN
DB
5
GN
DB
9
GN
DD
11
GN
DD
16
GN
DD
20
GN
DD
7
GN
DE
2
GN
DE
25
GN
DF
21
GN
DF
6
GN
DG
12
GN
DG
15
GN
DG
23
GN
DG
4
GN
DH
18
GN
DH
9
GN
DJ1
2
GN
DJ1
5
GN
DJ1
9
GN
DJ2
GN
DJ2
5
GN
DJ8
GN
DK
10
GN
DK
17
GN
DL1
3
GN
DL1
4
GN
DL2
3
GN
DL4
GN
DM
12
GN
DM
13
GN
DM
14
GN
DM
15
GN
DM
18
GN
DM
20
GN
DM
7
GN
DM
9
GN
DN
11
GN
DN
12
GN
DN
13
GN
DN
14
GN
DN
15
GN
DN
16
GN
DN
2
GN
DP
11
GN
DP
12
GN
DP
13
GN
DP
14
GN
DP
15
GN
DP
16
GN
DP
25
GN
DR
12
GN
DR
13
GN
DR
14
GN
DR
15
GN
DR
20
GN
DR
7
GN
DR
9
GN
DT
13
GN
DT
14
GN
DT
19
GN
DT
23
GN
DT
4
GN
DU
17
GN
DV
12
GN
DV
15
GN
DV
19
GN
DV
2
GN
DV
25
GN
DW
11
GN
DW
16
GN
DY
10
GN
DY
11
GN
DY
12
GN
DY
15
GN
DY
16
GN
DY
17
GN
DY
18
GN
DY
23
GN
DY
4
GN
DY
9
C32
100N
F-0
603S
MT
C32
100N
F-0
603S
MT
C67
1000
PF
-040
2SM
T
C67
1000
PF
-040
2SM
T
+C
44
22UF-16V_TANTBSMT
+C
44
22UF-16V_TANTBSMT
C53
10N
F-0
603S
MT
C53
10N
F-0
603S
MT
C84
1000
PF
-040
2SM
T
C84
1000
PF
-040
2SM
T
C58
1000
PF
-040
2SM
T
C58
1000
PF
-040
2SM
T
C16
1000
PF
-040
2SM
T
C16
1000
PF
-040
2SM
T
C33
100N
F-0
603S
MT
C33
100N
F-0
603S
MT
C66
1000
PF
-040
2SM
T
C66
1000
PF
-040
2SM
T
C73
10N
F-0
603S
MT
C73
10N
F-0
603S
MT
C86
1000
PF
-040
2SM
T
C86
1000
PF
-040
2SM
T
C52
10N
F-0
603S
MT
C52
10N
F-0
603S
MT
C76
10N
F-0
603S
MT
C76
10N
F-0
603S
MT
C49
10N
F-0
603S
MT
C49
10N
F-0
603S
MT
C25
10N
F-0
603S
MT
C25
10N
F-0
603S
MT
C11
1000
PF
-040
2SM
T
C11
1000
PF
-040
2SM
T
C70
10N
F-0
603S
MT
C70
10N
F-0
603S
MT
C68
1000
PF
-040
2SM
T
C68
1000
PF
-040
2SM
T
C60
1000
PF
-040
2SM
T
C60
1000
PF
-040
2SM
T
C18
1000
PF
-040
2SM
T
C18
1000
PF
-040
2SM
T
C79
10N
F-0
603S
MT
C79
10N
F-0
603S
MT
C23
10N
F-0
603S
MT
C23
10N
F-0
603S
MT
25
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 23. Programming5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
CONFIG
CFG Switches
SPI FLASH
ON
FROM ISPVM CABLE
This LED
indicates activity
on TDI.
JTAG
FPGA GSRN
PROGRAMN
DONE indicator will light when
configuration is successfully
completed
INITN indicator will light
if an error occurs during
configuration programming
edoM n
oitarugifnoC
2GFC
CFG1
CFG0
ispJTAG
Slave Serial
SPIm
SPI Flash
Slave Parallel
0(ON)
XX1(OFF)
1(OFF)
1(OFF)
1(OFF)
1(OFF)
0(ON)
0(ON)
1(OFF)
0(ON)
0(ON)
0(ON)
X
TMS
TCK
+3.3V
TDI
GND
TDO
CONFIG
Status LEDs
PROGRAMN
& GSRN
Pushbuttons
Primary
Component
Side
Secondary
Component
Side
SW1 and SW3 on Primary Side
SW6 and SW7 on Secondary Side
PROGRAMN
CF
G2
CF
G1
CF
G0
TC
K_B
UF
FP
GA
_D1
FP
GA
_D0
FP
GA
_D3
FP
GA
_D4
FP
GA
_D5
FP
GA
_D6
FP
GA
_D2
TM
S_B
UF
FLA
SH
_DIS
PR
OG
RA
MN
FP
GA
_XR
ES
FP
GA
_CS
SP
I0N
_DI
SP
I0_Q
DO
NE
LOA
DE
R_C
K
PR
OG
RA
MN
FP
GA
_CS
SP
I1N
_DO
UT
GS
RN
FP
GA
_CS
SP
I0N
_DI
CF
G2
CF
G1
CF
G0
INIT
N
FP
GA
_SIS
PI
INIT
N
DO
NE
GSRN
TD
I_B
UF
FP
GA
_CC
LK
SP
I_C
LK
FP
GA
_D7
FP
GA
_SIS
PI
FP
GA
_WR
ITE
N
DONE
FP
GA
_D0
SP
IFA
ST
N
FP
GA
_XR
ES
FP
GA
_CC
LK
INITN
PROGRAMN
SP
I_C
LK
FP
GA
_MC
LK
TC
K_B
UF
TM
S_B
UF
TD
I_B
UF
TD
I_X
O
FP
GA
_MC
LKF
PG
A_C
CLK
FP
GA
_CS
N
SP
I0_Q
FP
GA
_D7
FP
GA
_CS
1NG
SR
N
LOC
AL_
TD
ILO
CA
L_T
MS
LOC
AL_
TC
K
FPGA_CS1N
FPGA_CSN
FPGA_WRITEN
FP
GA
_D13
FP
GA
_D12
FP
GA
_D11
FP
GA
_D10
FP
GA
_D9
FP
GA
_D8
FP
GA
_D15
FP
GA
_D14
FPGA_D[8..15]
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
TM
S_B
UF
[5]
PR
OG
RA
MN
[5]
DO
NE
[5]
INIT
N[5
]
LOA
DE
R_C
K[5
]
CF
G[0
..2]
[5]
TD
I_X
O[5
]
FP
GA
_CC
LK[5
]
]5[N
RS
G
SP
I_C
LK[5
]
TC
K_B
UF
[5]
TD
O_X
O[5
]
FP
GA
_WR
ITE
N[5
]
FP
GA
_CS
1N[5
]F
PG
A_C
SN
[5]
FP
GA
_D[0
..7]
[5]
FP
GA
_D[8
..15]
[5]
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
Pro
gam
min
g
C
49
Thu
rsda
y, A
ugus
t 09,
201
2
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
Pro
gam
min
g
C
49
Thu
rsda
y, A
ugus
t 09,
201
2
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
Pro
gam
min
g
C
49
Thu
rsda
y, A
ugus
t 09,
201
2
U8
NC
7WZ
16-M
AA
O6A
/Fai
rchi
ld T
inyL
ogic
IN A
11
GND2
IN A
23
OU
T Y
24
VCC5
OU
T Y
16
R46
10K
-060
3SM
T
U10
NC
7WZ
16-M
AC
O6A
/Fai
rchi
ld T
inyL
ogic
IN A
11
GND2
IN A
23
OU
T Y
24
VCC5
OU
T Y
16
G
D9
LED-SMT1206_GREEN
R27
10K
-060
3SM
T
R48
10K
-060
3SM
T
RN1C
4.7K
3 6
C90100NF-0603SMT
C87
100NF-0603SMT
C92
100NF-0603SMT
R D10
LED
-SM
T12
06_G
RE
EN
J4
HE
AD
ER
612 3 4
56
R3910K-0603SMT
SW
3
SW
PU
SH
BU
TT
ON
-SP
ST
R3610K-0603SMT
R31
10K
-060
3SM
T
SW
6
SW
PU
SH
BU
TT
ON
-SP
ST
R42 OPEN-0603SMT
R50
100R-0603SMT
RN1B
4.7K
2 7
J3
HE
AD
ER
21 2
R44
4_7K-0603SMT
RN1D
EX
BV
8V47
2JV
4.7K
4 5
R24
680R
-060
3SM
T
U6
M25
P64
-FLA
SH
S#
7
Q8
DU
13
DU
24
VC
C2
HO
LD#
1
DU
46
DU
35
W#
9V
SS
10D
U5
11D
U6
12D
U7
13D
U8
14D
15C
K16
J8
HE
AD
ER
612 3 4
56
R3810K-0603SMT
R49
10K
-060
3SM
T
Y
D7
LED
-SM
T12
06_R
ED
R51100R-0603SMT
R
D6
LED
-SM
T12
06_R
ED
RN1A
4.7K
1 8
EC
P3-
672f
pBG
AU1G
PR
16B
/BU
SY
/SIS
PI/A
VD
NK
21
PR
14B
/D6/
SP
ID1
C26
PR
16A
/D7/
SP
ID0
K20
PR
14A
/D5
B25
PR
13B
/D4/
SO
J22
PR
13A
/D3/
SI
J21
PR
11B
/D2
D26
PR
11A
/D1
D25
PR
10B
/D0/
SP
IFA
ST
ND
23
PR
8B/M
CLK
C25
PR
10A
/WR
ITE
N/O
EN
E24
PR
8A/D
OU
T/C
SO
N/C
SS
PI1
ND
24
PR
7B/C
SN
/SN
/CO
NT
1NH
22P
R5B
/DI/C
SS
PI0
N/C
EN
C24
PR
7A/C
S1N
/HO
LD/C
ON
T2N
G22
PR
5AC
23
DO
NE
B24
CC
LKA
24
INIT
NH
21
PR
OG
RA
MN
J20
CF
G0
B23
CF
G1
A23
CF
G2
E21
PT
145B
F22
PT
145A
F23
PT
143B
E22
PT
143A
E23
PT
142B
G21
PT
142A
G20
PT
140B
D21
PT
140A
D22
TM
SE
6
TD
OE
7
TC
KE
5
TD
IF
5
XR
ES
R18
TE
MP
SE
NS
EU
10
TE
MP
VS
SV
8
VC
CIO
8H
19
VC
CIO
8H
20
VC
CJ
H7
C91
100N
F-0
603S
MT
SW
7
SW
PU
SH
BU
TT
ON
-SP
ST
R43
4_7K
-060
3SM
T
R33
10K
-060
3SM
T
R30
10K
-060
3SM
T
R47
220R
-060
3SM
T
SW
1
SW
PU
SH
BU
TT
ON
-SP
ST
R25
680R
-060
3SM
T
R23
680R
-060
3SM
T
R29
10K
-060
3SM
T
R41 OPEN-0603SMT
C88
10NF-0603SMT
R34
10K
-060
3SM
T
C89
100NF-0603SMT
SW
2IN
S38
2592
85S
W D
IP-3
CT
S 1
94-3
MS
T
123
654
J2H
EA
DE
R 2
X2
3 41 2
R404_7K-0603SMT
R26
220R-0603SMT
R3710K-0603SMT
R32
10K
-060
3SM
T
R28
10K
-060
3SM
T
U7
MA
X68
17
IN1
1
GND2
IN2
3
OU
T2
4
VCC5
OU
T1
6
U9B
SN
74LV
C12
5A/S
O14
3Y8
3A9
3OE
_N10
4Y11
4A12
4OE
_N13
VCC14
U9A
SN
74LV
C12
5A/S
O14
1OE
_N1
1A2
1Y3
2OE
_N4
2A5
2Y6
GND7
Y
D8
LED
-SM
T12
06_R
ED
R45
10K
-060
3SM
T
R35
10K
-060
3SM
T
Q4
2N22
22/S
OT
23
3
1
2
26
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 24. Parallel FPGA Loader5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
FLA
SH
_A21
FLA
SH
_A20
FLA
SH
_A19
FLA
SH
_A18
FLA
SH
_A17
FLA
SH
_A16
FLA
SH
_A15
FLA
SH
_A14
FLA
SH
_A13
FLA
SH
_A12
FLA
SH
_A11
FLA
SH
_A10
FLA
SH
_A9
FLA
SH
_A8
FLA
SH
_A7
FLA
SH
_A6
FLA
SH
_A5
FLA
SH
_A4
FLA
SH
_A3
FLA
SH
_A2
FLA
SH
_A1
FLA
SH
_A0
FLA
SH
_A[0
..21]
FLA
SH
_D0
FLA
SH
_D1
FLA
SH
_D2
FLA
SH
_D3
FLA
SH
_D4
FLA
SH
_D5
FLA
SH
_D6
FLA
SH
_D7
FLA
SH
_D8
FLA
SH
_D9
FLA
SH
_D10
FLA
SH
_D11
FLA
SH
_D12
FLA
SH
_D13
FLA
SH
_D14
FLA
SH
_D15
FLA
SH
_D[0
..15]
FLA
SH
_D[0
..15]
FLA
SH
_WE
_N
FLA
SH
_WP
_N_A
CC
FLA
SH
_RE
SE
T_N
FLA
SH
_OE
_NF
LAS
H_C
Em
FLA
SH
_RD
/BY
FLA
SH
_BY
TE
n
TM
S_B
UF
TD
I_X
O
PR
OG
RA
MN
GS
RN
DO
NE
TC
K_B
UF
INIT
N
FP
GA
_0
FPGA_D[0..7]
FP
GA
_1F
PG
A_2
FP
GA
_3F
PG
A_4
FP
GA
_5
FP
GA
_D2
FP
GA
_6F
PG
A_7
FP
GA
_8
FP
GA
_D3
FP
GA
_D4
FP
GA
_D5
FP
GA
_D6
FP
GA
_D7
FP
GA
_D0
FP
GA
_D1
FP
GA
_9F
PG
A_1
0F
PG
A_1
1F
PG
A_1
2F
PG
A_1
3F
PG
A_1
4F
PG
A_1
5
LOA
DE
R_C
K
CF
G1
CF
G2
CF
G0
FLA
SH
_A21
FLA
SH
_A9
FLA
SH
_A8
FLA
SH
_A7
FLA
SH
_A6
FLA
SH
_A5
FLA
SH
_A4
FLA
SH
_A3
FLA
SH
_A2
FLA
SH
_A1
FLA
SH
_A0
FLA
SH
_A20
FLA
SH
_A19
FLA
SH
_A18
FLA
SH
_A17
FLA
SH
_A16
FLA
SH
_A15
FLA
SH
_A14
FLA
SH
_A13
FLA
SH
_A12
FLA
SH
_A11
FLA
SH
_A10
FLA
SH
_CLK
FLA
SH
_WE
_NF
LAS
H_W
P_N
_AC
CF
LAS
H_R
ES
ET
_NF
LAS
H_O
E_N
FLA
SH
_CE
mF
LAS
H_R
D/B
YF
LAS
H_B
YT
En
FLA
SH
_D0
FLA
SH
_D1
FLA
SH
_D2
FLA
SH
_D3
FLA
SH
_D4
FLA
SH
_D5
FLA
SH
_D6
FLA
SH
_D7
FLA
SH
_D8
FLA
SH
_D9
FLA
SH
_D10
FLA
SH
_D11
FLA
SH
_D12
FLA
SH
_D13
FLA
SH
_D14
FLA
SH
_D15
FPGA_D[8..15]
FP
GA
_D13
FP
GA
_D12
FP
GA
_D11
FP
GA
_D10
FP
GA
_D9
FP
GA
_D8
FP
GA
_D15
FP
GA
_D14
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
TD
O_X
O[4
]T
MS
_BU
F[4
]
TD
I_X
O[4
]
FP
GA
_[0:
15]
[8]
PR
OG
RA
MN
[4]
GS
RN
[4]
DO
NE
[4]
TC
K_B
UF
[4]
INIT
N[4
]
FP
GA
_D[0
..7]
[4]
LOA
DE
R_C
K[4
]
CF
G[0
..2]
[4]
SP
I_C
LK[4
]F
PG
A_C
CLK
[4]
FP
GA
_WR
ITE
N[4
]F
PG
A_C
S1N
[4]
FP
GA
_CS
N[4
]
FLA
SH
_CLK
[9]
FP
GA
_D[8
..15]
[4]
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
Par
alle
l FP
GA
Loa
der
C
59
Mon
day,
Feb
ruar
y 23
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
Par
alle
l FP
GA
Loa
der
C
59
Mon
day,
Feb
ruar
y 23
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
Par
alle
l FP
GA
Loa
der
C
59
Mon
day,
Feb
ruar
y 23
, 200
9
CPLD RESET
R55
2_2K
-060
3SM
TR
552_
2K-0
603S
MT
C98
10N
F-0
603S
MT
C98
10N
F-0
603S
MT
R57
1K-0
603S
MT
R57
1K-0
603S
MT
Lattice
FPGA
Loader
LCM
XO
1200
C-C
SB
GA
132
U12
Lattice
FPGA
Loader
LCM
XO
1200
C-C
SB
GA
132
U12
FP
GA
_IN
ITN
A1
CF
G1
A2
CF
G0
A3
FP
GA
_DO
NE
A4
FP
GA
_DA
TA
_1A
5
FLA
SH
_AD
DR
ES
S_1
A6
CLO
CK
A8
FLA
SH
_AD
DR
ES
S_4
A9
FLA
SH
_AD
DR
ES
S_9
A11
FLA
SH
_AD
DR
ES
S_1
9A
12
FLA
SH
_AD
DR
ES
S_1
7A
13
FLA
SH
_AD
DR
ES
S_1
2A
14
SP
I_C
LKB
1
FLA
SH
_CE
mB
2
FLA
SH
_AD
DR
ES
S_2
B3
FLA
SH
_AD
DR
ES
S_3
B5
FLA
SH
_AD
DR
ES
S_0
B6
FP
GA
_DA
TA
_7B
7
FLA
SH
_AD
DR
ES
S_1
3B
8
FLA
SH
_AD
DR
ES
S_5
B9
FLA
SH
_AD
DR
ES
S_7
B10
FLA
SH
_AD
DR
ES
S_1
5B
12
FLA
SH
_AD
DR
ES
S_1
8B
13
FLA
SH
_AD
DR
ES
S_2
1B
14
FLA
SH
_OE
_NC
1
FLA
SH
_CE
0_N
C3
FLA
SH
_DQ
_6C
4
FLA
SH
_AD
DR
ES
S_1
1C
8
FLA
SH
_AD
DR
ES
S_6
C10
FLA
SH
_AD
DR
ES
S_8
C11
FLA
SH
_AD
DR
ES
S_2
0C
12
FLA
SH
_AD
DR
ES
S_1
6C
13
FLA
SH
_AD
DR
ES
S_1
4C
14
FLA
SH
_RD
/BY
D1
FLA
SH
_DQ
_7D
3
FLA
SH
_DQ
_14
D12
FLA
SH
_AD
DR
ES
S_1
0D
14F
PG
A_D
AT
A_6
E3
FLA
SH
_DQ
_8E
13
FLA
SH
_DQ
_15
E14
FLA
SH
_BY
TE
nF
2
FLA
SH
_CE
1_N
F3
FP
GA
_CS
NF
12
FLA
SH
_DQ
_9F
13F
LAS
H_D
Q_1
0F
14
FP
GA
_DA
TA
_0G
1
FLA
SH
_DQ
_0G
3F
LAS
H_D
Q_1
G13
FLA
SH
_DQ
_12
G14
FLA
SH
_DQ
_4H
1
FP
GA
_PR
OG
RA
MN
H2
GP
IO16
H12
GP
IO17
H13
FP
GA
_CS
1NH
14
FLA
SH
_DQ
_5J1
TS
ALL
J2
FP
GA
_DA
TA
_4J3
FLA
SH
_DQ
_13
J12
FLA
SH
_DQ
_11
J13
FP
GA
_DA
TA
_5K
1
FLA
SH
_WE
_NK
2
FU
NC
_RE
SE
TK
12
FLA
SH
_DQ
_2K
13
FLA
SH
_WP
_N_A
CC
L1F
PG
A_C
LKL3
GP
IO0
M1
GP
IO12
M2
GP
IO13
M3
GP
IO14
M4
GP
IO15
M6
NC
M7
FP
GA
_DA
TA
_3M
8
CF
G2
M9
GP
IO11
M12
GP
IO18
M13
GP
IO20
M14
GP
IO7
N1
GP
IO8
N3
GP
IO9
N4
GP
IO19
N6
GP
IO3
N7
GP
IO4
N8
FLA
SH
_DQ
_3N
9
FP
GA
_WR
ITE
NN
10
GP
IO6
N13
FP
GA
_RE
SE
TN
N14
GP
IO10
P1
FP
GA
_CC
LKP
5
FP
GA
_DA
TA
_2P
8
GP
IO2
P10
GP
IO5
P11
GP
IO1
P13
FLA
SH
_RE
SE
T_N
P14
TC
KP
4
TD
IM
5
TD
ON
5
TM
SP
3
GND E1
VCCH3
GND L2
GND P2
VCCP6
VCCAUXP7
GND N11
GND L13
VCCG12
GND D13
GND A10
VCCAUXA7
VCCC7
GND B4
GND F1
GND P9
GND J14
GND C9
VCCIO0C5
VCCIO1B11
VCCIO2E12
VCCIO3L12
VCCIO4M10
VCCIO5N2
VCCIO7D2
VCCIO6K3
SLE
EP
NN
12
FP
GA
_D15
C6
FP
GA
_D14
C2
FP
GA
_D13
K14
FP
GA
_D12
P12
FP
GA
_D11
L14
FP
GA
_D10
M11
FP
GA
_D9
G2
FP
GA
_D8
E2
C96
10N
F-0
603S
MT
C96
10N
F-0
603S
MT
R54
10K
-060
3SM
TR
5410
K-0
603S
MT
C97
100N
F-0
603S
MT
C97
100N
F-0
603S
MT
SW
4
B3F
-115
0M
omen
tary
Sw
itch
SW
4
B3F
-115
0M
omen
tary
Sw
itch
13
24
C94
10N
F-0
603S
MT
C94
10N
F-0
603S
MT
R561K-0603SMT
R561K-0603SMT
U11
S29
GL0
64A
U11
S29
GL0
64A
A21
C4
A20
D3
A19
D4
A18
C3
A17
B2
A16
E6
A15
D6
A14
C6
A13
A6
A12
B6
A11
D5
A10
C5
A9
A5
A8
B5
A7
A2
A6
C2
A5
D2
A4
B1
A3
A1
A2
C1
A1
D1
A0
E1
GN
DH
6
GN
DH
1R
ES
ET
nB
4W
Pn
B3
BY
TE
nF
6R
D/B
YA
3W
En
A4
OE
nG
1C
En
F1
DQ
0E
2D
Q1
H2
DQ
2E
3D
Q3
H3
DQ
4H
4D
Q5
E4
DQ
6H
5D
Q7
E5
DQ
8F
2D
Q9
G2
DQ
10F
3D
Q11
G3
DQ
12F
4D
Q13
G5
DQ
14F
5D
Q15
G6
VC
CG
4
C95
100N
F-0
603S
MT
C95
100N
F-0
603S
MT
C10
0
10N
F-0
603S
MT
C10
0
10N
F-0
603S
MT
C93
100N
F-0
603S
MT
C93
100N
F-0
603S
MT
R53
0R-0
603S
MT
R53
0R-0
603S
MT
R52
OP
EN
-060
3SM
TR
52O
PE
N-0
603S
MT
C99
100N
F-0
603S
MT
C99
100N
F-0
603S
MT
C101100NF-0603SMT
C101100NF-0603SMT
27
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 25. SERDES5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
PC
SA
_HD
OU
TP
0
PC
SA
_HD
OU
TN
0
x1_P
ER
p0
x1_P
ER
n0
PC
IE_3
V3
x1_P
ER
p0x1
_PE
Rn0
PC
IE_P
ER
ST
N
x1_P
ET
p0x1
_PE
Tn0
PC
IE_3
V3
x1_P
CIE
_CLK
Nx1
_PC
IE_C
LKP
x4_P
ER
p0x4
_PE
Rn0
x4_P
ER
p1x4
_PE
Rn1
x4_P
ET
p3
x4_P
ER
p2x4
_PE
Rn2
x4_P
ER
p3x4
_PE
Rn3
PC
IE_P
ER
ST
N
PC
IE_3
V3
x4_P
ET
p0x4
_PE
Tn0
x4_P
ET
p1x4
_PE
Tn1
x4_P
ET
p2x4
_PE
Tn2
x4_P
ET
n3
PC
IE_3
V3
x4_P
CIE
_CLK
Nx4
_PC
IE_C
LKP
x4_P
ER
p3
x4_P
ER
n3
x4_P
ER
p2
x4_P
ER
n2
x4_P
ER
p1
x4_P
ER
n1
x4_P
ER
p0
x4_P
ER
n0
x4_P
CIE
_CLK
Px4
_PC
IE_C
LKN
x1_P
CIE
_CLK
Px1
_PC
IE_C
LKN
LOO
P3_
N
LOO
P3_
PLO
OP
3_N
x1_P
CIE
_CLK
Nx1
_PC
IE_C
LKP
LOO
P2_
PLO
OP
2_N
LOO
P1_
PLO
OP
1_N
x1_P
ET
p0x1
_PE
Tn0
LOO
P2_
PLO
OP
2_N
LOO
P1_
PLO
OP
1_N
PC
SA
_HD
OU
TP
0P
CS
A_H
DO
UT
N0
LOO
P3_
P
x4_P
CIE
_CLK
Px4
_PC
IE_C
LKN
x4_P
ET
n0x4
_PE
Tp0
x4_P
ET
p3
x4_P
ET
p1
x4_P
ET
n3
x4_P
ET
n1x4
_PE
Tp2
x4_P
ET
n2
PC
SB
_HD
OU
TP
0P
CS
B_H
DO
UT
N0
PC
SB
_HD
OU
TN
1P
CS
B_H
DO
UT
P1
PC
SB
_HD
OU
TN
2P
CS
B_H
DO
UT
P2
PC
SB
_HD
OU
TP
3P
CS
B_H
DO
UT
N3
PC
SB
_HD
OU
TP
1
PC
SB
_HD
OU
TN
1
PC
SB
_HD
OU
TP
2
PC
SB
_HD
OU
TP
3
PC
SB
_HD
OU
TN
3
PC
SB
_HD
OU
TP
0
PC
SB
_HD
OU
TN
0
PC
SB
_HD
OU
TN
2
12_0
V
12_0
V
PC
SA
_VC
CIB
1_2V
_A
1_2V
_A
PC
SA
_VC
CO
B
1_2V
_A
PC
SB
_VC
CIB
PC
SB
_VC
CO
B
1_2V
_A
PC
SA
_VC
CIB
PC
SA
_VC
CO
B
PC
SB
_VC
CIB
PC
SB
_VC
CO
B
PC
SA
_VC
CO
B
PC
SB
_VC
CO
BP
CS
B_V
CC
IB
PC
SA
_VC
CIB
PC
IE_P
ER
ST
N[8
]
x1_P
RS
NT
n[8
]
x4_P
RS
NT
n[8
]
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
SE
RD
ES
C
69
Mon
day,
Feb
ruar
y 23
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
SE
RD
ES
C
69
Mon
day,
Feb
ruar
y 23
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
SE
RD
ES
C
69
Mon
day,
Feb
ruar
y 23
, 200
9
X1 PCIe Board Fingers
B side = Primary Component Side(TOP)
A side = Secondary Component Side(BOTTOM)
Place near U1
X4 PCIe Board Fingers
B side = Secondary Component Side(BOTTOM)
A side = PRIMARY Component Side(TOP)
All Nets are 85-ohm differential pairs.
The P and N traces shall be <20mil matched in length
All Nets are 85-ohm differential pairs.
The P and N traces shall be <20mil matched in length
C12
2
100N
F-0
603S
MT
C12
2
100N
F-0
603S
MT
C11
6
100N
F-0
603S
MT
C11
6
100N
F-0
603S
MT
C11
1
10N
F-0
603S
MT
C11
1
10N
F-0
603S
MT
C11
4
100N
F-0
603S
MT
C11
4
100N
F-0
603S
MT
C12
3
10N
F-0
603S
MT
C12
3
10N
F-0
603S
MT
C10
7
1UF-16V-0805SMT
C10
7
1UF-16V-0805SMT
C12
610
0NF
X5R
-040
2SM
TC
126
100N
FX
5R-0
402S
MT
C10
9
1UF-16V-0805SMT
C10
9
1UF-16V-0805SMT
CN
1
PC
I Exp
ress
x4
Edg
e F
inge
r C
onn.
CN
1
PC
I Exp
ress
x4
Edg
e F
inge
r C
onn.
PR
SN
T1#
A1
+12
VA
2
+12
VA
3
GN
DA
4
JTA
G2
A5
JTA
G3
A6
JTA
G4
A7
JTA
G5
A8
+3.
3VA
9
+3.
3VA
10
PE
RS
T#
A11
GN
DA
12
RE
FC
LK+
A13
RE
FC
LK-
A14
GN
DA
15
PE
Rp0
A16
PE
Rn0
A17
GN
DA
18
RS
VD
_A19
A19
GN
DA
20
PE
Rp1
A21
PE
Rn1
A22
GN
DA
23
GN
DA
24
PE
Rp2
A25
PE
Rn2
A26
GN
DA
27
GN
DA
28
PE
Rp3
A29
PE
Rn3
A30
GN
DA
31
+12
VB
1
+12
VB
2
RS
VD
_B3
B3
GN
DB
4
SM
CLK
B5
SM
DA
TB
6
GN
DB
7
+3.
3VB
8
JTA
G1
B9
3.3V
aux
B10
WA
KE
#B
11
RS
VD
_B12
B12
GN
DB
13
PE
Tp0
B14
PE
Tn0
B15
GN
DB
16
PR
SN
T3#
B17
GN
DB
18
PE
Tp1
B19
PE
Tn1
B20
GN
DB
21
GN
DB
22
PE
Tp2
B23
PE
Tn2
B24
GN
DB
25
GN
DB
26
PE
Tp3
B27
PE
Tn3
B28
GN
DB
29
RS
VD
_B30
B30
PR
SN
T4#
B31
GN
DB
32R
SV
D_A
32A
32R
59O
PE
N-0
603S
MT
R59
OP
EN
-060
3SM
T
+C
106
22UF-16V_TANTBSMT
+C
106
22UF-16V_TANTBSMT
C13
510
0NF
X5R
-040
2SM
TC
135
100N
FX
5R-0
402S
MT
+C
108
22UF-16V_TANTBSMT
+C
108
22UF-16V_TANTBSMT
C11
5
10N
F-0
603S
MT
C11
5
10N
F-0
603S
MT
C12
5
10N
F-0
603S
MT
C12
5
10N
F-0
603S
MT
C13
410
0NF
X5R
-040
2SM
TC
134
100N
FX
5R-0
402S
MT
C11
7
10N
F-0
603S
MT
C11
7
10N
F-0
603S
MT
C13
310
0NF
X5R
-040
2SM
TC
133
100N
FX
5R-0
402S
MT
EC
P3-
672f
pBG
A
U1H
EC
P3-
672f
pBG
A
U1H
PC
SA
_HD
INP
0A
D21
PC
SA
_HD
INN
0A
D20
PC
SA
_HD
INP
1A
D18
PC
SA
_HD
INN
1A
D19
PC
SA
_HD
INP
2A
D17
PC
SA
_HD
INN
2A
D16
PC
SA
_HD
INP
3A
D14
PC
SA
_HD
INN
3A
D15
PC
SA
_HD
OU
TP
0A
F21
PC
SA
_HD
OU
TN
0A
F20
PC
SA
_HD
OU
TP
1A
F18
PC
SA
_HD
OU
TN
1A
F19
PC
SA
_HD
OU
TP
2A
F17
PC
SA
_HD
OU
TN
2A
F16
PC
SA
_HD
OU
TP
3A
F14
PC
SA
_HD
OU
TN
3A
F15
PC
SA
_RE
FC
LKP
AC
17
PC
SA
_RE
FC
LKN
AC
18
PC
SA
_VC
CIB
0A
B18
PC
SA
_VC
CIB
1A
A16
PC
SA
_VC
CIB
2A
A15
PC
SA
_VC
CIB
3A
B14
PC
SA
_VC
CO
B0
AA
17
PC
SA
_VC
CO
B1
AB
17
PC
SA
_VC
CO
B2
AB
16
PC
SA
_VC
CO
B3
AB
15
PC
SB
_HD
INP
0A
D13
PC
SB
_HD
INN
0A
D12
PC
SB
_HD
INP
1A
D10
PC
SB
_HD
INN
1A
D11
PC
SB
_HD
INP
2A
D9
PC
SB
_HD
INN
2A
D8
PC
SB
_HD
INP
3A
D6
PC
SB
_HD
INN
3A
D7
PC
SB
_HD
OU
TP
0A
F13
PC
SB
_HD
OU
TN
0A
F12
PC
SB
_HD
OU
TP
1A
F10
PC
SB
_HD
OU
TN
1A
F11
PC
SB
_HD
OU
TP
2A
F9
PC
SB
_HD
OU
TN
2A
F8
PC
SB
_HD
OU
TP
3A
F6
PC
SB
_HD
OU
TN
3A
F7
PC
SB
_RE
FC
LKP
AC
9
PC
SB
_RE
FC
LKN
AC
10
PC
SB
_VC
CIB
0A
B13
PC
SB
_VC
CIB
1A
B11
PC
SB
_VC
CIB
2A
A11
PC
SB
_VC
CIB
3A
B9
PC
SB
_VC
CO
B0
AB
12
PC
SB
_VC
CO
B1
AA
12
PC
SB
_VC
CO
B2
AB
10
PC
SB
_VC
CO
B3
AA
10
FB
3B
LM41
PG
600S
N1
FB
3B
LM41
PG
600S
N1
C11
3
10N
F-0
603S
MT
C11
3
10N
F-0
603S
MT
C13
210
0NF
X5R
-040
2SM
TC
132
100N
FX
5R-0
402S
MT
FB
4B
LM41
PG
600S
N1
FB
4B
LM41
PG
600S
N1
C12
710
0NF
X5R
-040
2SM
TC
127
100N
FX
5R-0
402S
MT
C13
110
0NF
X5R
-040
2SM
TC
131
100N
FX
5R-0
402S
MT
C12
0
100N
F-0
603S
MT
C12
0
100N
F-0
603S
MT
FB
2B
LM41
PG
600S
N1
FB
2B
LM41
PG
600S
N1
C13
010
0NF
X5R
-040
2SM
TC
130
100N
FX
5R-0
402S
MT
C12
1
10N
F-0
603S
MT
C12
1
10N
F-0
603S
MT
FB
5B
LM41
PG
600S
N1
FB
5B
LM41
PG
600S
N1
C11
2
100N
F-0
603S
MT
C11
2
100N
F-0
603S
MT
CN
2
PC
I Exp
ress
x1
Edg
e F
inge
r C
onn.
CN
2
PC
I Exp
ress
x1
Edg
e F
inge
r C
onn.
PR
SN
T1#
A1
+12
VA
2
+12
VA
3
GN
DA
4
JTA
G2
A5
JTA
G3
A6
JTA
G4
A7
JTA
G5
A8
+3.
3VA
9
+3.
3VA
10
PE
RS
T#
A11
GN
DA
12
RE
FC
LK+
A13
RE
FC
LK-
A14
GN
DA
15
PE
Rp0
A16
PE
Rn0
A17
GN
DA
18
+12
VB
1
+12
VB
2
RS
VD
_B3
B3
GN
DB
4
SM
CLK
B5
SM
DA
TB
6
GN
DB
7
+3.
3VB
8
JTA
G1
B9
3.3V
aux
B10
WA
KE
#B
11
RS
VD
_B12
B12
GN
DB
13
PE
Tp0
B14
PE
Tn0
B15
GN
DB
16
PR
SN
T3#
B17
GN
DB
18
C10
3
1UF-16V-0805SMT
C10
3
1UF-16V-0805SMT
TP
14T
ES
TP
OIN
TT
P14
TE
ST
PO
INT
1
C11
8
100N
F-0
603S
MT
C11
8
100N
F-0
603S
MT
C12
910
0NF
X5R
-040
2SM
TC
129
100N
FX
5R-0
402S
MT
C12
4
100N
F-0
603S
MT
C12
4
100N
F-0
603S
MT
C12
810
0NF
X5R
-040
2SM
TC
128
100N
FX
5R-0
402S
MT
TP
13T
ES
TP
OIN
TT
P13
TE
ST
PO
INT
1
+C
102
22UF-16V_TANTBSMT
+C
102
22UF-16V_TANTBSMT
R58
OP
EN
-060
3SM
TR
58O
PE
N-0
603S
MT
+C
104
22UF-16V_TANTBSMT
+C
104
22UF-16V_TANTBSMT
C11
0
100N
F-0
603S
MT
C11
0
100N
F-0
603S
MT
C11
9
10N
F-0
603S
MT
C11
9
10N
F-0
603S
MT
C10
5
1UF-16V-0805SMT
C10
5
1UF-16V-0805SMT
28
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 26. DDR2 Memory5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DD
R2_
CS
0#
DD
R2_
CE
0#D
DR
2_O
DT
0
DD
R2_
DQ
S0
DD
R2_
15
DD
R2_
DQ
1D
DR
2_30
DD
R2_
DQ
4D
DR
2_33
DD
R2_
DQ
6D
DR
2_35
DD
R2_
DQ
2D
DR
2_31
DD
R2_
DQ
0D
DR
2_29
DD
R2_
DQ
5D
DR
2_34
DD
R2_
DQ
7D
DR
2_36
DD
R2_
DQ
3D
DR
2_32
DD
R2_
DQ
8D
DR
2_37
DD
R2_
DQ
9D
DR
2_38
DD
R2_
DQ
14D
DR
2_43
DD
R2_
DQ
13D
DR
2_42
DD
R2_
DQ
11D
DR
2_40
DD
R2_
DQ
10D
DR
2_39
DD
R2_
DQ
15D
DR
2_44
DD
R2_
DQ
12D
DR
2_41
DD
R2_
DQ
S1
DD
R2_
13D
DR
2_D
QS
0#D
DR
2_14
DD
R2_
A5
DD
R2_
23
DD
R2_
A3
DD
R2_
25
DD
R2_
A0
DD
R2_
28
DD
R2_
A8
DD
R2_
20
DD
R2_
A4
DD
R2_
24
DD
R2_
A1
DD
R2_
27
DD
R2_
A7
DD
R2_
21D
DR
2_A
6D
DR
2_22
DD
R2_
BA
1D
DR
2_B
A0
DD
R2_
RA
S#
DD
R2_
A2
DD
R2_
26
DD
R2_
A9
DD
R2_
19D
DR
2_A
10D
DR
2_18
DD
R2_
WE
#
DD
R2_
CA
S#
DD
R2_
A12
DD
R2_
16D
DR
2_A
11D
DR
2_17
DD
R2_
VR
EF
DD
R2_
A5
DD
R2_
A3
DD
R2_
A0
DD
R2_
A8
DD
R2_
A4
DD
R2_
A1
DD
R2_
A7
DD
R2_
A6
DD
R2_
A2
DD
R2_
A9
DD
R2_
A12
DD
R2_
A11
DD
R2_
A10
DDR2_A[0:12]
DD
R2_
DM
0D
DR
2_11
DD
R2_
DM
1D
DR
2_10
DD
R2_
DQ
S1#
DD
R2_
12
DD
R2_
OD
T0
DD
R2_
3
DD
R2_
RA
S#
DD
R2_
5D
DR
2_W
E#
DD
R2_
6
DD
R2_
CS
0#D
DR
2_2
DD
R2_
CE
0#D
DR
2_7
DD
R2_
BA
0D
DR
2_1
DD
R2_
BA
1D
DR
2_0
DD
R2_
K#
DD
R2_
8D
DR
2_K
DD
R2_
9
DD
R2_
CA
S#
DD
R2_
4
DDR2_K
DDR2_K#
DD
R2_
VD
DQ
DD
R2_
VD
D
1_8V V
DD
L
DD
R2_
VD
D
DD
R2_
VD
DQ
DD
R2_
VD
DQ
1_8V
3_3V
3_3V
DD
R2_
VT
T
DD
R2_
VT
T
DD
R2_
VT
T
1_8V
1_8V
DD
R2_
[0:4
4][8
]
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
DD
R2
Mem
ory
C
79
Thu
rsda
y, M
arch
26,
200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
DD
R2
Mem
ory
C
79
Thu
rsda
y, M
arch
26,
200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
DD
R2
Mem
ory
C
79
Thu
rsda
y, M
arch
26,
200
9
VTT
X1
needs to be matched length
for all traces
U1 Pin
MEMORY DEVICE
Pin
X1
X2
Termination
at end of line
ALL Memory controller
buses, clocks, and control
traces must be 50 Ohm
Transmission lines
PLACE CLOSE TO U14
C169
10NF-0603SMT
C169
10NF-0603SMT
SP
2S
P2 1
C137
1UF-16V-0805SMT
C137
1UF-16V-0805SMT
R1
R1
R1=50 Ohm
RP
1C
TS
-R24
02B
7
R1
R1
R1=50 Ohm
RP
1C
TS
-R24
02B
7
A2A2
B2B2
C2C2
D2D2
E2E2
F2F2
G2G2
H2H2
J2J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3J3
A1
A1
B1
B1
C1
C1
D1
D1
E1
E1
F1
F1
G1
G1
H1
H1
J1J1
C177
100NF-0603SMT
C177
100NF-0603SMT
FB
7B
LM41
PG
600S
N1
FB
7B
LM41
PG
600S
N1
C172
10NF-0603SMT
C172
10NF-0603SMT
R62
1K_A
DJ/
SM
T3M
M
R62
1K_A
DJ/
SM
T3M
M
C16
7
1UF-16V-0805SMT
C16
7
1UF-16V-0805SMT
+C
152
22UF-16V-TANTBSMT
+C
152
22UF-16V-TANTBSMT
C15510NF-0603SMT
C15510NF-0603SMT
SP
1S
P1 1
C149
10NF-0603SMT
C149
10NF-0603SMT
C150
10NF-0603SMT
C150
10NF-0603SMT
C14
1
1UF-16V-0805SMT
C14
1
1UF-16V-0805SMTR
224
50R
-040
2SM
TR
224
50R
-040
2SM
T
C176
10NF-0603SMT
C176
10NF-0603SMT
C14
8
10N
F-0
603S
MT
C14
8
10N
F-0
603S
MT
PP
2P
P2
1 2
U14
A
DD
R2-
SD
RA
M-8
4FB
GA
U14
A
DD
R2-
SD
RA
M-8
4FB
GA
NC
_A2
A2
DQ
14B
1D
Q15
B9
DQ
9C
2
DQ
8C
8
DQ
12D
1
DQ
11D
3
DQ
10D
7
DQ
13D
9
DQ
6F
1D
Q7
F9
DQ
1G
2
DQ
0G
8
DQ
4H
1
DQ
3H
3
DQ
2H
7
DQ
5H
9
NC
_E2
E2
LDQ
S#/
NU
E8
LDM
F3
LDQ
SF
7
CK
J8
CK
#K
8
CK
EK
2
WE
#K
3
RA
S#
K7
OD
TK
9
BA
0L2
BA
1L3
CA
S#
L7
CS
#L8
RF
U_L
1L1
A0
M8
A1
M3
A2
M7
A3
N2
A4
N8
A5
N3
A6
N7
A7
P2
A8
P8
A9
P3
A10
M2
A11
P7
A12
R2
RF
U_R
3R
3
RF
U_R
7R
7
NC
_R8
R8
UD
MB
3
UD
QS
B7
UD
QS
#/N
UA
8
C163
10NF-0603SMT
C163
10NF-0603SMT
C178
10NF-0603SMT
C178
10NF-0603SMT
C14
7
100N
F-0
603S
MT
C14
7
100N
F-0
603S
MT
PP
1P
P1
1 2
C164
10NF-0603SMT
C164
10NF-0603SMT
C139
100NF-0603SMT
C139
100NF-0603SMT
C14
6
10N
F-0
603S
MT
C14
6
10N
F-0
603S
MT
C14
5
100N
F-0
603S
MT
C14
5
100N
F-0
603S
MT
C151
100NF-0603SMT
C151
100NF-0603SMT
R661K-0603SMT
R661K-0603SMT
C16
5
100N
F-0
603S
MT
C16
5
100N
F-0
603S
MT
C174
10NF-0603SMT
C174
10NF-0603SMT
C157
100NF-0603SMT
C157
100NF-0603SMT
FB
6B
LM41
PG
600S
N1
FB
6B
LM41
PG
600S
N1
U14
B
DD
R2-
SD
RA
M-8
4FB
GA
U14
B
DD
R2-
SD
RA
M-8
4FB
GA
VD
DA
1
VD
DE
1
VD
DJ9
VD
DM
9
VD
DR
1
VS
SA
3
VS
SE
3
VS
SJ3
VS
SN
1
VS
SP
9
VD
DQ
A9
VD
DQ
C1
VD
DQ
C3
VD
DQ
C7
VD
DQ
C9
VD
DQ
E9
VD
DQ
G1
VD
DQ
G3
VD
DQ
G7
VD
DQ
G9
VS
SQ
A7
VS
SQ
B2
VS
SQ
B8
VS
SQ
D2
VS
SQ
D8
VS
SQ
E7
VS
SQ
F2
VS
SQ
F8
VS
SQ
H2
VS
SQ
H8
VD
DL
J1V
RE
FJ2
VS
SD
LJ7
+C
153
22UF-16V-TANTBSMT
+C
153
22UF-16V-TANTBSMT
+C
142
10UF-16V-TANTBSMT
+C
142
10UF-16V-TANTBSMT
FB
8
BLM
41P
G60
0SN
1
FB
8
BLM
41P
G60
0SN
1
C168
100NF-0603SMT
C168
100NF-0603SMT
R611K-0603SMT
R611K-0603SMT
R1
R1
R1=50 Ohm
RP
2C
TS
-RT
2402
B7
R1
R1
R1=50 Ohm
RP
2C
TS
-RT
2402
B7
A2A2
B2B2
C2C2
D2D2
E2E2
F2F2
G2G2
H2H2
J2J2
A3
A3
B3
B3
C3
C3
D3
D3
E3
E3
F3
F3
G3
G3
H3
H3
J3J3
A1
A1
B1
B1
C1
C1
D1
D1
E1
E1
F1
F1
G1
G1
H1
H1
J1J1
C181
100NF-0603SMT
C181
100NF-0603SMT
+C
166
22UF-16V-TANTBSMT
+C
166
22UF-16V-TANTBSMT
C170
10NF-0603SMT
C170
10NF-0603SMT
SP
3S
P3 1
C15
4
1UF-16V-0805SMT
C15
4
1UF-16V-0805SMT
+C
140
100UF-FKSMT
+C
140
100UF-FKSMT
C180
10NF-0603SMT
C180
10NF-0603SMT
C14
4
1UF-16V-0805SMT
C14
4
1UF-16V-0805SMT
C22
010
NF
-040
2SM
TC
220
10N
F-0
402S
MT
R63
OP
EN
-060
3SM
TR
63O
PE
N-0
603S
MT
U13
LP29
98-S
O8
U13
LP29
98-S
O8
GND 1
SD
2
VS
EN
SE
3V
RE
F4
VD
DQ
5
AVIN6
PVIN7
VT
T8
C179
100NF-0603SMT
C179
100NF-0603SMT
C171
100NF-0603SMT
C171
100NF-0603SMT
R64
0R-0
603S
MT
R64
0R-0
603S
MT
C159
100NF-0603SMT
C159
100NF-0603SMT
C156
10NF-0603SMT
C156
10NF-0603SMT
C16
2
10N
F-0
603S
MT
C16
2
10N
F-0
603S
MT
R22
350
R-0
402S
MT
R22
350
R-0
402S
MT
+
C138
47UF-10V-TANTBSMT
+
C138
47UF-10V-TANTBSMT
C175
100NF-0603SMT
C175
100NF-0603SMT
C16
0
100N
F-0
603S
MT
C16
0
100N
F-0
603S
MT
C143
100NF-0603SMT
C143
100NF-0603SMT
C173
100NF-0603SMT
C173
100NF-0603SMT
C16
1
10N
F-0
603S
MT
C16
1
10N
F-0
603S
MT
C136
100NF-0603SMT
C136
100NF-0603SMT
SP
4S
P4 1
C158
100NF-0603SMT
C158
100NF-0603SMT
R604_7K-0603SMT
R604_7K-0603SMT
29
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 27. FPGA Test5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
DD
R2_
DQ
S0
DD
R2_
15
DD
R2_
DQ
1D
DR
2_30
DD
R2_
DQ
4D
DR
2_33
DD
R2_
DQ
6D
DR
2_35
DD
R2_
DQ
2D
DR
2_31
DD
R2_
DQ
0D
DR
2_29
DD
R2_
DQ
5D
DR
2_34
DD
R2_
DQ
7D
DR
2_36
DD
R2_
DQ
3D
DR
2_32
DD
R2_
DQ
8D
DR
2_37
DD
R2_
DQ
9D
DR
2_38
DD
R2_
DQ
14D
DR
2_43
DD
R2_
DQ
13D
DR
2_42
DD
R2_
DQ
11D
DR
2_40
DD
R2_
DQ
10D
DR
2_39
DD
R2_
DQ
15D
DR
2_44
DD
R2_
DQ
12D
DR
2_41
DD
R2_
DQ
S1
DD
R2_
13D
DR
2_D
QS
0#D
DR
2_14
DD
R2_
A5
DD
R2_
23
DD
R2_
A3
DD
R2_
25
DD
R2_
A0
DD
R2_
28
DD
R2_
A8
DD
R2_
20
DD
R2_
A4
DD
R2_
24
DD
R2_
A1
DD
R2_
27
DD
R2_
A7
DD
R2_
21D
DR
2_A
6D
DR
2_22
DD
R2_
A2
DD
R2_
26
DD
R2_
A9
DD
R2_
19D
DR
2_A
10D
DR
2_18
DD
R2_
A12
DD
R2_
16D
DR
2_A
11D
DR
2_17
DD
R2_
DM
0D
DR
2_11
DD
R2_
DM
1D
DR
2_10
DD
R2_
DQ
S1#
DD
R2_
12
DD
R2_
OD
T0
DD
R2_
3
DD
R2_
RA
S#
DD
R2_
5D
DR
2_W
E#
DD
R2_
6
DD
R2_
CS
0#D
DR
2_2
DD
R2_
CE
0#D
DR
2_7
DD
R2_
BA
0D
DR
2_1
DD
R2_
BA
1D
DR
2_0
DD
R2_
K#
DD
R2_
8D
DR
2_K
DD
R2_
9
DD
R2_
CA
S#
DD
R2_
4
SE
G8
SE
G2
SE
G11
SE
G14
SE
G7
SE
G4
SE
G10
SE
G13
SE
G15
SE
G6
SE
G16
SE
G9
SE
G3
SE
G12
SE
G0
SE
G1
SE
G5
SW
ITC
H5
SW
ITC
H6
SW
ITC
H7
SW
ITC
H8
SW
ITC
H3
SW
ITC
H2
SW
ITC
H4
SW
ITC
H1
LA18
LA19
LA20
LA21
LA34
LA22
LA23
LA24
LA25
LA26
LA27
LA28
LA29
LA30
LA31
LA32
LA33
LA1
LA2
LA3
LA4
LA5
LA6
LA7
LA8
LA9
LA10
LA11
LA12
LA13
LA14
LA15
LA16
LA17
FP
GA
_0F
PG
A_1
FP
GA
_2F
PG
A_3
FP
GA
_4F
PG
A_5
FP
GA
_6F
PG
A_7
FP
GA
_8F
PG
A_9
FP
GA
_10
FP
GA
_11
FP
GA
_12
FP
GA
_13
FP
GA
_14
FP
GA
_15
LED
0LE
D1
LED
3LE
D2
LED
5
LED
7LE
D6
LED
4
LED
9
LED
11LE
D10
LED
8
LED
13
LED
15LE
D14
LED
12
TP
_3T
P_4
TP
_5T
P_6
TP
_7
TP
_14
TP
_2
TP
_15
TP
_1T
P_0
TP
_9T
P_1
0T
P_1
1
TP
_13
TP
_12
TP
_8
OS
C_I
N_1
OS
C_I
N_2
OS
C_I
N_3
VR
EF
1_6
VR
EF
1_6
DD
R2_
OD
T0
DD
R2_
DQ
S1
DD
R2_
DM
0
DD
R2_
DM
1
DD
R2_
DQ
S1#
DD
R2_
A5
DD
R2_
A3
DD
R2_
A0
DD
R2_
A4
DD
R2_
A2
DD
R2_
RA
S#
DD
R2_
CS
0#
DD
R2_
CE
0#
DD
R2_
BA
0D
DR
2_B
A1
DD
R2_
CA
S#
DD
R2_
A8
DD
R2_
A7
DD
R2_
A6
DD
R2_
A9
DD
R2_
A10
DD
R2_
WE
#
DD
R2_
K#
DD
R2_
K
DD
R2_
DQ
9D
DR
2_D
Q8
DD
R2_
DQ
14
DD
R2_
DQ
13
DD
R2_
DQ
11
DD
R2_
DQ
15
DD
R2_
DQ
12
DD
R2_
DQ
S0
DD
R2_
DQ
1
DD
R2_
DQ
4D
DR
2_D
Q6
DD
R2_
DQ
2
DD
R2_
DQ
0
DD
R2_
DQ
5
DD
R2_
DQ
7D
DR
2_D
Q3
DD
R2_
DQ
10
DD
R2_
DQ
S0#
OS
C_I
N_3
DD
R2_
A12
DD
R2_
A11
DD
R2_
A1
DD
R2_
OS
C_C
LKN
DD
R2_
OS
C_C
LKP
DD
R2_
OS
C_C
LKN
DD
R2_
OS
C_C
LKP
1_8V
DD
R2_
VT
T
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
1_8V
3_3V
DD
R2_
VT
T
DD
R2_
[0:4
4][7
]
SE
G[0
:16]
[9]
SW
ITC
H[1
:8]
[9]
x1_P
RS
NT
n[6
]x4
_PR
SN
Tn
[6]
LA[1
:34]
[9]
FP
GA
_[0:
15]
[5]
LED
[0:1
5][9
]
TP
_[0:
15]
[9]
OS
C_I
N_[
1:3]
[9]
FP
GA
_SM
A_R
EF
CLK
P[9
]F
PG
A_S
MA
_RE
FC
LKN
[9]
PC
IE_P
ER
ST
N[6
]
GS
RN
[6]
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
FP
GA
C
89
Mon
day,
Apr
il 06
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
FP
GA
C
89
Mon
day,
Apr
il 06
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
FP
GA
C
89
Mon
day,
Apr
il 06
, 200
9
These pins are connected
to the XO CPLD.
PLACE CLOSE TO U1
R22
850
R-0
402S
MT
R22
850
R-0
402S
MT
EC
P3-
672f
pBG
A
U1C
EC
P3-
672f
pBG
A
U1C
PR
19A
J23
PR
19B
H23
PR
20A
G26
PR
20B
F26
PR
22A
F24
PR
22B
G24
PR
23A
H26
PR
23B
H25
PR
25A
K23
PR
25B
K22
PR
25E
_AF
25
PR
25E
_BE
26
PR
25E
_CL2
1
PR
25E
_DL2
2
PR
26A
H24
PR
26B
G25
PR
28A
L20
PR
28B
M21
PR
29A
K24
PR
29B
J24
PR
31A
M23
PR
31B
M24
PR
32A
L24
PR
32B
K25
PR
34A
/VR
EF
1_2
M22
PR
34B
/VR
EF
2_2
N21
PR
35A
J26
PR
35B
K26
PR
37A
/RU
M0_
GD
LLT
_IN
_AN
23
PR
37B
/RU
M0_
GD
LLT
_IN
_BN
22
PR
38A
/RU
M0_
GD
LLT
_FB
_AK
19
PR
38B
/RU
M0_
GD
LLT
_FB
_BL1
9
PR
40A
P23
PR
40B
R22
PR
41A
L25
PR
41B
L26
PR
43A
/PC
LKT
2_0
P21
PR
43B
/PC
LKC
2_0
P22
PR
43E
_A/R
UM
2_G
PLL
T_F
B_A
M25
PR
43E
_B/R
UM
2_G
PLL
T_F
B_B
M26
PR
43E
_C/R
UM
2_G
PLL
_IN
_AT
21
PR
43E
_D/R
UM
2_G
PLL
T_I
N_B
R21
VC
CIO
2K
18
VC
CIO
2M
19
VC
CIO
2N
18
VC
CIO
2N
19
VT
T2
N20
EC
P3-
672f
pBG
A
U1E
EC
P3-
672f
pBG
A
U1E
PL4
4A/L
DQ
49P
1
PL4
4B/L
DQ
49P
2
PL4
6A/P
CLK
T6_
0/LD
Q49
N5
PL4
6B/P
CLK
C6_
0/LD
Q49
N6
PL4
7A/L
DQ
49R
1
PL4
7B/L
DQ
49R
2
PL4
9A/L
DQ
S49
N3
PL4
9B/L
DQ
S49
#P
3
PL5
0A/L
DQ
49T
2
PL5
0B/L
DQ
49U
3
PL5
2A/V
RE
F1_
6/LD
Q49
P5
PL5
2B/V
RE
F_2
_6/L
DQ
49P
6
PL5
3A/L
DQ
58P
4
PL5
3B/L
DQ
58R
3
PL5
5A/L
DQ
58R
5
PL5
5B/L
DQ
58R
6
PL5
6A/L
DQ
58T
1
PL5
6B/L
DQ
58U
1
PL5
8A/L
DQ
S58
T3
PL5
8B/L
DQ
S58
#R
4
PL5
9A/L
DQ
58V
1
PL5
9B/L
DQ
58U
2
PL6
1A/L
DQ
58T
7
PL6
1B/L
DQ
58T
8
PL6
1E_A
/LLM
1_G
PLL
T_F
B_A
W1
PL6
1E_B
/LLM
1_G
PLL
T_F
B_B
W2
PL6
1E_C
/LLM
1_G
PLL
T_I
N_A
U4
PL6
1E_D
/LLM
1_G
PLL
T_I
N_B
V5
PL6
2A/L
DQ
67Y
3
PL6
2B/L
DQ
67W
3
PL6
4A/L
DQ
67T
5
PL6
4B/L
DQ
67T
6
PL6
5A/L
DQ
67V
3
PL6
5B/L
DQ
67V
4
PL7
0E_A
/LLM
2_G
PLL
T_F
B_A
W4
PL7
0E_B
/LLM
2_G
PLL
T_F
B_B
W5
PL7
0E_C
/LLM
2_G
PLL
T_I
N_A
U6
PL7
0E_D
/LLM
2_G
PLL
T_I
N_B
U5
PL7
9E_A
/LLM
3_G
PLL
T_F
B_A
Y1
PL7
9E_B
/LLM
3_G
PLL
T_F
B_B
Y2
PL7
9E_C
/LLM
3_G
PLL
T_I
N_A
U7
PL7
9E_D
/LLM
3_G
PLL
T_I
N_A
U8
PL8
0A/L
DQ
85A
A1
PL8
0B/L
DQ
85A
A2
PL8
2A/L
DS
85V
6
PL8
2B/L
DQ
85V
7
PL8
3A/L
DQ
85A
B1
PL8
3B/L
DQ
85A
C1
PL8
5A/L
DQ
S85
W7
PL8
5B/L
DQ
S85
#W
6
PL8
6A/L
DQ
85A
C2
PL8
6B/L
DQ
85A
C3
PL8
8A/L
DQ
85Y
5
PL8
8B/L
DQ
85A
A5
PL8
9A/L
DQ
94A
A3
PL8
9B/L
DQ
94A
A4
PL9
1A/L
DQ
94A
B5
PL9
1B/L
DQ
94A
B6
PL9
2A/L
DQ
94A
B3
PL9
2B/L
DQ
94A
B4
PL9
4A/L
DQ
S94
Y6
PL9
4B/L
DQ
S94
#Y
7
PL9
5A/L
DQ
94A
D1
PL9
5B/L
DQ
94A
D2
PL9
7A/L
DQ
94W
8
PL9
7B/L
DQ
94W
9
PB
2AA
D4
PB
2BA
E3
PB
4AA
A7
PB
4BA
B7
PB
5AA
D3
PB
5BA
C4
PB
8AA
E2
PB
8BA
F3
PB
10A
Y8
PB
11A
AE
4
PB
11B
AF
4
PB
13A
V10
PB
13B
W10
VC
CIO
6P
8
VC
CIO
6P
9
VC
CIO
6R
8
VC
CIO
6U
9
VT
T6
P7
R73
0R-0
603S
MTR
730R
-060
3SM
T
EC
P3-
672f
pBG
A
U1A
EC
P3-
672f
pBG
A
U1A
PT
2AB
6
PT
2BC
7
PT
4AD
5
PT
4BC
4
PT
5AD
6
PT
5BC
6
PT
7AC
5
PT
7BB
4
PT
8AD
8
PT
8BC
8
PT
10A
G7
PT
10B
H8
PT
11A
A3
PT
11B
A4
PT
13A
F7
PT
13B
F8
PT
14A
B7
PT
14B
A7
PT
16A
E8
PT
16B
E9
PT
17A
A5
PT
17B
A6
PT
19A
G8
PT
19B
F9
PT
38A
D9
PT
38B
D10
PT
40A
F10
PT
40B
E10
PT
41A
A8
PT
41B
B8
PT
43A
G10
PT
43B
G9
PT
44A
C9
PT
44B
C10
PT
46A
H10
PT
46B
H11
PT
56A
A9
PT
56B
B10
PT
58A
F11
PT
58B
G11
PT
59A
A10
PT
59B
A11
PT
61A
D12
PT
61B
C11
PT
62A
B11
PT
62B
B12
PT
64A
E11
PT
64B
E12
PT
65A
A12
PT
65B
B13
PT
67A
C12
PT
67B
C13
PT
68A
A13
PT
68B
A14
PT
70A
F12
PT
70B
G13
PT
71A
A15
PT
71B
A16
PT
73A
E13
PT
73B
D13
VC
CIO
0H
12
VC
CIO
0H
13
VC
CIO
0J1
0
VC
CIO
0J1
3
R741K-0603SMT
R741K-0603SMT
EC
P3-
672f
pBG
A
U1B
EC
P3-
672f
pBG
A
U1B
PT
74A
C15
PT
74B
B15
PT
76A
C14
PT
76B
D14
PT
77A
B16
PT
77B
C16
PT
79A
F13
PT
79B
F14
PT
80A
A17
PT
80B
A18
PT
82A
B17
PT
82B
C17
PT
83A
A19
PT
83B
A20
PT
85A
E14
PT
85B
E15
PT
86A
A21
PT
86B
B20
PT
88A
G14
PT
88B
F15
PT
89A
C20
PT
89B
B19
PT
91A
D15
PT
91B
E16
PT
101A
E17
PT
101B
F18
PT
103A
G16
PT
103B
F16
PT
104A
C19
PT
104B
D19
PT
106A
H16
PT
106B
H17
PT
107A
C18
PT
107B
D18
PT
109A
F17
PT
109B
G17
PT
128A
E19
PT
128B
E20
PT
130A
E18
PT
130B
D17
PT
131A
B21
PT
131B
A22
PT
133A
F19
PT
133B
F20
PT
134A
C22
PT
134B
C21
PT
136A
/VR
EF
1_1
G18
PT
136B
/VR
EF
2_1
G19
VC
CIO
1H
14
VC
CIO
1H
15
VC
CIO
1J1
4
VC
CIO
1J1
7
R72
1K_A
DJ/
SM
T3M
M
R72
1K_A
DJ/
SM
T3M
M
R70
4_7K-0603SMT
R70
4_7K-0603SMT
C224
100NF-0603SMT
C224
100NF-0603SMT
R681K-0603SMT
R681K-0603SMT
+C
223
10UF-16V-TANTBSMT
+C
223
10UF-16V-TANTBSMT
EC
P3-
672f
pBG
A
U1F
EC
P3-
672f
pBG
A
U1F
PL8
AB
2
PL8
BB
3
PL1
0AD
4
PL1
0BE
4
PL1
1AC
3
PL1
1BD
3
PL1
3AG
5
PL1
3BG
6
PL1
4AE
3
PL1
4BF
4
PL1
6AH
6
PL1
6BJ6
PL1
7AC
2
PL1
7BD
2
PL1
9AK
8
PL1
9BJ7
PL2
0AF
2
PL2
0BF
3
PL2
2AK
7
PL2
2BK
6
PL2
3AG
2
PL2
3BG
3
PL2
5AH
5
PL2
5BJ5
PL2
5E_A
/LU
M2_
GP
LLT
_FB
_AH
4
PL2
5E_B
/LU
M2_
GP
LLT
_FB
_BH
3
PL2
5E_C
/LU
M2_
GP
LLT
_IN
_AL8
PL2
5E_D
/LU
M2_
GP
LLT
_IN
_BL7
PL2
6AK
2
PL2
6BK
1
PL2
8AJ4
PL2
8BJ3
PL2
9AD
1
PL2
9BC
1
PL3
1AK
4
PL3
1BK
5
PL3
2AE
1
PL3
2BF
1
PL3
4A/V
RE
F1_
7L5
PL3
4B/V
RE
F2_
7L6
PL3
5AH
2
PL3
5BG
1
PL3
7A/L
UM
0_G
DLL
T_I
N_A
K3
PL3
7B/L
UM
0_G
DLL
T_I
N_B
L3
PL3
8A/L
UM
0_G
DLL
T_F
B_A
H1
PL3
8B/L
UM
0_G
DLL
T_F
B_B
J1
PL4
0AM
5
PL4
0BM
6
PL4
1AL2
PL4
1BL1
PL4
3A/P
CLK
T7_
0M
4
PL4
3B/P
CLK
C7_
0N
4
PL4
3E_A
/LU
M0_
GP
LLT
_FB
_AM
1
PL4
3E_B
/LU
M0_
GP
LLT
_FB
_BN
1
PL4
3E_C
/LU
M0_
GP
LLT
_IN
_AM
3
PL4
3E_D
/LU
M0_
GP
LLT
_IN
_BM
2
VC
CIO
7K
9
VC
CIO
7M
8
VC
CIO
7N
8
VC
CIO
7N
9
VT
T7
N7
C222
100NF-0603SMT
C222
100NF-0603SMT
R71
4_7K-0603SMT
R71
4_7K-0603SMT
R22250R-0603SMT
R22250R-0603SMT
R22
7
1_6R
-060
3SM
T
R22
7
1_6R
-060
3SM
T
R69
4_7K-0603SMT
R69
4_7K-0603SMT
C22
510
NF
-040
2SM
TC
225
10N
F-0
402S
MT
Y2
CR
YS
TE
K-1
33M
HZ
Y2
CR
YS
TE
K-1
33M
HZ
Q_N
5
Q4
VCC6 GND 3
DIS
#1
NC
2
R67
0R-0
603S
MTR
670R
-060
3SM
T
R75
0R-0
603S
MTR
750R
-060
3SM
T
R22
9
50R
-040
2SM
T
R22
9
50R
-040
2SM
T
C18210NF-0603SMT
C18210NF-0603SMT
EC
P3-
672f
pBG
A
U1D
EC
P3-
672f
pBG
A
U1D
PR
44A
N24
PR
44B
N25
PR
46A
/PC
LKT
3_0
U20
PR
46B
/PC
LKC
3_0
U19
PR
47A
P24
PR
47B
R24
PR
49A
R23
PR
49B
T22
PR
50A
N26
PR
50B
P26
PR
52A
/VR
EF
1_3
T20
PR
52B
/VR
EF
2_3
U21
PR
53A
R25
PR
53B
R26
PR
55A
U24
PR
55B
V24
PR
56A
T25
PR
56B
T24
PR
58A
V21
PR
58B
V22
PR
59A
T26
PR
59B
U26
PR
61A
U23
PR
61B
U22
PR
61E
_A/R
LM1_
GP
LLT
_FB
_AU
25
PR
61E
_B/R
LM1_
GP
LLT
_FB
_BV
26
PR
61E
_C/R
LM1_
GP
LLT
_IN
_AV
20
PR
61E
_D/R
LM1_
GP
LLT
_IN
_BW
19
PR
70E
_A/R
LM2_
GP
LLT
_FB
_AW
26
PR
70E
_B/R
LM2_
GP
LLT
_FB
_BW
25
PR
70E
_C/R
LM2_
GP
LLT
_IN
_AY
26
PR
70E
_D/R
LM2_
GP
LLT
_IN
_BY
25
PR
79E
_A/R
LM3_
GP
LLT
_FB
_AV
23
PR
79E
_B/R
LM3_
GP
LLT
_FB
_BW
24
PR
79E
_C/R
LM3_
GP
LLT
_IN
_AV
17
PR
79E
_D/R
LM3_
GP
LLT
_IN
_BW
18
PR
80A
AA
25
PR
80B
Y24
PR
82A
W23
PR
82B
W22
PR
83A
AA
26
PR
83B
AB
26
PR
85A
W21
PR
85B
W20
PR
86A
AD
26
PR
86B
AD
25
PR
88A
AA
24
PR
88B
AA
23
PR
89A
AC
26
PR
89B
AC
25
PR
91A
Y19
PR
91B
Y20
PR
92A
AB
24
PR
92B
AC
24
PR
94A
Y22
PR
94B
AA
22
PR
95A
AE
25
PR
95B
AF
24
PR
97A
AD
24
PR
97B
AE
24
PB
137A
AD
23
PB
137B
AC
23
PB
139A
AB
20
PB
139B
AB
21
PB
140A
AF
23
PB
140B
AE
23
PB
142A
W17
PB
143A
AB
23
PB
143B
AB
22
PB
145A
Y21
PB
145B
AA
20
VC
CIO
3P
18
VC
CIO
3P
19
VC
CIO
3R
19
VC
CIO
3U
18
VT
T3
P20
30
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Figure 28. VSS/Decoupling5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
SE
G0
SE
G1
LA27
LA33
LA31
LA25
LA29
LA17
LA13
LA23
LA21
LA5
LA15
LA11
LA7
LA19
LA3
LA1
LA9
LA34
LA32
LA22
LA26
LA16
LA30
LA14
LA20
LA12
LA28
LA24
LA10
LA6
LA8
LA4
LA2
LA18
FLA
SH
_CLK
OS
C_I
N_2
OS
C_I
N_3
SE
G15
SE
G14
SE
G13
SE
G12
SE
G11
SE
G10
SE
G9
SE
G8
SE
G7
SE
G6
SE
G5
SE
G4
SE
G3
SE
G2
TP
_8
TP
_3T
P_4
TP
_5T
P_6
TP
_7
TP
_2T
P_1
TP
_0
TP
_9T
P_1
0T
P_1
1
TP
_13
TP
_12
TP
_14
TP
_15
SE
G16
US
R0_
PU
SW
ITC
H5
SW
ITC
H6
SW
ITC
H7
SW
ITC
H8
SW
ITC
H3
SW
ITC
H2
SW
ITC
H4
SW
ITC
H1
PLL
_LK
_PU
US
R1_
PU
X4_
US
R0
LED
12
PO
LL_P
U
X4_
US
R1
LED
15
X4_
PO
LLLE
D4
X4_
US
R2
LED
11
SW
ITC
H5
SW
ITC
H6
L0_P
U
SW
ITC
H7
SW
ITC
H8
SW
ITC
H3
SW
ITC
H2
SW
ITC
H4
SW
ITC
H1
US
R3_
PU
X4_
PLL
_LK
LED
7
X4_
L0LE
D3
PLL
_LK
_PU
US
R0_
PU
US
R1_
PU
DL_
UP
_PU
L0_P
U
US
R3_
PU
US
R2_
PU
PO
LL_P
U
X1_
PO
LLLE
D6
X1_
PLL
_LK
LED
5
X1_
DL_
UP
LED
2
X1_
L0LE
D1
X1_
US
R0
LED
14
X1_
US
R1
LED
13
DL_
UP
_PU
X1_
US
R3
LED
10
X1_
US
R2
LED
9
US
R2_
PU
X4_
US
R3
LED
8
LED
0
OS
C_I
N_1
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
3_3V
FLA
SH
_CLK
[5]
FP
GA
_SM
A_R
EF
CLK
P[8
] FP
GA
_SM
A_R
EF
CLK
N[8
]
SW
ITC
H[1
:8]
[8]
LA[1
:34]
[8]
SE
G[0
:16]
[8]
LED
[0:1
5][8
]
OS
C_I
N_[
1:3]
[8]
TP
_[0:
15]
[8]
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
FP
GA
TE
ST
C
99
Mon
day,
Feb
ruar
y 23
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
FP
GA
TE
ST
C
99
Mon
day,
Feb
ruar
y 23
, 200
9
Titl
e
Siz
eP
roje
ctR
ev
Dat
e:S
heet
of
1605 Valley Center Parkway
Bethlehem, PA 18017
EC
P3
PC
Ie D
evK
it E
val B
oard
1.0
FP
GA
TE
ST
C
99
Mon
day,
Feb
ruar
y 23
, 200
9
SEGMENT BGA
A B7
B F8
C F7
D A4
E A3
F H8
G G7
H C8
K D8
M B4
N C5
P C6
R D6
S C4
T D5
U C7
DP B6
LOGIC ANALYZER PROBE
100MHZ GENERAL PURPOSE CLOCKS
16-SEGMENT DISPLAY
PLACE CLOSE TO U1
Connected to SMA inputs
DIP SWITCH
LEDs
PLL LOCK STATUS
POLLING STATUS
L0
DL UP
LED USER 3
LED USER 2
LED USER 1
LED USER 0
SWITCH BGA
1 D9
2 F9
3 G8
4 A6
5 A5
6 E9
7 E8
8 A7
LED BGA
0 D10
1 F10
2 E10
3 A8
4 B8
5 G10
6 G9
7 C9
8 C10
9 H10
10 H11
11 A9
12 B10
13 F11
14 G11
15 A10
RN
4HR
N4H
89
RN
5FE
XB
2HV
471J
V47
0RR
N5F
EX
B2H
V47
1JV
470R
611
RN
2GE
XB
2HV
472J
V4_
7KR
N2G
EX
B2H
V47
2JV
4_7K
710
D24
LED
-SM
T12
06_B
LUE
D24
LED
-SM
T12
06_B
LUE
ABCDEFGHKMNPRSTUDP
D23
LTP
-587
HR
/16-
SE
GM
EN
T
ABCDEFGHKMNPRSTUDP
D23
LTP
-587
HR
/16-
SE
GM
EN
T
18
211613986547 311 1715121410
RN
2CE
XB
2HV
472J
V4_
7KR
N2C
EX
B2H
V47
2JV
4_7K
314
RN
4AR
N4A
116
RN
3CR
N3C
314
RN
5GE
XB
2HV
471J
V47
0RR
N5G
EX
B2H
V47
1JV
470R
710
RN
2HE
XB
2HV
472J
V4_
7KR
N2H
EX
B2H
V47
2JV
4_7K
89
RN
2BE
XB
2HV
472J
V4_
7KR
N2B
EX
B2H
V47
2JV
4_7K
215
RN
4CE
XB
2HV
151J
V15
0RR
N4C
EX
B2H
V15
1JV
150R
314
RN
4BR
N4B
215
R80
OP
EN
-060
3SM
TR
80O
PE
N-0
603S
MT
D25
LED
-SM
T12
06_B
LUE
D25
LED
-SM
T12
06_B
LUE
D11
LED
-SM
T12
06_G
RE
END11
LED
-SM
T12
06_G
RE
EN
RN
2DE
XB
2HV
472J
V4_
7KR
N2D
EX
B2H
V47
2JV
4_7K
413
RN
3DR
N3D
413
J6 SM
A
J6 SM
A
12 3 4 5
Y1
CT
S-C
B3L
V-3
C-1
00.0
0MH
Z
Y1
CT
S-C
B3L
V-3
C-1
00.0
0MH
Z
N/C
1
GN
D2
OU
T3
Vcc
4
RN
5HE
XB
2HV
471J
V47
0RR
N5H
EX
B2H
V47
1JV
470R
89
D20
LED
-SM
T12
06_R
ED
D20
LED
-SM
T12
06_R
ED
C18
7
100N
F-0
603S
MT
C18
7
100N
F-0
603S
MT
D26
LED
-SM
T12
06_B
LUE
D26
LED
-SM
T12
06_B
LUE
RN
3AE
XB
2HV
151J
V
150R
RN
3AE
XB
2HV
151J
V
150R
116
RN
4DR
N4D
413
RN
5AE
XB
2HV
471J
V47
0RR
N5A
EX
B2H
V47
1JV
470R
116
D13
LED
-SM
T12
06_G
RE
END13
LED
-SM
T12
06_G
RE
EN
RN
3ER
N3E
512
C18
3
100N
F-0
603S
MT
C18
3
100N
F-0
603S
MT
D15
LED
-SM
T12
06_Y
ELL
OW
D15
LED
-SM
T12
06_Y
ELL
OW
RN
5CE
XB
2HV
471J
V47
0RR
N5C
EX
B2H
V47
1JV
470R
314
RN
4ER
N4E
512
R76
150R
-060
3SM
TR
7615
0R-0
603S
MT
SW
5
SW
DIP
-8/S
M
SW
5
SW
DIP
-8/S
M
RN
3FR
N3F
611
RN
5BE
XB
2HV
471J
V47
0RR
N5B
EX
B2H
V47
1JV
470R
215
C18
6
100N
F-0
603S
MT
C18
6
100N
F-0
603S
MT
D17
LED
-SM
T12
06_Y
ELL
OW
D17
LED
-SM
T12
06_Y
ELL
OW
D16
LED
-SM
T12
06_Y
ELL
OW
D16
LED
-SM
T12
06_Y
ELL
OW
R78
51R
-060
3SM
TR
7851
R-0
603S
MT
C18
410
0NF
-060
3SM
TC
184
100N
F-0
603S
MT
D12
LED
-SM
T12
06_G
RE
EN
D12
LED
-SM
T12
06_G
RE
EN
RN
4FR
N4F
611
R79
OP
EN
-060
3SM
TR
79O
PE
N-0
603S
MT
RN
5DE
XB
2HV
471J
V47
0RR
N5D
EX
B2H
V47
1JV
470R
413
RN
3GR
N3G
710
R77
51R
-060
3SM
TR
7751
R-0
603S
MT
D22
LED
-SM
T12
06_R
ED
D22
LED
-SM
T12
06_R
ED
D19
LED
-SM
T12
06_R
ED
D19
LED
-SM
T12
06_R
ED
J7 SM
A
J7 SM
A
12 3 4 5
RN
2EE
XB
2HV
472J
V4_
7KR
N2E
EX
B2H
V47
2JV
4_7K
512
C18
510
NF
-060
3SM
TC
185
10N
F-0
603S
MT
RN
4GR
N4G
710
D14
LED
-SM
T12
06_G
RE
EN
D14
LED
-SM
T12
06_G
RE
EN
LA1
2-57
6700
4-2
LA1
2-57
6700
4-2
5V1
SC
L2
GN
D3
SD
A4
CLK
15
CLK
6
77
88
99
1010
1111
1212
1313
1414
1515
1616
1717
1818
1919
2020
2121
2222
2323
2424
2525
2626
2727
2828
2929
3030
3131
3232
3333
3434
3535
3636
3737
3838
D27
LED
-SM
T12
06_B
LUE
D27
LED
-SM
T12
06_B
LUE
D21
LED
-SM
T12
06_R
ED
D21
LED
-SM
T12
06_R
ED
RN
3HR
N3H
89
RN
2FE
XB
2HV
472J
V4_
7KR
N2F
EX
B2H
V47
2JV
4_7K
611
J5 HE
AD
ER
9X
2
J5 HE
AD
ER
9X
2
2 4 6 8 10 12 14 16 18
1 3 5 7 9 11 13 15 17R
N5E
EX
B2H
V47
1JV
470R
RN
5EE
XB
2HV
471J
V47
0R5
12
RN
3BR
N3B
215
RN
2AE
XB
2HV
472J
V4_
7KR
N2A
EX
B2H
V47
2JV
4_7K
116
D18
LED
-SM
T12
06_Y
ELL
OW
D18
LED
-SM
T12
06_Y
ELL
OW
U15 CY
2304
-1
U15 CY
2304
-1
RE
F1
CLK
A1
2
CLK
A2
3
GN
D4
CLK
B1
5C
LKB
26
VD
D7
FB
K8
31
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
Appendix B. Bill of MaterialsTable 17. Bill of Materials
Item Quantity Reference Part Manufacturer Part Number Description
1 1 CN1 PCI Express x4 Edge Finger Conn. PCB Edge finger
2 1 CN2 PCI Express x1 Edge Finger Conn. PCB Edge finger
3 1 C1 470UF-FKSMT Panasonic EEV-FK1V471Q CAP 470UF 35V ELECT FK SMD
4 2 C2, C140 100UF-FKSMT Panasonic EEEFK1V101XP CAP 100UF 35V ELECT FK SMD
5 5 C3, C4, C7, C9, C142 10UF-16V-TANTBSMT AVX TAJB106K016R CAP 10UF 16V TANT B-SIZE
6 4 C5, C6, C8, C10 330UF-FKSMT Panasonic EEEFK1C331P CAP 330UF 16V ELECT FK SMD
7 30 C11, C12, C13, C14, C15, C16, C17, C18, C36, C37, C38, C39, C40, C56, C57, C58, C59, C60, C61, C62, C63, C64, C65, C66, C67, C68, C83, C84, C85, C86
1000PF-0402SMT Panasonic ECJ-0EB1E102K CAP 1000PF 25V CERAMIC X7R 0402
8 54 C19, C20, C21, C22, C23, C24, C25, C41, C43, C47, C49, C50, C51, C52, C53, C54, C55, C70, C73, C76, C79, C80, C88, C94, C96, C98, C100, C111, C113, C115, C117, C119, C121, C123, C125, C146, C148, C149, C150, C155, C156, C161, C162, C163, C164, C169, C170, C172, C174, C176, C178, C180, C182, C185
10NF-0603SMT Kemet C0603C103K5RACTU CAP .01UF 50V CERAMIC X7R 0603
9 14 C26, C34, C48, C71, C77, C103, C105, C107, C109, C137, C141, C144, C154, C167
1UF-16V-0805SMT Panasonic ECJ-2FB1C105K CAP 1UF 16V CERAMIC 0805 X5R
10 12 C27, C29, C44, C69, C81, C102, C104, C106, C108, C152, C153, C166
22UF-16V_TANTBSMT Kemet T491B226M016AT CAPACITOR TANT 22UF 16V 20% SMD
11 54 C28, C30, C31, C32, C33, C35, C42, C45, C46, C72, C74, C75, C78, C82, C87, C89, C90, C91, C92, C93, C95, C97, C99, C101, C110, C112, C114, C116, C118, C120, C122, C124, C136, C139, C143, C145, C147, C151, C157, C158, C159, C160, C165, C168, C171, C173, C175, C177, C179, C181, C183, C184, C186, C187
100NF-0603SMT Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603
12 10 C126, C127, C128, C129, C130, C131, C132, C133, C134, C135
100NFX5R-0402SMT Kemet C0402C104K8PACTU CAP .10UF 10V CERAMIC X5R 0402
13 1 C138 47UF-10V-TANTBSMT Kemet T491B476M010AT CAPACITOR TANT 47UF 10V 20% SMD
14 11 D1, D2, D3, D4, D5, D9, D10, D11, D12, D13, D14
LED-SMT1206_GREEN Panasonic LNJ316C83RA LED GREEN (UP) W/LENS 1206
15 7 D6, D7, D8, D19, D20, D21, D22 LED-SMT1206_RED Panasonic LNJ211R82RA LED RED (UP) W/LENS 1206
16 4 D15, D16, D17, D18 LED-SMT1206_YELLOW Panasonic LNJ411K84RA LED YELLOW (UP) W/LENS 1206
17 1 D23 LTP-587HR/16-SEGMENT Lite-On LTP-587HR 16-segment array
18 4 D24, D25, D26, D27 LED-SMT1206_BLUE Panasonic LNJ916C8BRA LED BLUE (UP) W/LENS 1206
19 8 FB1, FB2, FB3, FB4, FB5, FB6, FB7, FB8
BLM41PG600SN1 Murata BLM41PG600SN1L FERRITE CHIP 60 OHM 6000MA 1806
20 5 F1, F2, F3, F4, F5 F1228CT-ND Littlefuse 0154005.DR FUSEBLOCK WITH 5A FUSE SMD
21 1 J1 22HP037-2.1mm Condor 22HP037-2.1mm power input
22 1 J2 HEADER 2X2 Samtec TSW-102-07-T-D 2x2-0.25 Header
23 1 J3 HEADER 2 Samtec TSW-102-07-T-S 2x1-0.25 Header
24 2 J4, J8 HEADER 6 Samtec TSM-106-01-T-SH 6x1-0.25 Header-SMT
25 1 J5 HEADER 9X2 Samtec TSW-109-07-T-D 9x2-0.25 Header
32
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
26 2 J6, J7 SMA Molex 73391-0060 CONN JACK SMA STR 50 OHM PCB
27 1 LA1 2_5767004-2 Amp 2_5767004-2 CONN RECEPT 38POS .025 VERT SMD
28 5 LP1, LP2, LP3, LP4, LP5 5016 Keystone Electronics 5016 TEST POINT PC COMPACT SMT
29 3 MH1, MH2, MH3 M HOLE2
30 2 PP1, PP2 PROBEPOINT
31 4 Q1, Q2, Q3, Q4 2N2222/SOT23 Diodes Inc. MMBT2222A-7-F TRANS NPN 40V 350MW SMD SOT-23
32 1 RN1 EXBV8V472JV Panasonic EXBV8V472JV RES ARRAY 4.7K OHM 5% 4 RES SMD
33 1 RN2 EXB2HV472JV Panasonic EXB2HV472JV RES ARRAY 4.7K OHM 5% 8 RES SMD
34 2 RN3, RN4 EXB2HV151JV Panasonic EXB2HV151JV RES ARRAY 150 OHM 5% 8 RES SMD
35 1 RN5 EXB2HV471JV Panasonic EXB2HV471JV RES ARRAY 470 OHM 5% 8 RES SMD
36 2 RP1, RP2 CTS-R2402B7 CTS Corporation Resistor/Electrocomponents
CTS-R2402B7TR7 RES NET DDR SDRAM 50 OHM 3X9 BGA
37 4 R1, R2, R3, R4 1_8K-1206SMT Panasonic ERJ-8GEYJ182V RES 1.8K OHM 1/4W 5% 1206 SMD
38 1 R76 150R-0603SMT Panasonic ERA-3YEB151V RES 150 OHM 1/16W .1% 0603 SMD
39 23 R6, R7, R8, R21, R22, R27, R28, R29, R30, R31, R32
10K-0603SMT Panasonic ERJ-3GEYJ103V RES 10K OHM 1/10W 5% 0603 SMD
R33, R34, R35, R36, R37, R38, R39, R45, R46, R48, R49, R54
40 7 R9, R10, R53, R64, R67, R73, R75 0R-0603SMT Panasonic ERJ-3GEY0R00V RES ZERO OHM 1/10W 5% 0603 SMD
41 2 R11, R12 OPEN-0805SMT
42 1 R13 12_1K-0603SMT Susumu Co Ltd. RG1608P-1212-B-T5 RES 12.1K OHM 1/10W .1% 0603 SMD
43 2 R14, R20 2K-0603SMT Panasonic ERJ-3EKF2001V RES 2.00K OHM 1/10W 1% 0603 SMD
44 2 R15, R16 100R-0805SMT Panasonic ERJ-6GEYJ101V RES 100 OHM 1/8W 5% 0805 SMD
45 8 R17, R19, R56, R57, R61, R66, R68, R74
1K-0603SMT Panasonic ERJ-3EKF1001V RES 1.00K OHM 1/16W 1% 0603 SMD
46 1 R18 806R-0603SMT Panasonic ERJ-3EKF8060V RES 806 OHM 1/10W 1% 0603 SMD
47 3 R23, R24, R25 680R-0603SMT Panasonic ERJ-3GEYJ681V RES 680 OHM 1/10W 5% 0603 SMD
48 3 R5, R26, R47 220R-0603SMT Panasonic ERJ-3GEYJ221V RES 220 OHM 1/10W 5% 0603 SMD
49 7 R40, R43, R44, R60, R69, R70, R71 4_7K-0603SMT Panasonic ERJ-3GEYJ472V RES 4.7K OHM 1/10W 5% 0603 SMD
50 8 R41, R42, R52, R58, R59, R63, R79, R80
OPEN-0603SMT
51 2 R50, R51 100R-0603SMT Panasonic ERA-3YEB101V RES 100 OHM 1/16W .1% 0603 SMD
Table 17. Bill of Materials (Continued)
Item Quantity Reference Part Manufacturer Part Number Description
33
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
52 1 R55 2_2K-0603SMT Panasonic ERJ-3GEYJ222V RES 2.2K OHM 1/10W 5% 0603 SMD
53 2 R62, R72 1K_ADJ/SMT3MM Murata PVG3A102C01R00 POT 1K 3MM CERM SQ S/T SMD
54 0 R65(deleted) 0R-2010SMT Vishay/Dale CRCW20100000Z0EF RES 0.0 OHM1/2W 5% 2010 SMD
55 2 R77, R78 51R-0603SMT Panasonic ERJ-3GEYJ510V RES 51 OHM 1/10W 5% 0603 SMD
56 4 SP1, SP2, SP3, SP4 TEST POINT
57 4 SW1, SW3, SW6, SW7 SW PUSHBUTTON-SPST C&K Components EP11FPD1SAPE SPST- Momentary RA/SMT
58 1 SW2 SW DIP-3 CTS 194-3MST CTS Corporation Resis-tor/Electrocomponents
194-3MST SWITCH SIDE ACTUATED GOLD 3 SEC
59 1 SW4 B3F-1150 Omron B3F-1150 SWITCH TACT 6MM 100GF H=7.3MM
60 1 SW5 SW DIP-8/SM C&K Components BPA08SB 8-POSITION DIP PACK
61 1 TB1 Terminal Block/ED1202DS On-Shore Tech. ED120/2DS TERMINAL BLOCK 5.08MM VERT 2POS
62 14 TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, TP10
TESTPOINT
TP11, TP12, TP13, TP14
63 1 U1 ECP3-672fpBGA LATTICE SUPPLIED
64 1 U2 PTH12060L Texas Instruments PTH12060LAH MODULE PIP 12VIN 10A ADJ 10-TH
65 1 U3 PTH12060W Texas Instruments PTH12060WAH MODULE PIP 12VIN 10A ADJ 10-TH
66 2 U4, U5 SC1592 Semtech SC1592IMTRT IC LDO ADJ REG 3A TO-263-7
67 1 U6 M25P64-FLASH STMicro M25P64-VMF6P IC SRL FLASH 64MBIT 3V 16-SOP Wide(300MIL)
68 1 U7 MAX6817 Maxim MAX6817-EUT+T ±15kV ESD-Pro-tected, Dual, CMOS Switch Debouncers
69 2 U8,U10 NC7WZ16-MAAO6A/Fair-child TinyLogic
Fairchild NC7WZ16P6X IC BUFFER UHS DUAL SC70-6
70 1 U9 SN74LVC125A/SO14 Texas Instruments SN74LVC125AD IC QUAD BUS BUF-FER GATE 14-SOIC
71 1 U11 S29GL064A Spansion S29GL064N90BF1040 48fBGA FLASH-VBN048
72 1 U12 LCMXO1200C-CSBGA132
LATTICE SUPPLIED
73 1 U13 LP2998-SO8 National Semi LP2998MA/NOPB IC DDR TERMINA-TION REG 8SOIC
74 1 U14 DDR2-SDRAM-84FBGA Micron MT47H16M16BG-37E 16-Bit DDR2
75 1 U15 CY2304-1 Cypress Semiconductor CY2304SXC-1 zero delay buffer
76 1 Y1 CTS-CB3LV-3C-100.00MHZ
CTS-Frequency Controls CB3LV-3l-100M0000-T OSC CLOCK 100.000 MHZ 3.3V SMD
77 1 Bracket
78 2 Screw 4-40 x .250
79 2 Flat washer 4-40
80 2 Lock washer 4-40
81 2 C222, C224 100NF-0603SMT Panasonic ECJ-1VF1C104Z CAP .1UF 16V CERAMIC Y5V 0603
82 1 C223 10UF-16V-TANTBSMT AVX TAJB106K016R CAP 10UF 16V TANT B-SIZE
Table 17. Bill of Materials (Continued)
Item Quantity Reference Part Manufacturer Part Number Description
34
LatticeECP3 PCI Express Solutions Board – Revision A User’s Guide
83 1 R227 1_6R-0603SMT Panasonic ERJ-3GEYJ1R6V RESISTOR 1.6 OHM 1/10W 5% 0603
84 4 R223, R224, R228, R229 50R-0402SMT Vishay FC0402E50R0BTBST1 RES 50 OHM 50MW .1% 0402 SMD
85 1 Y2 CRYSTEK_133MHZ Crystek CCLD-033-50-133.000 OSC LVDS 133.0 MHZ 3.3V 7mmx5mm SMD
86 2 C220, C225 10NF-0402SMT Panasonic ECJ0EB1E103K CAP .01UF 25V CERAMIC X7R 0402
87 1 R222 50R-0603SMT Vishay FC0603E50R0BTBT1 RES 50 OHM 125MW .1% 0603 SMD
88 1 D33 SCHOTTKY/VISHAYV12P10
Vishay V12P10-E3/87A TO277 SCHOTTKY DIODE
Table 17. Bill of Materials (Continued)
Item Quantity Reference Part Manufacturer Part Number Description
