Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic.
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Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426 NITTTR, Chandigarh EDIT -2015 88 Layout Design Analysis of CMOS Comparator using 180nm Technology 1 Jyoti , 2 Rajesh Mehra 1 ME Scholar , 2 Associate Professor, 1, 2 Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training and Research, Chandigarh, India [email protected]ABSTRACT- Comparator is a very useful and basic arithmetic component of digital system. In the world of technology the demand of portable devices are increasing day by day. This paper presents CMOS design of 1-bit comparator on 180nm technology. The layout of 1-bit comparator has been developed using Automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their Power and Area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is developed manually. The result shows that semi-custom consumes less power as compared to Automatic. Key Words: CMOS technology, Power dissipation, Layout, Performance analysis, combinational circuit INTRODUCTION Comparator is one of the fundamental building blocks in most analog-to-digital converters (ADCs) [1]. Comparator are the most important design element for various application such as in embedded processor, general purpose processor, DSP core, image/signal processing and built in self test circuits [2]. Minimizing the power dissipation for the digital circuits requires optimization at all level of the design. So, this optimization depends on circuit style, topologies and in fact includes the technology which is used to implement the digital circuits [3]. In VLSI design Comparator is a basic component which compares two binary number and then determine whether the number is greater than, less than or equal to the other input. The n-bit Comparator is shown in figure 1 A A > B A=B B A > B Fig.1 Block diagram of n-bit Comparator The outcome of comparison is specified by three binary variables that show whether A>B, A=B, or A<B. In the truth table, the circuit for comparing two n-bit numbers, has 2n inputs & 2 2n entries. So, 4 inputs & 16-rows in the truth table for 2-bit numbers and similarly, for 3-bit numbers 6-inputs & 64-rows in the truth table [4]. The logic style used in logic gates basically influences the size, speed, power dissipation and the wiring complexity of a circuit [5]. Circuit size depends on the number of transistors and their sizes and on the wiring complexity [6]. The wiring complexity is determined by the number of connections and their lengths. All mentioned characteristics may vary considerably from one logic style to another and thus proper choice of logic style is very important for circuit performance [7, 8]. The speed, power consumption and chip area are the important factors while designing comparators. The continually-growing application of portable devices makes the power consumption a very critical constraint for circuit designers [9].The CMOS technology produce degraded output in the circuit. As NMOS transistor pass strong logic 0 and weak 1 pass but PMOS transistor is strong 1 pass and weak 1 pass. It is possible to combine NMOS and PMOS transistor into a single switch that is capable of driving its output terminal either to a low or high voltage equally well [10]. Here we use Microwind3.1 to draw the layout of the CMOS circuit. In order to differentiate designs, simulations are carried out for Power and Area. Simulations are performed at 180nm technology. CMOS can be designed by using PMOS and NMOS transistor and CMOS consumes no steady state power. 1-BIT MAGNITUDE COMPARATOR Digital Comparator also called “Magnitude Comparator” is a combinational circuit that compares two numbers in which A and B are two inputs and three outputs A> , = , < and only one of the three outputs would be high accordingly if A is greater than or equal to or less than B. The truth table of 1-bit comparator is shown in Table 1 Table 1. Truth table of 1-bit comparator Input Output A B A> A=B A< 0 0 0 1 0 0 1 0 0 1 1 0 1 0 0 1 1 0 1 0 Karnaugh -Map is used to minimize Boolean function obtained from truth table and shown in figure 2 Equation for (A > B) = ′ n- Bit Magnitude Comparator
Layout Design Analysis of CMOS Comparatorusing 180nm Technology
1 Jyoti , 2Rajesh Mehra1ME Scholar , 2Associate Professor,
1, 2Department of Electronics & Communication Engineering, National Institute of Technical Teachers Training andResearch, Chandigarh, [email protected]
ABSTRACT- Comparator is a very useful and basic arithmeticcomponent of digital system. In the world of technology thedemand of portable devices are increasing day by day. Thispaper presents CMOS design of 1-bit comparator on 180nmtechnology. The layout of 1-bit comparator has been developedusing Automatic and semi-custom techniques. Both the layoutsare compared and analyzed in terms of their Power and Areaconsumption. Automatic layout is generated from its equivalentschematic whereas semi-custom layout is developed manually.The result shows that semi-custom consumes less power ascompared to Automatic.
Key Words: CMOS technology, Power dissipation, Layout, Performanceanalysis, combinational circuit
INTRODUCTIONComparator is one of the fundamental building blocks inmost analog-to-digital converters (ADCs) [1]. Comparatorare the most important design element for various applicationsuch as in embedded processor, general purpose processor,DSP core, image/signal processing and built in self testcircuits [2]. Minimizing the power dissipation for the digitalcircuits requires optimization at all level of the design. So,this optimization depends on circuit style, topologies and infact includes the technology which is used to implement thedigital circuits [3]. In VLSI design Comparator is a basiccomponent which compares two binary number and thendetermine whether the number is greater than, less than orequal to the other input. The n-bit Comparator is shown infigure 1
A A > B
A=BB
A > B
Fig.1 Block diagram of n-bit Comparator
The outcome of comparison is specified by three binaryvariables that show whether A>B, A=B, or A<B. In the truthtable, the circuit for comparing two n-bit numbers, has 2ninputs & 22n entries. So, 4 inputs & 16-rows in the truth tablefor 2-bit numbers and similarly, for 3-bit numbers 6-inputs &64-rows in the truth table [4]. The logic style used in logicgates basically influences the size, speed, power dissipationand the wiring complexity of a circuit [5]. Circuit sizedepends on the number of transistors and their sizes and on
the wiring complexity [6]. The wiring complexity is determinedby the number of connections and their lengths. All mentionedcharacteristics may vary considerably from one logic style toanother and thus proper choice of logic style is very important forcircuit performance [7, 8]. The speed, power consumption andchip area are the important factors while designing comparators.The continually-growing application of portable devices makesthe power consumption a very critical constraint for circuitdesigners [9].The CMOS technology produce degraded output inthe circuit. As NMOS transistor pass strong logic 0 and weak 1pass but PMOS transistor is strong 1 pass and weak 1 pass. It ispossible to combine NMOS and PMOS transistor into a singleswitch that is capable of driving its output terminal either to a lowor high voltage equally well [10].Here we use Microwind3.1 to draw the layout of the CMOScircuit. In order to differentiate designs, simulations are carriedout for Power and Area. Simulations are performed at 180nmtechnology. CMOS can be designed by using PMOS and NMOStransistor and CMOS consumes no steady state power.
1-BIT MAGNITUDE COMPARATORDigital Comparator also called “Magnitude Comparator” is acombinational circuit that compares two numbers in which A andB are two inputs and three outputs A> , = , < and onlyone of the three outputs would be high accordingly if A is greaterthan or equal to or less than B. The truth table of 1-bit comparatoris shown in Table 1
SCHEMATIC DESIGN SIMULATIONSA Comparator has two inputs and three outputs which areA > B , A< B and A=B. The logic circuit of this comparatorcan be implemented with the help of XNOR gate, AND gatesand NOT gates. The logic for A=B requires XNOR gatewhile the logic for A >B and A< B requires AND and NOTgates. The basic logic diagram for Comparator with basicgates can be represented as shown below figure 3
Fig.3 Logic Level comparator
The Switch level Comparator consist of NMOS and PMOStransistors as shown in figure 4 and showing 1-bitComparator. Also the timing diagram is shown in fig. 5
Fig.4 Switch Level Comparator
Fig.5 Timing diagram of Switch Level Comparator
LAYOUT DISCUSSIONSThe schematic of 1-bit Comparator is designed. Using Microwindsoftware, the auto generated layout of 1-bit Comparator is createdwith 180nm foundary. The figure 6 represents the autogeneratedlayout. Layout is the general concept that describes thegeometrical representation of the circuits by the means of layers.Different logical layers is used by designers to generate thelayout.
Fig.6 Auto generated layout of the comparator
The Output waveform for Automatic generated layout is shown infigure 7
Fig.7 Output waveform for automatic generated layout
The representation of Semi-Custom Layout of the 1-bitComparator using nMOS, pMOS and its output waveform isshown in figure 8 and figure 9 respectively.
Fig.8 Semi-custom layout of the comparator
Fig.9 Output waveform for semi-custom layout
The performance of proposed 1-bit Comparator layout iscompared with semicustom approach. The performance interms of Area and Power is compared. Comparative analysisis shown in Table 2
Table 2: Comparative Analysis For Area And Power
Approach Area(μm2)
Power(mWatt)
Width(μm) Height(μm)
AutomaticGenerated
1446.5 0.176 73.8 19.6
Semi-Custom
855.4 0.163 31.8 26.9
In terms of area and power the Semi-Custom layout hasbetter performance among two design approaches. Area andPower graph representation of these design approach isshown below in figure 10 and Figure 11 respectively
Fig.10 Area shown between Automatic Generated and Semi-Custom layout
Fig11 Power shown between Automatic Generated and Semi-Custom layout
From the above graph we observed that there is a reduction inpower and Area for semi custom approach as compared toAutomatic generated layout.
CONCLUSIONAbove analysis conclude that this technique is very useful toreduce the effective area on a chip and power dissipation. In thispaper, we presented the analysis for layout of 1-bit comparatorusing auto generated and semi-custom technique and alsoexpressions were derived using karnaugh -map. Finally from thecomparative analysis it is clear that the Semi-Custom layout ismore efficient than auto generated in terms of power and area. Sothis design approach can be implemented where area and powerreduction is the main consideration.
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