Tutorial - Layout LVS & PEX with

CalibreCalibre

Adapted from CIC Full-Custom IC

Design Concepts (for WS)

Outline

• Verification by Layout Versus Schematic (LVS)

with Calibre Tool Setting

• Verification by Parasitic Extraction (PEX) with

Calibre Tool SettingCalibre Tool Setting

• NAND and NOR Layout with Sharing Drain and

Source

• Exercise

• LAB

Outline

• Verification by Layout Versus Schematic (LVS)

with Calibre Tool Setting

• Verification by Parasitic Extraction (PEX) with

Calibre Tool SettingCalibre Tool Setting

• NAND and NOR Layout with Sharing Drain and

Source

• Exercise

• LAB

Layout Versus Schematic

Design View

• Composer

Layout View

• Virtuoso• Virtuoso

• Lacker

Layout Netlist Layout Netlist

Verification

Results

Comparsion

Phase

Process Flow for LVSCompleted

Layout

Calibre LVS

Rule File Completed

Source

Correct Layout

Errors

Locate Errors

Layout Tool

Locate Errors

using

Calibre RVE &

Layout Tool

LVS Results

Database

ASCII

Report

Extracted

Netlist

Determine

Errors form

Report

Calibre Tool

Design Rule Check

Layout Versus Schematic

Parasitic Extraction using XCalibre

Results Viewing Environment

Invoked by Cadence Virtuoso

Calibre LVS Window & Rule Window

Specify the LVS rules file.

Indicate the LVS run directory.

• File : Contains pulldown menus that allow the user to create, open, save,

use recent runset or to exit the GUI.

• Transcript : Contains pulldown menus that allow the user to save as, echo the

transcript to another location and search the file.

• Setup : Contains pulldown menus that allow the user to select check

preference, setup the layout viewer and the icon to turn on/off

how tool tips.

Calibre LVS Input WindowRun Hierarchical or Flat mode

No service

• Inputs

– Specify the layout database including the type of file and primary cell.

– Indicate whether or not to import the layout database from the layout

viewer.

– Layout database type : GDSII

– Source Database Type : SPICE

Switch to Specify Cell Correspondence

Two difference way

• Hierarchical analysis requires the identification of corresponding cells

between the source and layout.

– LVS-H automatically matches cells in the source and layout with the same name when

invoked with the “Match cells by name(automatch)”

– Creating the hcells correspondence file

• In this tutorial we just use automatch, so be careful to check your layout &

source cells name.

Calibre LVS Output Window

Create SVDB Database

after finish LVS to watch

about errors information

• Outputs

– Specify the LVS report file.

– Indicate where the report will be written or view it upon completion

Calibre LVS Control Window

Know about server information

• Run Control

– Specify how the LVS run is to be executed.

– Run Single-Threaded or Multi-Threaded.

Calibre LVS Execution Window

Press the button and start run LVS.

• Transcript

– View the transcript for the current Calibre run.

• Run LVS

– Run Calibre based on the information provided by the user.

• Start RVE

– Start the result viewing environment.

Press the button and start run LVS.

If select before, it will open RVE

When LVS finish.

LVS Report File

ERRORS!!!!

Calibre RVE WindowFile Browser:

Display a tree

view of the input

and output files

Discrepancy Information Pane:

Display an excerpt from the

LVS report related to the

discrepancy.

Calibre RVE - Rule File

We assign in the

Calibre LVS Rule

Window .

Calibre RVE – Extraction Report

The Ectraction Results include Extraction Report.

Click here

Select detail

Highlight Errors

Click here

Select detail

More Detail Highlight Error

Know The True Error

• The Calibre RVE will hightlight all errors in

Cadence Virtuoso layout editor, but

sometimes they are not true error.

• Go through all errors and Debug some errors.• Go through all errors and Debug some errors.

• Run Calibre LVS again, you will find out some

errors which perplex you disappear.

Calibre LVS Report & Debug

Wonderful !!!!!!!!!!!

The smiling face is guarantees

expensively very much !

LVS Finish

The same

==Design

Outline

• Verification by Layout Versus Schematic (LVS)

with Calibre Tool Setting

• Verification by Parasitic Extraction (PEX) with

Calibre Tool SettingCalibre Tool Setting

• NAND and NOR Layout with Sharing Drain and

Source

• Exercise

• LAB

Process Flow for PEX

Completed

Layout

Calibre PEX

Rule File Completed

Source

Modify Layout

Simulation

Calibre PEX

PEX Results

Database

ASCII

Report

Extracted

Netlist

Meet

spec?

To TapeoutYES

NO

Post-Layout Simulation

• The netlist of SPICE/CDL format that includes

parasitic element can be obtained after the

Dracula LPE/PRE (Layout Parameter

Extraction). It can be used for post simulation Extraction). It can be used for post simulation

by circuit simulator, such as SPICE.

• Add simulation control and input stimulus for

final simulation(Post-Layout Simulation).

Calibre Tool

Design Rule Check

Layout Versus Schematic

Parasitic Extraction using XCalibre

Results Viewing Environment

Invoked by Cadence Virtuoso

Calibre PEX Window & Rule Window

Specify the PEX rules file.

Indicate the PEX run directory.

• File : Contains pulldown menus that allow the user to create, open, save,

use recent runset or to exit the GUI.

• Transcript : Contains pulldown menus that allow the user to save as, echo the

transcript to another location and search the file.

• Setup : Contains pulldown menus that allow the user to select check

preference, setup the layout viewer and the icon to turn on/off

how tool tips.

PEX Run Directory

PEX Run Directory need

these two file to execution!!!

Calibre PEX Input WindowTick this button will

enable schematic

capture to generate

new netlist

• Inputs

– Specify the layout database including the type of file and primary cell.

– Indicate whether or not to import the layout database from the layout

viewer.

– Layout database type : GDSII

– Source Database Type : SPICE

Choice source

netlist here

Choice GDS

file here

Switch to Specify Cell Correspondence

Two difference way

• Hierarchical analysis requires the identification of corresponding cells

between the source and layout.

– LVS-H automatically matches cells in the source and layout with the same name when

invoked with the “Match cells by name(automatch)”

– Creating the hcells correspondence file

• In this tutorial we just use automatch, so be careful to check your layout &

source cells name.

Hierarchical Extraction

Calibre PEX Output Window

Output main

file name

Select nets extraction

These nets

don’t extraction

Calibre PEX Control Window

Know about server information

• Run Control

– Specify how the PEX run is to be executed.

– Run Single-Threaded or Multi-Threaded.

Calibre PEX Execution Window

No ERRORS !!

Excellent!

• Transcript

– View the transcript for the current Calibre run.

• Run PEX

– Run Calibre based on the information provided by the user.

• Start RVE

– Start the result viewing environment.

PEX Result

Remember Subckt Sequence!

PEX Result Files

After finish PEX execution

Three files be produced.

inv_pex.sp.INV.pxi & inv_pex.sp.pex

Create a New File To Simulation

Be Careful→ Subckt Sequence!

Using PEX Result Subckt

Run HSPICE & Use Scope

Finish!

Load HSPICE

Watch the signal

Post-Simulation inverter Result

Outline

• Verification by Layout Versus Schematic (LVS)

with Calibre Tool Setting

• Verification by Parasitic Extraction (PEX) with

Calibre Tool SettingCalibre Tool Setting

• NAND and NOR Layout with Sharing Drain and

Source

• Exercise

• LAB

Sharing Drain/Sourcemetal

N+/P+ IMP

poly

N+/P+ N+/P+N+/P+

contact

P-

Sharing drain and source

SiO2

N+/P+ IMP

metalpoly

N+/P+ N+/P+N+/P+

contact

P-

Reduce the parasitic

resistance

SiO2

NAND gate Schematic & Layout

vdd vdd

vo

gnd

vi1

vi2

vo

NOR gate Schematic and Layout

vi1

vi2

vdd

vi2

vo

gnd gnd

Outline

• Verification by Layout Versus Schematic (LVS)

with Calibre Tool Setting

• Verification by Parasitic Extraction (PEX) with

Calibre Tool SettingCalibre Tool Setting

• NAND and NOR Layout with Sharing Drain and

Source

• Exercise

• LAB

Exercise• Try LVS and PEX with last LAB(three inverter).

• Use HSPICE to Post_simulation.

• Look different between Pre_simulation and Post_simulation .

• Input constrain :

– vi vi gnd! pwl 0 0 9.9n 0 10n 1.8 19.9n 1.8 20n 0 R

• If we want to measure the net, it will need add label on that net in • If we want to measure the net, it will need add label on that net in

layout view.

– For example: we need add label on net in layout view, so we can

use measre option to calculate what information we want.

Delay with Pre_sim & Post_sim

Pre-simulation :

Delay increased.

Post-simulation :

Delay increased.

Because after

layout complete

real circuit can

be calculation.

Outline

• Verification by Layout Versus Schematic (LVS)

with Calibre Tool Setting

• Verification by Parasitic Extraction (PEX) with

Calibre Tool SettingCalibre Tool Setting

• NAND and NOR Layout with Sharing Drain and

Source

• Exercise

• LAB

LAB(Due date is 11/17 11:00PM)

• Draw the layout view of NAND and NOR gate.

• Use DRC , LVS , and PEX to check the circuit is

working.

• Use HSPICE to process Pre_sim and Post_sim.• Use HSPICE to process Pre_sim and Post_sim.

• In word file, if you write more detail about

your LAB work , you can get higher grade in

this LAB.

What do you need to submit?

Directory name File in the directory

nand schematic/, symbol/, layout/

nor schematic/, symbol/, layout/

nand_sim pre_nand_sim.sp , pre_nand_sim.lis ,

post_nand_sim.sp (include file which will be

produced after PEX verification ) , produced after PEX verification ) ,

post_nand_sim.lis

nor_sim pre_nor_sim.sp , pre_nor_sim.lis ,

post_nor_sim.sp (include file which will be

produced after PEX verification ) ,

post_nor_sim.lis

word file

(學號_說明文件.doc)

Draw the schematic , symbol, and layout.

Run Pre_sim and Post_sim compare result.

Run DRC, LVS, PEX process (printscreen) .

整個包在壓縮檔：學號_姓名.rar

LAB constrain

• Input constrain:

– vdd vdd! gnd! 1.8

– vi1 vi1 gnd! pwl 0 0 2.2u 0 2.4u 1.8 4.6u 1.8 4.8u 0 R

– vi2 vi2 gnd! pwl 0 0 1u 0 1.2u 1.8 2.2u 1.8 2.4u 0 R– vi2 vi2 gnd! pwl 0 0 1u 0 1.2u 1.8 2.2u 1.8 2.4u 0 R

• Measure

– rise time of vo : 0.1*1.8~0.9*1.8 rise=1

– Fall time of vo : 0.9*1.8~0.1*1.8 fall=1

– AVG_power

Reference

• CIC訓練課程(A003)

– Physical Verification with Calibre

Training Manual

• CIC訓練課程(A004)• CIC訓練課程(A004)

– Full-Custom IC Design Concepts(for WS)

Training Manual