LOGICAL DESIGN 2

Course titular:DUMITRAŞCU Eugen

SYNTHESIS OF FSM

CHAPTER 7

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CONTENT

Classical synthesis steps of SLC Examples of classical synthesis of

FSM FSM synthesis with registers FSM synthesis using VHDL

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CLASSICAL SYNTHESIS STEPS OF SLCS1: Starting from verbal description (informal) of the functions

performed by the synthesis scheme, it is generated its block diagram (scheme). In the block diagram are all external control signals, clock signal which controls the synchronous evolution of the scheme and output signals. Each signal has a unique name (mnemonic) to suggest more clearly the significance of the signal. For all signals will specify, through graphical and names conventions, the logic activation of the signal.

S2: Based on the verbal description of the function realised by the scheme one goes to the formal description of the evolution using the states evolution diagram. It is the designer’s task to decide whether to use the Mealy or the Moore model. In certain situations, for instance in case of counters, the natural model is the Moore model. In other situations, both models can be considered and after the simulation of the functioning and the comparison of the results, the convenient solution will be chosen. The emphasized states have symbolic names.

S3: The states evolution diagram is transformed in a state table.

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CLASSICAL SYNTHESIS STEPS OF SLCS4: Trying to reduce the number of states. If the number

of states has been reduces, the state table from the preceding step is replaced with the state table of the minimal reduced machine equivalent to the initial sequential machine.

S5: Determine the minimum number of state variables required for encoding binary states with relationship:

where: N – number of statesn – minimum number of state variables

S6: It is realized assigning of the states, meaning that to each symbolic state it is allocated a unique combination of the states variables values. All assigned combinations will have the same length (at least n bits).

S7: It is generated the states transition table and the output table by replacing the symbolic states with the binary combinations of the state variables assigned at the preceding step.

Nn 2log

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CLASSICAL SYNTHESIS STEPS OF SLCS8: The output table is a truth table from which one can

synthesize the output functions using any of the known methods.

S9: It is chosen the type of the flip-flops used to implement the scheme.

S10: Using the state transition table and the excitation table for the chosen type of flip-flop, it is generated the scheme’s excitation table. This table is a truth table from which there are synthesized the scheme’s excitation functions using one of the known methods.Utilisation of D type flip-flops eliminates this stage becausein this case the excitation function of each flip-flop isidentical to the function representing the next state. Inother words the state transition table is the excitationfunction table.

S11: It is drawn the synthesized SLC.

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CLASSICAL SYNTHESIS STEPS OF SLCS12: It is analysed the obtained scheme in the state space in

order to emphasize possible design flaws or anomalies in the synthesized scheme functioning. If necessary, the synthesis process is started again from one of the previous stages. In case there are detected stages or cycles that block the system, one can introduce an asynchronous initialisation signal even if it is not specified in the initial design or modify the excitation functions to avoid such situations.

S13: There are chosen from catalogues the components needed for the implementation of the scheme.

S14: It is performed the simulation of the scheme using a clock signal with a frequency equal to the working frequency of the real scheme. The simulation can emphasize more subtle anomalies provoked by the delays in signal propagation. Some of the anomalies detected at this step may necessitate choosing other components for the implementation or even redoing the synthesis by modifying the states assignment or choosing a different synthesis method.

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CLASSICAL SYNTHESIS STEPS OF SLCAssigning states

The assignment of states means the association by designer of a unique binary combinations of each symbolic state from a sequential machines.

The assignment process is a artificial process and there is infinite possible assignments, provided that two different states are assigned two different binary combinations.

The assignment process is used, as a fundamental working hypothesis, encoding all states with binary combinations with the same length.

Next will be considered two methods commonly used to assign states.

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CLASSICAL SYNTHESIS STEPS OF SLCa) Assigning with minimum length encoding Assuming that the sequential machine has N states, will be

required n state variables so that the number of binary combinations is at least equal with N, so

2n Nnlog(2)log(N) nlog2(N)

Usually choose the minimum value:n= log2(N)

Example: It is considered a synchronous SM (state machine) with N=3 states, marked A,B,C. For encoding the states will be required n=log2(3) =2 state variables y1y2 noted.

11 is a redundant combination.

State y1 y2

A 0 0

B 0 1

C 1 0

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CLASSICAL SYNTHESIS STEPS OF SLCSpecial assignments In certain situations can be used other encoding with

minimum length or not, for example Gray or Johnsonencoding.

Example: If a sequential machine has 8 states, the minimum number of state variables required for coding is log2(8)=3. In this case, you can use a 3-bit Gray encoding or 4-bit Johnson encoding.

Gray encoding Johnson encoding

y2 y1 y0 y3 y2 y1 y0

A 0 0 0 0 0 0 0

B 0 0 1 0 0 0 1

C 0 1 1 0 0 1 1

D 0 1 0 0 1 1 1

E 1 1 0 1 1 1 1

F 1 1 1 1 1 1 0

G 1 0 1 1 1 0 0

H 1 0 0 1 0 0 0

State

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CLASSICAL SYNTHESIS STEPS OF SLCb) ONE-HOT assignment method ONE-HOT assignment method called full decoding

method of states differs fundamentally from previous method in that the number of states is equal to the number of state variables.

In other words, each state corresponds a state variable. Because at a time a SM may be located in one state, it

results immediately that on each moment must be active one state variable.

If we assume that state variables are active on high level, means that each combination assigned to contain exactly one 1.

Example:A

CD

BE

INIT#

state A B C D E

A 1 0 0 0 0

B 0 1 0 0 0

C 0 0 1 0 0

D 0 0 0 1 0

E 0 0 0 0 1

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CONTENT

Classical synthesis steps of SLC Examples of classical synthesis of

FSM FSM synthesis with registers FSM synthesis using VHDL

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

Example: It is considered a dynamic pattern recognizer (DPR) that signals at the output via logic 0 every time it detects the sequence 10110 in the series of bits from the input. The scheme has an input Clear for asynchronous initialisation signal that is active low.It will consider both Mealy and Moore variant.

Mealy model

S0 S1 S2 S4S31/1

0/1

0/1 1/11/1

1/1 0/1

1/1

0/0IN IT#

0/1

DPR

S

CLKCLOCK

E

IN IT#

Clear

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

1 110

1 1xx

1 1xx

1 1xx

Sy2y1y0

00 101101

00

10

11

01

0 0xx

0 0xx

0 1xx

0 0xx

Sy2y1y0

00 101101

00

10

11

01

0 001

1 0xx

x xxx

x xxx

Sy2y1y0

00 101101

00

10

11

01

E J1J2

x xxx

x xxx

0 1xx

1 0xx

Sy2y1y0

00 101101

00

10

11

01

0 110

x xxx

x xxx

0 1xx

Sy2y1y0

00 101101

00

10

11

01

x xxx

1 0xx

1 1xx

x xxx

Sy2y1y0

00 101101

00

10

11

01

K1 K0J0

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

State-space analysis – Mealy model

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

Moore model

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

State-space analysis – Moore model

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

state S0 S1 S2 S3 S4 S5

S0 1 0 0 0 0 0

S1 0 1 0 0 0 0

S2 0 0 1 0 0 0

S3 0 0 0 1 0 0

S4 0 0 0 0 1 0

S5 0 0 0 0 0 1

ONE-HOT assignment We will resume the previous example (Moore model) and we

summarize scheme using ONE-HOT assignment as in the table below.

For synthesis are used D-type flip-flops are used as connected in the next scheme.

Note! At activation for initialization signal, the S0 flip-flop must go to state 1 becomes active after the initialization. Other flip-flops passes in the state 0.

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EXAMPLES OF CLASSICAL SYNTHESIS OF FSM

Excitation and output functions are obtained directly from the diagram of the evolution of SM.

S4SD5

S3SD4

S5SS2SD3

S3SS1SD2

S4SS1SS0SD1

S5SS2SS0SD0

S5E

INIT#

S R R R R

CLK CLKCLKCLKCLK

D Q D QD QD QD QD0 D4D3D2D1

S4S3S2S1S0

CLOCK

R

CLK

D Q

S5

D5

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CONTENT Classical synthesis steps of SLC Examples of classical synthesis of

FSM FSM synthesis with registers FSM synthesis using VHDL

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FSM SYNTHESIS WITH REGISTERS

CLC

parallel-parallel register

k

x(t)m n

z(t)

INIT

k

CLOCK

shift register

CLC

SIRS

INIT

CLOCK

x(t)z(t)

y(t)

Design variants with registers

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FSM SYNTHESIS WITH REGISTERS

74LS194 register - states evolution

0000 011010011010

0101

1100

0011

1111

1110

1101

1011

0111

1000

0100

0010

0001

000

0 0

1

1 1

10

0

0

1

0

0

1

1

10 0

1

1

00

11

1 1

1

0

1

0

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FSM SYNTHESIS WITH REGISTERSExample: A Johnson counter modulo 8 (with 8 states) is to be

synthesized using one 74LS194 register.

0000 011010011010

0101

1100

0011

1111

1110

1101

1011

0111

1000

0100

0010

0001

000

0 0

1

1 1

10

0

0

1

0

0

1

1

10 0

1

1

00

11

1 1

10

0

1

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FSM SYNTHESIS WITH REGISTERS

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FSM SYNTHESIS WITH REGISTERS

74HCT194

Q0 Q3Q2Q1

D0 D3D2D1

S1

SR

S0

0

1

INIT#

0

CLEAR

CLKCLOCK

y0 y3y2y1

SI

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FSM SYNTHESIS WITH REGISTERS

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CONTENT Classical synthesis steps of SLC Examples of classical synthesis of

FSM FSM synthesis with registers FSM synthesis using VHDL

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FSM SYNTHESIS USING VHDLIt will synthesis a dynamic pattern recognizer that indicates by

logic 1 at oRecunoscut output every time is detected the sequence 010101 in the bit string from iD input.

Mealy Model

S0 S5S4S3S2S10/0 0/01/00/01/0

1/0

iINITL

0/0 1/0

0/0

1/0

1/1

0/0

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FSM SYNTHESIS USING VHDL

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FSM SYNTHESIS USING VHDL

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FSM SYNTHESIS USING VHDLIt will synthesis a dynamic pattern recognizer that indicates by

logic 1 at oRecunoscut output every time is detected the sequence 010101 in the bit string from iD input.

Moore Model

0 0101

1/0

iINITL

0 1

0

1

0

0

1

1

S0 S2 S5S4S3S1 S60 0 0 000 1

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FSM SYNTHESIS USING VHDL

Var. 1

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FSM SYNTHESIS USING VHDL

Var. 1

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FSM SYNTHESIS USING VHDL

Var. 2

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FSM SYNTHESIS USING VHDL

Var. 2

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FSM SYNTHESIS USING VHDL

Var. 2One-Hot assignment

QUESTIONS?