doc.: IEEE 802.11-03/0865r0

Submission

LDPC FEC forIEEE 802.11nApplications

Eric JacobsenIntel Labs

Communications Technology LaboratoryNovember 10, 2003

November 2003

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doc.: IEEE 802.11-03/0865r0

Submission

Agenda

• Background – why LDPCs?• Fitting LDPCs to WLAN• Details of candidate code• Performance and use of candidate code• Complexity analysis• Summary

November 2003

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Candidate Iterative FECs• Turbo Codes (PCCC or SCCC)

– High complexity– Poor performance with short blocks– IP Issues

• Turbo Product Codes– Medium Complexity– Best performance at R ~= 0.8– Poor performance with short blocks– Possible IP issues

• Low Density Parity Check Codes (LDPCs)– Invented in 1962 – No basic IP!– Potential for low complexity – constituent codes are Parity Check

relationships– Extremely good performance with long blocks (C-0.0045dB!)– Very good performance with short blocks (Lin)– Eliminate channel interleaver

November 2003

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Submission

LDPC Codes solve several problems• Close the large gap between current and theoretical

performance– Only known solution for good performance with small

block sizes• Enable Adaptive Bit Loading by eliminating the

channel bit interleaver– LDPCs incorporate the required randomization into the

code – These are the only known codes that do this!– This also provides a significant complexity reduction

• Offsets complexity of code– Decoupling the FEC and modulation increases

flexibility

November 2003

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Submission

Low Density Parity Check FEC• Iterative decoding of simple parity check codes• Published examples of good performance with short blocks

– Kou, Lin, Fossorier, Trans IT, Nov. 2001• Near-capacity performance with long blocks

– Very near! - Chung, et al, “On the design of low-density parity-check codes within 0.0045dB of the Shannon limit”, IEEE Comm. Lett., Feb. 2001

• Complexity fears, especially in encoder• Implementation Challenges

– Many options wrt decoding algorithms, architectures, techniques

November 2003

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Submission

LDPC Bipartite (Tanner) Graph

This is an example bipartite graph for an irregular LDPC code.This is an example bipartite graph for an irregular LDPC code.

Check NodesCheck Nodes

EdgesEdges

Variable NodesVariable Nodes(Codeword bits)(Codeword bits)

November 2003

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doc.: IEEE 802.11-03/0865r0

Submission

BICM System with LDPC

Receiver FFT Slicer De-Interleaver

DemodulatedDemodulatedConstellationConstellation

SymbolsSymbols

DetectedDetectedCoded BitsCoded Bits

De-InterleavedDe-InterleavedCoded BitsCoded Bits

Corrected BitsCorrected Bits

The nature of the LDPC calls into question whetherThe nature of the LDPC calls into question whetherthe deinterleaver produces any benefit or justthe deinterleaver produces any benefit or justdefines a different LDPC code. defines a different LDPC code.

November 2003

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doc.: IEEE 802.11-03/0865r0

Submission

Direct Coding with LDPC

Receiver FFT Slicer

DemodulatedDemodulatedConstellationConstellation

SymbolsSymbols DetectedDetectedCoded BitsCoded Bits

Corrected BitsCorrected Bits

Since the interleaver merely permutes the orderSince the interleaver merely permutes the orderof the rows of the parity check matrix, it can beof the rows of the parity check matrix, it can bedeleted and its effects taken into account indeleted and its effects taken into account inthe code design. the code design.

A system withA system withLDPC FEC shouldLDPC FEC shouldprovide superiorprovide superiorperformance withperformance withreasonable simplicity. Sincereasonable simplicity. Sincethe interleaver can be excludedthe interleaver can be excludedthe complexity drops further.the complexity drops further.

November 2003

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Submission

191-bit block results, Kou

Capacity~1.2dB

forR = 0.69

November 2003

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doc.: IEEE 802.11-03/0865r0

Submission

Large Block LDPCs in FadingFor large block sizes,For large block sizes,In this case 10In this case 1055 and 10 and 1066,,LDPCs perform LDPCs perform extremely close to extremely close to capacity.capacity.

For a code with R = ½ in For a code with R = ½ in AWGN, C = ~ 1.2 dB AWGN, C = ~ 1.2 dB EEbb/N/Noo (BICO). (BICO).

November 2003

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Submission

Candidate LDPC Code• (2000, 1600) code, R = 0.8

– Long enough for good performance, short enough to implement– BER in AWGN is <1.5dB from Capacity at Pe = 10-5

• Column weights are controlled by the code design• Four edges per information bit, two per parity bit

– Last parity bit has one edge• 18 edges per check node (regular in H1)• Total of 7199 edges• Simplified Encoder• BCJR or Min-Sum decoding algorithm

– Min-Sum costs 0.3dB in peformance, cuts gate count

November 2003

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Submission

Performance in AWGN

2 3 4 5 6 7 81 10 8

1 10 7

1 10 6

1 10 5

1 10 4

1 10 3

0.01

0.1

UncodedR=3/4, ViterbiR=7/8, ViterbiR=0.8, LDPC

Eb/No

BER

2.044

Capacity for R = 0.8Capacity for R = 0.8is 2.044dB, shownis 2.044dB, shownwith a verticalwith a verticaldashed red line.dashed red line.

At PAt Pee = 10 = 10-5-5 the theLDPC code isLDPC code is<1.5dB from<1.5dB fromCapacity.Capacity.

November 2003

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Submission

LDPC, ABL in fadingThese results are inChannel Model D, 50nsdelay spread.

The Viterbi-UBL resultsare essentially an802.11a referencesystem.

The LDPC-UBL resultsuse a fixed code rate ofR = 0.8.

-5 0 5 10 15 20 25 300

10

20

30

40

50

LDPC-UBL, (No Puncturing), rms = 50 ns, 50 Iterations

Thro

ughp

ut (M

bps)

BPSKQPSK16-QAM64-QAM

-5 0 5 10 15 20 25 3010

-4

10-3

10-2

10-1

100

SNR (dB)

PE

R

November 2003

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Submission

LDPC, ABL in fadingThese results are inChannel Model D, 50nsdelay spread.

The Viterbi-ABL resultsuse puncturing andmodulations BPSK,QPSK, 16-QAM and64-QAM, with variablecode rate.

The LDPC-ABL resultsuse puncturing, QPSK,16-QAM, and 64-QAM,with a fixed code rate ofR = 0.8. The throughputcurve drops off at lowSNR because BPSK isnot part of the adaptationmenu.

November 2003

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Submission

LDPC, ABL in fadingThese results are inChannel Model D, 50nsdelay spread.

The Viterbi-ABL resultsuse puncturing andmodulations BPSK,QPSK, 16-QAM and64-QAM, with variablecode rate.

The LDPC-ABL resultsuse puncturing, QPSK,16-QAM, and 64-QAM,with a fixed code rate ofR = 0.8. The throughputcurve drops off at lowSNR because BPSK isnot part of the adaptationmenu.

November 2003

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Submission

Selected LDPC Code Use• Long packets are encoded by concatenating

codewords– 1500 byte packet + overhead is ~8 codewords

• Short packets are accommodated with code shortening– Parity stays constant, information field shortened– Short packets consume the minority of airtime, so code

rate reduction carries little penalty– Increase in reliability for short packets comes at low cost

November 2003

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Submission

Dartmouth Usage Statistics

1500 byte packets are the driving long packet type.1500 byte packets are the driving long packet type.

November 2003

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doc.: IEEE 802.11-03/0865r0

Submission

Packet size accommodation1600 bit data field 400 bit

parity

2000 bit codeword2000 bit codeword

Long packets use concatenated codewordsLong packets use concatenated codewords

N bit data field 400 bitparity1600-N bit zero pad1600-N bit zero pad

Short blocks use shortened codewords.Short blocks use shortened codewords.The zero pad is not transmitted.The zero pad is not transmitted.

November 2003

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Submission

Comparative Performance

(AWGN)

LDPC (2000, 1600) r = 4/5 vs. K7

convolutional code r = 3/4.

November 2003

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Submission

LDPC Shortened Packet Performance vs Eb/No

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

1 2 3 4 5

Eb/No

PER

1600/501600/8800/50800/8400/50400/8

Shown are theShown are theeffects ofeffects ofshortening theshortening thecode from 1600code from 1600information bitsinformation bitsto 800 and 400to 800 and 400bits (code ratesbits (code ratesof R = 2/3 andof R = 2/3 andR = ½ ,R = ½ ,respectively.respectively.

Performance forPerformance forboth 50 and 8both 50 and 8iterations are shown to verify performance for the shortened codes.iterations are shown to verify performance for the shortened codes.Allowing the code rate to drop with packet size maintains power efficiencyAllowing the code rate to drop with packet size maintains power efficiencyfor short packets.for short packets.

November 2003

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Submission

LDPC Shortened Packet Performance vs SNR

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

-2 0 2 4

SNR

PER

1600/501600/8800/50800/8400/50400/8

Shortened codeShortened codePerformancePerformanceIs shown vsIs shown vsSNR.SNR.

The gain fromThe gain fromshortening theshortening thecodes can becodes can beused toused toincrease rangeincrease rangeif also appliedif also appliedto longerto longerpackets bypackets byconcatenation.concatenation.

November 2003

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Submission

Iteration Management• LDPCs are iteratively decoded

– The number of iterations affects the code performance– The number of iterations also affects the complexity

November 2003

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Submission

Mother Code Iteration Study

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

2 3 4 5 6

Eb/No

PER

1600-bit packets for all cases.1600-bit packets for all cases.

4455

88

667799

101011, 1211, 12

5050 Viterbi, R = 3/4Viterbi, R = 3/4

Viterbi, R = 0.8Viterbi, R = 0.8(estimated)(estimated)

November 2003

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Complexity Tradeoffs• Gate and memory complexity decrease with

increasing clock rate– Serialization of processing allows gate and memory reuse

• Gate complexity increases with number of iterations– Memory stays constant

• BCJR more than 2x gate complexity over Min-Sum kernel– 0.3dB performance improvement– If memory complexity drives, then BCJR is a good

option

November 2003

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Submission

Latency Drives• For any block code for 802.11 the MAC latency

requirements will drive• 1600 bits at 240 Mbps takes 6.6us to receive• SIFS budget drives, so for worst-case we assume

a 1us budget allocated to the FEC block

November 2003

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Analysis Assumptions

• 240 Mbps target – Should encompass most modes

• Eight iterations• Two processing clocks per information bit

– Keep duty cycle low, reduces power consumption?

• BCJR algorithm

November 2003

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Complexity Estimates• Gates

– 1us = 240 cycles at 240 MHz– Computation gates, BCJR ~= 124k gates– Additional control, sums, etc., ~40k gates– Estimated BCJR total gate count ~164k gates– Estimated Min-Sum total gate count ~98k gates

• Memory– Scratchpad, computation, buffering ~= 120k bits– Code address ROM ~= 93.6k bits

November 2003

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Submission

LDPC Decoder Area vs Latency

0.80.85

0.90.95

11.05

1.11.15

1.21.25

1.3

1 2 3 4 5 6

Latency

BCJR Area

Min-Sum Area

Shown is the estimated normalized die area, relative to a target reference,Shown is the estimated normalized die area, relative to a target reference,as a function of decoding latency. This takes into account only the reductionas a function of decoding latency. This takes into account only the reductionin gates by allowing the reuse of the maxx() hardware, and does notin gates by allowing the reuse of the maxx() hardware, and does notconsider that the scratchpad memory size could also be reduced.consider that the scratchpad memory size could also be reduced.

BCJR reference caseBCJR reference case

November 2003

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Submission

Encoder Complexity

Guv

]|[]|[ 21tt HHuuPuuGuv

DuHuHuHuv ttt

11|]|[ 121

The generic block encoder definition. A typical LDPCgenerator matrix, G, is high density for a low density paritycheck matrix H.

By carefully partitioning G, the lowdensity H matrix may be used andseparated into two portions, H1

and H2, where H2 takes the low-density form shown. The inversetranspose of H2 can then beimplemented as a differentialencoder.

November 2003

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Encoder Implementation

The final encoder structure is as shown above. The data vector, u,is the systematic portion of the codeword, v. The parity bits, p, aregenerated from the low-density matrix H1 and the differential encoder 1/1+D.

November 2003

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Complexity Summary• ~164k gates computation and control with BCJR• ~98k gates computation and control with Min-Sum

– This is to achieve 1us decode time. Gate counts drop dramatically as latency is allowed to increase.

• Memory estimate is 120k bits of RAM and 93.6k bits of control ROM

• This is a conservative budgetary estimate. Other decoding algorithms or trick implementations may yield different results.

November 2003

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Summary• This LDPC code by itself provides 2-3+dB of

gain – Implementation is practical – much flexibility in

approach– Less than 1.5dB from AWGN Capacity at Pe = 10-5

with a 1600-bit data block and R = 0.8• Flexible in code rate and data block size

– Shortening schemes allow no restrictions on data block size

– Observing OFDM symbol boundaries is not required– Eliminates Channel Interleaver

• Decouples FEC from modulation, MIMO/SISO, higher-order modulation, etc.

doc.: IEEE 802.11-03/0865r0

Submission

Backup

November 2003

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Submission

Partial Reference List• TCM

– G. Ungerboeck, “Channel Coding with Multilevel/Phase Signals”, IEEE Trans. IT, Vol. IT-28, No. 1, January, 1982

• BICM– G. Caire, G. Taricco, and E. Biglieri, “Bit-Interleaved Coded Modulation”, IEEE

Trans. On IT, May, 1998• LDPC

– Ryan, W., “An Introduction to Low Density Parity Check Codes”, UCLA Short Course Notes, April, 2001

– Kou, Lin, Fossorier, “Low Density Parity Check Codes Based on Finite Geometries: A Rediscovery and New Results”, IEEE Transactions on Information Theory, Vol. 47, No. 7, November 2001

– R. Gallager, “Low-density parity-check codes”, IRE Trans. IT, Jan. 1962– Chung, et al, “On the design of low-density parity-check codes within 0.0045dB of

the Shannon limit”, IEEE Comm. Lett., Feb. 2001– J. Hou, P. Siegel, and L. Milstein, “Performance Analysis and Code Optimisation for

Low Density Parity-Check Codes on Rayleigh Fading Channels” IEEE JSAC, Vol. 19, No. 5, May, 2001

– L. Van der Perre, S. Thoen, P. Vandenameele, B. Gyselinckx, and M. Engels, “Adaptive loading strategy for a high speed OFDM-based WLAN”, Globecomm 98

– Numerous articles on recent developments LDPCs, IEEE Trans. On IT, Feb. 2001

November 2003

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Submission

Performance comparison around 1.5 bit/s/Hz

DVBS+30%

Effic

ienc

yHughes NSHughes NS

(LDPC)(LDPC)SpaceBridgeSpaceBridge

(PCCC)(PCCC)

1.35

1.4

1.45

1.5

1.55

1.6

3.75 3.95 4.15 4.35 4.55 4.75 4.95 5.15 5.35 5.55 5.75 5.95 6.15 6.35

C/N

Bit/

s/H

z

Turbo Concept A

Turbo Concept B

ComTech

Philips

Conexant

Space Bridge LowComplexity A

Space Bridge LowComplexity B

Space Bridge HighComplexity A

Space Bridge HighComplexity B

STM

ESA

Hughes

DVB-DSNG(ImplementationFree)DVB-DSNG (30%increment inspectral ef f iciency)

C/N

DVBS