Department of Computer EngineeringTallinn University of Technology

Estonia

Department of Computer Engineeringati.ttu.ee

Learning-by-gaming in HW/SW codesign

Vadim Pesonen, Maksim Gorev, Kalle Tammemäe

EWME 2010-05-11

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Learning-by-gaming in HW/SW codesign

Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements

EWME 2010-05-11

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Introduction and course objectives

Modelling languages and tools Design space Estimate and analyze to partition Predefined IP cores Accomplish team tasks

Students must be aware of/be able to:

Laboratory works for HW/SW codesign course Overcome complexity with entertaining practical works Learn by designing games

EWME 2010-05-11

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Agenda

Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements

EWME 2010-05-11

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Planning the course and practical works

English as the primary language Materials available online Affordable development boards

Consider students’ background knowledge Introduction to HDLs VLSI synthesis Digital system design System-on-a-chip design Numerous projects

EWME 2010-05-11

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Agenda

Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements

EWME 2010-05-11

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Laboratory work assignments

4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design

• Various HW/SW ratios

EWME 2010-05-11

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Laboratory work assignments

4 levels in ascending complexity order Introductory

Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design

• Several HW/SW partitions

EWME 2010-05-11

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Laboratory work assignments

4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog

Intermediate – graphical application Advanced – complex design

• Various HW/SW ratios

EWME 2010-05-11

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Laboratory work assignments

4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application

• Xilinx PicoBlaze soft-core processor

Advanced – complex design• Various HW/SW ratios

EWME 2010-05-11

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Laboratory work assignments

4 levels in ascending complexity order Introductory Beginner – simple HW design in VHDL/Verilog Intermediate – graphical application Advanced – complex design

• Various HW/SW ratios

EWME 2010-05-11

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Agenda

Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements

EWME 2010-05-11

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Obtained results

+ Good course objective coverage

+ Generally positive students’ reaction

+ Strong team spirit during practical works

– Insufficient practical work guides

– Complexity gap between assignments

- 1/3 failed the laboratory tasks

– Used soft-core processor insufficient

EWME 2010-05-11

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Agenda

Introduction and course objectives Planning the course and practical works Laboratory work assignments Obtained results Future enhancements

EWME 2010-05-11

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Future enhancements

Address negative feedback Employ more powerful soft-core processors

Xilinx MicroBlaze OpenRISC Coffee RISC core

Extend board usage Different FPGA platforms

EWME 2010-05-11