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6.976
High Speed Communication Circuits and Systems
Lecture 1
Overview of Course
Michael Perrott
Massachusetts Institute of Technology
Copyright 2003 by Michael H. Perrott
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M.H. Perrott MIT OCW
Wireless Systems
Direct conversion architecture
sin(wot)
90o
D/A
D/A
DigitalProcessing
Block
Digital
Processing
Block
sin(wot)
90o
A/D
A/D
Transmit IC Receive IC
LNA
PowerAmp
Transmitter issues
- Meeting the spectral mask (LO phase noise & feedthrough,quadrature accuracy), D/A accuracy, power amp linearity
Receiver Issues
- Meeting SNR (Noise figure, blocking performance, channelselectivity, LO phase noise, A/D nonlinearity and noise),selectivity (filtering), and emission requirements
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Future Goals
Low cost, low power, and small area solutions
- New architectures and circuits! Increased spectral efficiency
- Example: GSM cellphones (GMSK) to 8-PSK (Edge) Requires a linear power amplifier!
Increased data rates
- Example: 802.11b (11 Mb/s) to 802.11a (> 50 Mb/s) GFSK modulation changes to OFDM modulation
Higher carrier frequencies
- 802.11b (2.5 GHz) to 802.11a (5 GHz) to ? (60 GHz) New modulation formats
- GMSK, CDMA, OFDM, pulse position modulation New application areas
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High Speed Data Links
A common architecture
DEMUX
DigitalProcessing
Block
Receive IC
AmpClock
and Data
Recovery
Clock
Distribution
10 Gb/sData Link
MUX Driver
DigitalProcessing
Block
Transmit IC
Clock Generation
Transmitter Issues
- Intersymbol interference (limited bandwidth of ICamplifiers, packaging), clock jitter, power, area
Receiver Issue
- Intersymbol interference (same as above), jitter fromclock and data recovery, power, area
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This Class
Circuit AND system focus
- Knowing circuit design is not enough- Knowing system theory is not enough
Circuit stuff
- RF issues: transmission lines and impedance transformers- High speed design techniques- Basic building blocks: amplifiers, mixers, VCOs, digitalcomponents- Nonidealities: noise and nonlinearity
System stuff- Macromodeling and simulation- Wireless and high speed data link principles
-System level blocks: PLLs, CDRs, transceivers
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The Goal Design at Circuit/System Level
1. Design architecture with analytical models May require new circuits guess what they look like
2. Verify architectural ideas by simulating with idealmacro-models of circuit blocks
Guess macro-models for new circuits
3. Add known non-idealities of circuit blocks
(nonlinearity, noise, offsets, etc.) Go back to 1. if the architecture breaks!
4. Design circuit blocks and get better macro-models
Go back to 1. if you cant build the circuit! Go back to 1. if the architecture breaks!
5. Verify as much of system as possible with SPICE
6.Layout, extract, verify
Do this soon for high speed systems - iteration likely!
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Key System Level Simulation Needs
You need a fast simulator
- To design new things well, you must be able to iterate- The faster the simulation, the faster you can iterate
You need to be able to add non-idealities in a
controlled manner
- Fundamental issues with architectures need to beseparated from implementation issues An architecture that is fundamentally flawed should be
quickly abandoned
You need flexibility
- Capable of implementing circuit blocks such as filters,VCOs, etc.
- Capable of implementing algorithms
- Arbitrary level of detail
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A Custom C++ Simulator Will Be Used - CppSim
Blocks are implemented with C/C++ code
- High computation speed- Complex block descriptions
Users enter designs in graphical form using Cadence
schematic capture
- System analysis and transistor level analysis in thesame CAD framework
Resulting signals are viewed in Matlab
- Powerful post-processing and viewing capability
Note: Hspice used for circuit level simulations
CppSim is on Athena and freely downloadable at
http://www-mtl.mit.edu/~perrott
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A Quick Preview of Homeworks and Projects
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HW1 Transmission Lines and Transformers
High speed data link application:
VoutC1 RL
L1Delay = x
Characteristic Impedance = Ro
Ideal Transmission Line
Ro
Vin
Two-Port Model
C2
Ei1
Er1
Ei2
Er2
dieAdjoining pinsConnector
Controlled Impedance
PCB trace
package
On-ChipDriving
Source
High Speed Trace (RF Connector to Chip Die)
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HW2 High Speed Amplifiers
M4
M1 M2
M3
IbiasVin+
R1
Vin-
R2
Vo+Vo-
50
Vin
M1
M2
Ls
Ld
Lg
Cbig
Ibias = 1mA
M3
Vout
CL=1pF5 k
Zin
x
Broadband
Narrowband
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HW3 Amplifier Noise and Nonlinearity
Amplifier circuit
ModelM1
Ibias
Vout
10
0.18
2
0.18
M2
RL
Vin
Cbig2
Cbig1
RT
50
Vin
50
50
Nonlinearity
Vout
Vout = co+ c1x + c2x2+ c3x
3
Noise
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HW4 Low Noise Amplifiers and Mixers
Narrowband LNA
Passive Mixer
Vin
CL
RL/2 RL/2
RS/2 Cbig
RS/2 Cbig
LO
LO LO
LO
Vout Vout
0 V
0
Vdd
0
Vdd
50
Vin
M1
M2
Ls
Lg
Cbig
Ibias = 1mA
M3
Vout
CL=1pF
5 k
Zin
Rps
RpgRps
Cbig
Ld
Rpd
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HW5 Voltage Controlled Oscillators
Differential CMOS
Colpitts
Vbias=1.2V
M1
Ld=4nH
Vout
C1=2pF
Ibias=100 A
C2=8pF
Rd=10k
M1M2
M3
Vout
Ctune
3 nH
100/0.18
50/0.18
M4100/0.18
50/0.18
VoutVin
1.8 V
0 V
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Project 1 - High Speed Frequency Dividers
High speed
latches/registers High speed dual-modulus
divider
Load
Load
ININ
OUT OUT
22/3Core
ControlQualifier
CON
IN OUT2
A B
2/3
INA
B
OUT
CON*
8 + CON Cycles
CON*
CON
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HW6 Phase Locked Loop Design
Integer-N synthesizer
Phase noise simulation
PFD Loop
Filter
ref(t) out(t)
Divider
T
T
e(t) vin(t)
div(t)
VCO
N[k] = Nnom
Icp
out(t) = cos(2 (fo+Kvvin())d)
vin out
t
s
1 + s/(2fp)
vph2
Sout(f)
foffset0
-20 dBc/Hz/dec
vspur = Asin(2fst)
K2 dBc
K1 dBc/Hz
fpfs
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Project 2 GMSK Transmitter for Wireless Apps
Kv = 30 MHz/V
fo = 900 MHz
GaussianLPFDataGenerator
Digital I/Q Generation
out(t)
T
T
t
Td
t
T
Loop FilterReferenceFrequency
vin(t)PFD
N
RF TransmitSpectrum
0f
fRF
Trans.Noise
PowerAmp
Kph
1 - z-1
cos()
sin()
D/A
D/A
finst
90o
I
Q
Peak-to-PeakFrequency
Deviation
Td
t
Inst
antaneous
Fr
equency
Data Eye
LimitAmp
(100 MHz)
= 1
1 MHz
IncludesZero-Order
Hold
Icp H(s)
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Project 2 Accompanying Receiver
0
f
ffRF
fRF
ReceivedSpectrum
ReceiverNoise
f
BasebandSpectrum
cos(2fRFt)
IR
QR
NR
ReceiverNoise
ModulationSignal
TransmitterNoise
S(IR+jQR)
Trans.
Noise LNA
BandSelect
Filter
ChannelSelectFilter
sin(2fRFt)
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Basics of Digital Communication
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Example: A High Speed Backplane Data Link
Suppose we consider packaging issues at the receiverside (ignore transmitter packaging now for simplicity)
Vout
Delay = 110 ps
Characteristic Impedance = 50
Ideal Transmission Line100
Vin
Two-Port Model
Ei1
Er1
Ei2
Er2
dieAdjoining pins
Controlled Impedance
PCB trace
package
On-Chip
Driving
Source
55 0.5 pF
M4
M1 M2
M3
Ibias Vin+ Vin-
Vo+
100 100
ReceiverTransmitter
unintentional
mismatch
intentional
mismatch
0.5 pF
1 nH
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Modulation Format
Binary, Non-Return to Zero (NRZ), Pulse Amplitude
Modulation (PAM)
- Send either a zero or one in a given time interval Td- Time interval set by a low jitter clock- Ideal signal from transmitter:
0 0.5 1 1.5 2 2.5
x 108
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
in
TIME
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Receiver Function
Two operations- Recover clock and use it to sample data- Evaluate data to be 0 or 1 based on a slicer
Slice
Level
Sampling
Instant
Recovered
Clock
Detector
Data
Clock
Recovery
Out
Data
Out0 1 1 111 10 0 0 0 0 0
Recovered
Clock
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Issue: PC Board Trace is Not an Ideal Channel
Chip capacitance and inductance limits bandwidth
Transmission line effects cause reflections in the
presence of impedance mismatch
Example: transmit at 1 Gb/s across link in previousslide (assume bondwire inductance is zero)
- Signal at receiver termination resistor
0 0.5 1 1.5 2 2.5
x 108
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
out
TIME
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Eye Diagram for 1 Gb/s Data Rate
Wrap signal back onto itself every 2*Td seconds
- Same as an oscilloscope would do Allows immediate assessment of the quality of the
signal at the receiver (look at eye opening)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 109
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Time (seconds)
out
Eye Diagram
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Relationship of Eye to Sampling Time and Slice Level
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 109
0.05
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
Time (seconds)
out
Eye Diagram
Slice
Level
Sampling
Instant
Horizontal portion of eye indicates sensitivity to timing
jitter
Vertical portion of eye indicates sensitivity to additional
noise and ISI
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What Happens if We Increase the Data Rate?
Limited bandwidth and reflections cause intersymbol
interference (ISI)
Eye diagram at 10 Gb/s for same data link
0 1 2
x 1010
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (seconds)
out
Eye Diagram
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What is the Impact of the Bondwire Inductance?
Rule of thumb: 1 nH/mm for bondwire
- Assume 1 nH Impact of inductance here increases bandwidth
- less ISI occurs
0 1 2
x 1010
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (seconds)
out
Eye Diagram
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How High of a Data Rate Can The Channel Support?
Raise it to 25 Gb/s
However, we havent considered other issues
- PC board trace attenuates severely at high frequencies Bandwidth is < 5 GHz for 48 inch PC board trace (FR4)
0 2 4 6 8
x 1011
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
Time (seconds)
out
Eye Diagram
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Multi-Level Signaling
Increase spectral efficiency by sending more than onebit during a symbol interval
- Example: 4-Level PAM at 12.5 Gb/s on same channel
Effective data rate: 25 Gb/s
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
x 1010
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
Time (seconds)
out
Eye Diagram
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How Else Can We Reduce ISI?
Consider a system level view of the link
- Channel can be viewed as having an equivalentfrequency response
Assumes linearity and time-invariance (accurate for mosttransmission line systems)
Transmitter
Driver
Receiver
Detector
Channel
Transmitter Receiver
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Equalization
Undo channel frequency response with an inverse
filter at the receiver
- Removes ISI!
- Can make it adaptive to learn channel
Transmitter
Driver
Receiver
Detector
Channel
Transmitter Receiver
Equalization
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The Catch
Equalization enhances noise
- Overall SNR may be reduced Optimal approach is to make ISI and noise
degradation about equal
Transmitter
Driver
Receiver
Detector
Channel
Transmitter Receiver
EqualizationNoise
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Alternative Pre-emphasize at Transmitter
Put inverse filter at transmitter instead of receiver
- No enhancement of noise, but - Need feedback from receiver to learn channel
- Requires higher dynamic range/power from transmitter
Transmitter
Driver
Receiver
Detector
Channel
Trransmitter Receiver
NoiseCompensation
(Pre-emphasis)
O f
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Best Overall Performance
Combine compensation and equalization
- Starting to see this for high speed links
Transmitter
Driver
Receiver
Detector
Channel
Trransmitter Receiver
EqualizationNoiseCompensation
(Pre-emphasis)
Wh t th I ith Wi l S t ?
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What are the Issues with Wireless Systems?
Noise
- Need to extract the radio signal with sufficient SNR Selectivity (filtering, processing gain)
- Need to remove interferers (which are often much larger!) Nonlinearity
- Degrades transmit spectral mask
- Degrades selectivity for receiver Multi-path (channel response)
- Degrades signal nulls rather than ISI usually the issue
- Can actually be used to advantage!We will look at BOTH broadband data links and
wireless systems in this class