VHDL BASICS

Traditional vs Hardware Description Languages

Procedural programming languages provide the how or recipes

– for computation– for data manipulation– for execution on a specific hardware model

Hardware description languages describe a system

– many different facets– behavior– structure– functional properties– physical properties

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Why do we Describe Systems?

Design Specification– unambiguous definition of components and

interfaces in a large design

Design Simulation– verify system/subsystem/chip performance

prior to design implementation

Design Synthesis– automated generation of a hardware design

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A Digital System Design Flow

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Why HDLs Instead of Diagrams?

Schematic Diagrams

•Limited descriptive power

State Diagrams and Algorithmic State Machines

•Limited portability

•Limited complexity

•Difficult to describe parallelism

HDLs

•Highly portable (text)

• Describes multiple levels of abstraction

• Represents parallelism

• Provides many descriptive styles

•Structural

•Dataflow

•Behavioral

• Serves as input for synthesis5

n+n+S

GD

+

DEVICE

CIRCUIT

GATE

MODULE

SYSTEM

What HDLs can model?

HDL

HDL

HDL

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VHDL

• The VHDL Language• V Very High Speed Integrated Circuit• H Hardware• D Description• L Language

• Technology independent description• Reuse of components described in VHDL

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Execution Models for VHDL Programs

Two classes of execution models govern the application of VHDL programs

Simulation– discrete event simulation– understanding is invaluable in debugging programs

Synthesis– inference of hardware– a function of the building blocks used for implementation

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TYPICAL VHDL FILE

------LIBRARY DECLARATION

……ENTITY

----defines external details

…….ARCHITECTURE ------defines internal details

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Entity Declarations

• The primary purpose of the entity is to declare the signals in the design’s interface– The interface signals are listed in the PORT

clause• In this respect, the entity is similar to the schematic

symbol for the component

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Syntax:entity entity_name is

Port declaration;

end entity_name;

• An entity declaration should starts with ‘entity’ and ends with ‘end’ keywords.

In Port - can be read

Out Port - can be written

Inout Port - can be read and written

Buffer Port - can be read and written, it can have only one source.

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Half adder

enable

x

ycarry

resultHalf Adder

-- a simple half adder modelLIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;

ENTITY ha IS PORT( x, y, enable: IN BIT;

carry, result: OUT BIT);END ha;

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Architecture

• Describe the operation of the component• Consist of two parts :

– Declarative part -- includes necessary declarations• e.g. type declarations, signal declarations, component

declarations, subprogram declarations

– Statement part -- includes statements that describe organisation and/or functional operation of component

• e.g. concurrent signal assignment statements, process statements, component instantiation statements

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Syntax:architecture architecture_name of entity_name is

architecture_declarative_part;

begin

Statements;

end architecture_name;

• Here we should specify the entity name for which we are writing the architecture body.

• The architecture statements should be inside the begin and end keyword.

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Architecture

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• The internal working of an entity can be defined using different modeling styles inside architecture body.

• They are• Dataflow modeling.• Behavioral modeling.• Structural modeling.

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Behavioral modeling

• In this style of modeling, the internal working of an entity can be implemented using set of statements.

• It contains:

Process statements

Sequential statements

Signal assignment statements

Wait statements

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x

y

enable

carry

result

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Behavioral model

ARCHITECTURE ha2 OF ha ISBEGIN

PROCESS (x, y, enable)BEGIN

IF enable = ‘1’ THENresult <= x + y;carry <= x AND y;

ELSEcarry <= ‘0’;result <= ‘0’;

END IF;END PROCESS;

END ha2;

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Process statement

• It is the primary mechanism used to model the behavior of an entity.

• It contains sequential statements, variable assignment (:=) statements or signal assignment (<=) statements etc.

• It may or may not contain sensitivity list. If there is an event occurs on any of the signals in the sensitivity list, the statements within the process is executed.

• Inside the process the execution of statements will be sequential and if one entity is having two processes the execution of these processes will be concurrent. At the end it waits for another event to occur.

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Dataflow modeling

• In this style of modeling, the internal working of an entity can be implemented using set of statements

• In the data flow approach, we describe how signals (data) flow through the circuit

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Dataflow model

ARCHITECTURE ha1 OF ha IS

BEGIN

carry <= enable AND (x AND y);

result <= enable AND (x XOR y);

END ha1;

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Structural modeling

• The implementation of an entity is done through set of interconnected components.

• The structural description of a design is simply a textual description of a schematic.

• It contains:

Signal declaration.

Component instances

Port maps.

Wait statements.

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STRUCTURAL MODEL

ARCHITECTURE ha3 OF ha ISCOMPONENT and_ent

PORT (in0, in1 : IN BIT;out0 : OUT BIT);

END COMPONENT;

COMPONENT and3PORT (in0, in1, in2 : IN BIT;

out0 : OUT BIT);END COMPONENT;

COMPONENT xor_entPORT (in0, in1 : IN BIT;

out0 : OUT BIT);END COMPONENT;

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SIGNAL temp : BIT; -- internal signal

-- Note that other signals are already

-- declared in entity

BEGIN

A0 : and2 PORT MAP (enable, temp, result);

A1 : and3 PORT MAP (x, y, enable, carry);

X0 : xor2 PORT MAP (x, y, temp);

END ha3;

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Component declaration

Syntax:component component_name

List_of_interface ports;

end component component_name;

• Before instantiating the component it should be declared using component declaration.

• Component declaration declares the name of the entity and interface of a component.

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• Port map is used to connect different components as well as connect components to ports of the entity.

• Component instantiation is done as follows.Component_label: component_name port map (signal_list);

• Signal_list is the architecture signals which we are connecting to component ports.

• This can be done in different ways. What we declared above is positional binding. One more type is the named binding. The above can be written as,

A0 : and2 PORT MAP (in0 => enable, in1 => temp, out0 => result);

A1 : and3 PORT MAP (in0 => x, in1 => y, in2 => enable, out0 => carry);

X0 : xor2 PORT MAP (in0 => x, in1 => y, out0 => temp);

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Entity FOR DECODER

entity DECODER is

port (A, B, enable :in BIT ;

Z : out BIT-VECTOR ( 0 to 3);

end DECODER ;

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Data flow model for decoder

architecture D_FLOW of DECODER issignal ABAR ,BBAR :bitbegin

Z(3) <= not (A and B and ENABLE); Z(0) <= not (ABAR and BBAR and ENABLE); BBAR <= not B; Z(2) <= not (A and BBAR and ENABLE) ; ABAR <= not A; Z(1) <= not (ABAR and B and ENABLE); end D_FLOW;

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Behavioral ModelArchitecture SEQ of DECODER isbegin process(A,B,ENABLE)

variable ABAR,BBAR:bit; begin

ABAR := not A;BBAR := not B;if ENABLE =‘1’ then

Z(3) <= not (A and B); Z(2) <= not (A and BBAR);

Z(1) <= not (ABAR and B); Z(0) <= not (ABAR and BBAR);

else Z<=“1111” end if;

end process;end SEQ; 33

Structural Model architecture STRUC of DECODER is component INV; port (PIN:in BIT;POUT:out BIT); end component; component NAND3; port ( D0,D1,D2 : in BIT; DZ :out BIT); end component ; signal ABAR ,BBAR:BIT;

Begin V0:INV port map (A,ABAR);

V1:INV port map (B,BBAR); N0:NAND3 port map(ENABLE,ABAR,BBAR,Z(0); N1:NAND3 port map (ABAR ,B,ENABLE,Z(2); N2:NAND3 port map(A,BBAR,ENABLE,Z(2)); N3:NAND3 port map (A ,B,ENABLE ,Z(3)); end STRUC;

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DATA OBJECTS AND TYPESAND

RESOLVING SIGNAL VALUES

General aspects

• Case insensitive• Comments: '--' until end of line• Statements are terminated by ';'• Statements may span multiple lines• List delimiter: ','• Signal assignment: '<='• User defined names:

– Can contain letters, numbers, underscores– start with a letter

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---------------------------------

-- Example VHDL Code --

---------------------------------

signal mySignal: bit; -- an example signal

MYsignal <= '0', -- start with '0'

'1' AFTER 10 ns, -- and toggle after

'0' after 20 ns, -- every 10 ns

'1' after 30 ns;

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(Normal) IDENTIFIER

Letters, numerals, underscores

Case insensitive

No two consecutive underscores

Must begin with a letter

No VHDL keyword

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mySignal_23 -- normal identifier

rdy, RDY, Rdy -- identical identifiers

vector_&_vector -- X : special character

last of Zout -- X : white spaces

idle__state -- X : consecutive underscores

24th_signal -- X : begins with a numeral

open, register -- X : VHDL keywords

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Extended Identifier (VHDL93)

Enclosed in back slashes

Case sensitive

Graphical characters allowed

May contain spaces and consecutive underscores

VHDL keywords allowed

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\mySignal_23\ -- extended identifier

\rdy\, \RDY\, \Rdy\ -- different identifiers

\vector_&_vector\ -- legal

\last of Zout\ -- legal

\idle__state\ -- legal

\24th_signal\ -- legal

\open\, \register\ -- legal

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DATA OBJECTS

• Constant• Variable• Signal• File

Object declaration – declare its class and type

e.g. for constants –

Constant is its class

Integer is its type

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Constant Declarations

• Constant APPLE: INTEGER: =0;• Constant PULSE_WIDTH: TIME:=6 ns• Constant INPUT: INTEGER :=8• If the value of the constant is not specified, it is called a

deferred constant.

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Variable Declarations

• variable ABAR :BIT;• variable STATUS: INTEGER :=10;• variable SUM: INTEGER range 0 to 10 ;• variable NO ,YES:BOOLEAN ;• If no initial value is specified, default value

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Signal Declarations

signal PULSE :BIT

signal ADDR_BUS: BIT_VECTOR(10 downto 0);

Default value for Bit is ‘0’

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Standard Data Types

• Every type has a number of possible values• Standard types are defined by the language• User can define his own types

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DATA TYPES

• package STANDARD is type BOOLEAN is (FALSE,TRUE); type BIT is (‘0’, ‘1’); type CHARACTER is (-- ascii set); type INTEGER is range -- implementation_defined type REAL is range -- implementation_defined -- BIT_VECTOR, STRING, TIME

end STANDARD;

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DATA TYPE TIME

• Usage– testbenches– gate delays

• returns TIME type• internally in smallest unit (fs)• Available time units : fs, ps, ns, us, ms, sec, min, hr

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architecture EXAMPLE of TIME_TYPE is signal CLK : bit := `0'; constant PERIOD : time := 50 ns;

begin process begin wait for 50 ns; . . . wait for PERIOD ; . . . wait for 5 * PERIOD ; . . . wait for PERIOD * 5.5; end process; -- concurrent signal assignment CLK <= not CLK after 0.025 us; -- or with constant time -- CLK <= not CLK after PERIOD/2;

end EXAMPLE;50

Arrays• Collection of signals of the same type• Represent P address and data, function selection,

etc.• bit_vector (array of bit) or std_logic_vector• string (array of character)• We must also specify vector index range and

direction– big endian: (low to high)– little endian: (high downto low)

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Array Declarations

port (A, B: in std_logic_vector(7 downto 0); Z: out std_logic_vector(1 to 16));

A and B:

Z:

7 6 5 4 3 2 1 0

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

For Arrays A and B, 7th bit is the MSB.

But for array Z, 1st bit is the MSB

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Signal A_BUS, Z_BUS: bit_vector (3 downto 0);

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‘bit’ and ‘integer’ - examplearchitecture EXAMPLE_1 of DATATYPES issignal SEL : bit ;signal A, B, Z : integer range 0 to 3;begin A <= 2; B <= 3; process(SEL,A,B) begin if SEL = '1' then Z <= A; else Z <= B; end if; end process;end EXAMPLE_1; 54

architecture EXAMPLE_2 of DATATYPES issignal SEL : bit ; signal A, B, Z: bit_vector (1 downto 0);begin A <= "10"; B <= "11";process(SEL,A,B) begin if SEL = '1' then Z <= A; else Z <= B; end if; end process;end EXAMPLE_2;

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Assignments with Array Types

• Elements are assigned according to their position, not their number

• The direction of arrays – Use only one direction (usually 'downto' in hardware

applications) throughout your designs.

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architecture EXAMPLE of ARRAYS is signal Z_BUS : bit_vector (3 downto 0); signal C_BUS : bit_vector (0 to 3);begin Z_BUS <= C_BUS;end EXAMPLE;

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Types of Assignment for 'bit' Data Types

• Single bit values are enclosed in '.'• Vector values are enclosed in "..."• optional base specification (default: binary)• we can also specify Vector values using octal,

decimal, or hexadecimal.– O “1234” D “1999” X “ABCD”

• values may be separated by underscores to improve readability

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architecture EXAMPLE of ASSIGNMENT is signal Z_BUS : bit_vector (3 downto 0); signal BIG_BUS : bit_vector (15 downto 0); begin -- legal assignments: Z_BUS(3) <= ‘1’; Z_BUS <= "1100"; Z_BUS <= b "1100"; Z_BUS <= X "C"; Z_BUS <= X ‘C’; -- invalid BIG_BUS <= B "0000 _ 0001_0010_0011";end EXAMPLE;

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Concatenation operator &

architecture EXAMPLE_1 of CONCATENATION is

signal BYTE : bit_vector (7 downto 0);

signal A_BUS, B_BUS : bit_vector (3 downto 0);

begin

BYTE <= A_BUS & B_BUS;

end EXAMPLE;

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architecture EXAMPLE_2 of CONCATENATION is signal Z_BUS : bit_vector (3 downto 0); signal A_BIT, B_BIT, C_BIT, D_BIT : bit;

beginZ_BUS <= A_BIT & B_BIT & C_BIT & D_BIT;

end EXAMPLE;

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Aggregates

• Aggregates bundle signals together• May be used on both sides of an assignment• keyword 'other' selects all remaining elements• Some aggregate constructs may not be supported by

your synthesis tool.• Assignment of `0` to all bits of a vector regardless of

the width:

VECTOR <= (others => '0');

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architecture EXAMPLE of AGGREGATES is signal BYTE : bit_vector (7 downto 0); signal Z_BUS : bit_vector (3 downto 0); signal A_BIT, B_BIT, C_BIT, D_BIT : bit;

beginB_BIT <= ‘0’;

Z_BUS <= ( A_BIT, B_BIT, C_BIT, D_BIT ) ;( A_BIT, B_BIT, C_BIT, D_BIT ) <= BYTE (3

downto 0); BYTE <= ( 7 => `1`, 5 downto 2 => `1`, 6 =>

B_BIT, others => `0`) ;end EXAMPLE;

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SLICES OF ARRAYS

• The inverse operation of concatenation and aggregation is the selection of slices of arrays, i.e. only a part of an array is to be used.

• The range of the desired array slice is specified in brackets and must match the range declaration of the signal!

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architecture EXAMPLE of SLICES is signal BYTE : bit_vector (7 downto 0); signal A_BUS, Z_BUS : bit_vector (3 downto 0); signal A_BIT : bit;begin BYTE (5 downto 2) <= A_BUS; BYTE (5 downto 0) <= A_BUS; -- wrong Z_BUS (1 downto 0) <= `0` & A_BIT; Z_BUS <= BYTE (6 downto 3) A_BIT <= A_BUS (0);end EXAMPLE;

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Multi-dimensional arrays

• Syntaxtype array_name is array (index_ range , index_range) of element_ type;

• example:type memory is array (3 downto 0, 7 downto 0);

• For synthesizers which do not accept multidimensional arrays, one can declare two uni-dimensional arrays.

• example:type byte is array (7 downto 0) of std_logic;

type mem is array (3 downto 0) of byte;67

Type classification

• Scalar types:

contain exactly one value.

integer, real, bit, enumerated• Composite types:

may contain more than one value• array : values of one type, only• record : values of different types

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• Other types:

"file"

"access“• FILE and ACCESS types are data types that provide

access to other objects. • The FILE type is used to read or store data in a file; • ACCESS types are comparable with pointers.

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Enumeration Types

• Designers may define their own types• enhanced readability• (commonly used to describe the states of a state

machine)• Synthesis tools map enumerations onto a suitable bit

pattern

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Architecture EXAMPLE of ENUMERATION is

type T_STATE is (RESET, START, EXECUTE, FINISH);

signal CURRENT_STATE, NEXT_STATE : T_STATE ;

signal TWO_BIT_VEC : bit_vector(1 downto 0);

Begin -- valid signal assignments NEXT_STATE <= CURRENT_STATE; CURRENT_STATE <= RESET; -- invalid signal assignments CURRENT_STATE <= "00"; CURRENT_STATE <= TWO_BIT_VEC;end EXAMPLE;

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• In the example, a new data type with values denoting four different states (RESET, START, EXECUTE, FINISH) is defined. This type is used for the two signals CURRENT_STATE and NEXT_STATE and the four declared type values can be assigned directly.

• Of course, after synthesis, there will be two bits for each signal, but a direct assignment of a two bit vector is not allowed.

• In a signal assignment only those values may be used which are enumerated in the type declaration.

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SUBTYPES

• Subsets of existing types• Same type as the original type• Is a type with a constraint• More readable signal assignments• The type is called the base type of the subtype• subtype MY_WORD is INTEGER range 50 to 100;• type DIGIT is (‘0’,’1’ ,’2’, ‘3’,’4’);• subtype PART is DIGIT range ‘1’ to ‘3’;• Subtypes need not impose a constraint .It can simply

give another name to a type .

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BIT Type Issues

• Values `0` and `1`, only• default value is `0`Additional requirements for simulation and

synthesis• uninitialized• high impedance• undefined• `don`t care`• different driver strengths

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• The ' bit ' type has only the two values '0' and '1'. While this is enough to model simple logic where the wires are driven either high or low level, further options are desirable, especially for simulation purposes

• Additional legal wire conditions are necessary, if different driver strengths or high impedance outputs of real hardware drivers are to be modeled. It depends on the synthesis tool whether these additional logic values can be mapped to the corresponding hardware cells. In order to avoid hardware overhead one might think of designating bit positions that may safely be ignored during synthesis ("don't care").

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• In the beginning, several incompatible multi-valued logic systems were defined by the different software companies.

• In order to solve the resulting problems, a standardized 9-valued logic system was defined and accepted by the IEEE in 1992.

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Multi-valued Types

• Multi-valued logic-systems are declared via new datatypes

• uninitialized • unknown• high impedance• ...

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• No common standard before 1992• 9-valued logic-system defined and accepted by the

IEEE • The new data type is called 'std_ulogic' and is defined

in the package 'std_logic_1164' which is placed in the library IEEE. It is included by the following statement:

'use IEEE.std_logic_1164.all'.

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IEEE Standard Logic Type

type STD_ULOGIC is ( ` U `, -- uninitialized ` X `, -- strong 0 or 1 (= unknown) ` 0 `, -- strong 0 ` 1 `, -- strong 1 ` Z `, -- high impedance ` W `, -- weak 0 or 1 (= unknown) ` L `, -- weak 0 ` H `, -- weak 1 ` - `, -- don`t care);

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• 9 different signal states• Superior simulation results• Bus modeling• "ASCII-characters“• Array types available: 'std_(u)logic_vector', similar to

'bit_vector'• All 'bit' operators available

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• The new type is implemented as enumerated type by extending the existing '0' and '1' symbols with additional ASCII characters.

• The most important ones are probably 'u' (uninitialized) and 'x' (unknown value). The 'u' symbol is the leftmost symbol of the declaration, i.e. it will be used as initial value during simulation.

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Resolved and Unresolved Types

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• Signal assignments are represented by drivers• Unresolved data type: only one driver• Resolved data type: possibly several drivers per signal• Besides the type definition of 'std_ulogic' the

'std_logic_1164' package also contains the definition of a similar type called 'std_logic' which has the same value set as 'std_ulogic'.

• Like 'bit_vector', array data types 'std_(u)logic_vector' are also available. Additionally, all operators that are defined for the standard type 'bit' are overloaded to handle the new replacement type.

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• As mentioned before, the 'bit' data type can not be used to model bus architectures. This is because all signal assignments are represented by drivers in VHDL.

• If more than one driver try to force the value of a signal a resolution will be needed to solve the conflict. Consequently, the existence of a resolution function is necessary for legal signal assignments.

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• Predefined VHDL data types do not possess a resolution function because the effects of multiple signal drivers depend on the actual hardware realization. The 'std_ulogic' data type ("u" = "unresolved") is the basis for the resolved data type 'std_logic'.

• The decision about the final signal value in case of multiple drivers, is based upon a resolution table. All driving values are collected in an array and handed to the resolution function, even if only a single driver is present!

• The result is calculated element by element according to the table

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• The 'resolved' function that is also defined in the 'std_logic_1164' package gets called whenever signal assignments involving 'std_logic' based data types are carried out.

• The current result selects the row of the resolution table and the value of the next signal driver selects the column of the resulting signal value.

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Resolution Table for standard logic

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STD_LOGIC vs STD_ULOGIC

• STD_ULOGIC• STD_ULOGIC_VECTOR

Benefit• Error messages in case of multiple concurrent signal

assignments

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• STD_LOGIC• STD_LOGIC_VECTOR

Benefit• Common industry standard• gate level netlists• mathematical functions• Required for tri-state busses

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• By far most of the connections in a design, either as abstract signals or later on as real wires, are from one point to another, i.e. multiple signal drivers would indicate an error. This kind of error will be easily detected if just unresolved data types are used.

• Yet, the resolved counterpart 'std_logic' has been established as de facto industry standard despite of some shortcomings. As all kind of hardware structures, including bus systems, can be modeled with this data type. It is used by synthesis tools for the resulting gate level description of a design.

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• Even a workaround exists, so that multiple signal assignments can still be detected: the port mode 'buffer' allows for a single signal driver, only. According to the VHDL language definition, however, the resolution function has to be called when resolved signals are assigned. The impact on simulation performance depends on the compiler/simulator implementation.

• The last, but certainly not the least advantage of 'std_logic' based designs is the existence of standard packages defining arithmetical operations on vectors. This eliminates the need for complex type conversion functions and thus enhances the readability of the code.

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• The ' numeric_std ' package is located in the library IEEE and provides two numerical interpretations of the bit vector, either as signed or as unsigned integer value. Overloaded operators to mix vectors and integers in expressions are also available.

• The typical algebraic operators are available for integers, such as +,-,* (multiplication), and / (division). Although these operations are not built-in for bit_vectors, they are often provided in libraries that come with your VHDL software. They are used with bit_vectors by interpreting them as a binary representation of integers, which may be added, subtracted, multiplied, or divided.

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• Conversion functions ' to_integer ' and ' to_(un)signed ' are also defined in the package.

• The equivalent of ' numeric_std ' for ' bit ' based operations is called ' numeric_bit '.

• The use of ' bit ' based signals is not recommended, however, due to the disadvantages of a 2-valued logic system.

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OPERATORS

VHDL OPERATORSThere are 7 groups of predefined VHDL operators:

1. Binary Logical operators: and, or, nand, nor, xor, xnor

2. Relational operators: =, /=, <, <=, >, >=

3. Shifts operators: sll, srl, sla, sra, rol, ror

4. Adding operators: +, -, &(concatenation)

5. Unary sign operators: +, -

6. Multiplying operators: *, /, mod, rem,

7. Miscellaneous operators: not, abs, **(exponentiation)

The above classes are arranged in increasing priority when parentheses are not used.

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LOGICAL OPERATORS• Defined for bit, boolean, std_logic , std_ulogic and their

vectors• Data types have to match

• Predefined operators are all binary• Multi-input operators formed from series of binary

operators– AND-3: A and B and C

• nand and nor operators are not associative.• Use parentheses in a sequence of nand or nor operators

to prevent a syntax error:

Eg: X nand Y nand Z will give a syntax error and should be written as (X nand Y) nand Z.

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Operator Precedence

• ALL binary operators have the SAME precedence• Operators with the same precedence are evaluated left-

to-right• Operators in parentheses are evaluated first; innermost

to outermost order– Must be used for proper AND - OR evaluation

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Priority of operators.

Let A=”110”, B=”111”, C=”011000”, and D=”111011”

(A & not B or C ror 2 and D) = “110010” ?

the operators are applied in the following order: not, &, ror, or, and, =

not B = ‘000” --bit-by-bit complement

A & not B = “110000” --concatenation

C ror 2 = “000110” --rotate right 2 places

(A & not B) or (C ror 2) = “110110 --bit-by-bit or

(A & not B or C ror 2) and D = “110010” --bit-by-bit and

[(A & not B or C ror 2 and D) = “110010”]=TRUE --with parentheses the equality test is done last

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entity LOGIC_OP is port (A, B, C, D : in bit; Z1: out bit; EQUAL : out boolean);end LOGIC_OP;

architecture EXAMPLE of LOGIC_OP isbegin Z1 <= A and (B or (not C xor D))); EQUAL <= A xor B; -- wrongend EXAMPLE;

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Vector Logical Operations

• Single bit logical operations also apply to vectors– Operands MUST be the same size (generally applies

to all vector operations)– Assignment target must also have the same number

of bits as the result– Operations are applied bitwise to operands to

produce the vector result– Assignment via the position of the elements

(according to range definition)

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Given:

signal A, B, Z: std_logic_vector(7 downto 0);

Then the following logical operation and assignmentZ <= A and B;

Is equivalent to:for i = 0 to 7Zi = Ai and Bi ;

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architecture EXAMPLE of LOGICAL_OP is

signal A_BUS, B_BUS : bit_vector (3 downto 0);

signal Z_BUS : bit_vector (4 to 7);

begin

Z_BUS <= A_BUS and B_BUS;

end EXAMPLE;

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Relational operators

• They are =, /=, <, <=, > and >= and have their usual meanings (/= denotes the not equal operator).

• The result of all these operators is a boolean value (TRUE or FALSE).

• The arguments to the = and /= operators may be of any type.

• The arguments of the <, <=, > and >= operators may be any scalar type (integer, real, and physical types) or the bit_vector type.

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• If the arguments are bit_vectors, then the arguments must be the same length and the result is TRUE only if the relation is true for each corresponding element of the array arguments.

• When operands are discrete array types, comparison is performed one element at a time from left to right .

“011” < “101” -- True

Since the first element in the first array is less than the first element in the second.

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architecture EXAMPLE of COMPARISON is signal NIBBLE: bit_vector(3 downto 0); signal BYTE: bit_vector(0 to 7);begin NIBBLE <= "1001"; BYTE <= "00001111";

COMPARE: process (NIBBLE, BYTE) begin if (NIBBLE < BYTE) then -- evaluated as: -- if (NIBBLE(3) < BYTE(0)) or -- ((NIBBLE(3) = BYTE(0)) and -- (NIBBLE(2) < BYTE(1))) or -- ((NIBBLE(3) = BYTE(0)) and -- (NIBBLE(2) = BYTE(1)) and -- (NIBBLE(1) < BYTE(2))) or ... -- better: if (( "0000"& NIBBLE) <= BYTE) then

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• When comparing array types it must be considered that the comparison is carried out from the left side to the right.

• Arrays may differ in length • left-alignment prior to comparison• are compared element after element• No numerical interpretation (unsigned, 2-complement,

etc.) • That means for arrays of varying length that "111" is

greater than "1001", for example. If it is not desired, hence shall be compared right-aligned, then the arrays will have to be brought upon the equal length by hand, e.g. by means of concatenation: '0'&"111" is then smaller than "1001".

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Shift Operators

• Each of the operator takes an array of bit or boolean as the left operand and an integer value as the right operand

• If the integer value is a negative number, the opposite action is performed i.e., a left shift or rotate becomes a right shift or rotate respectively and vice versa

• The sll and srl operator fill the vacated bits with left operand type

• The sla operator fills the vacated bits with right most bit of the left operand, while the sra operator fills the vacated bits with leftmost bit of the left operand

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Example: Shift operators.

Let A = “10010101”

A sll 2 = “01010100” --shift left logical, filled with ‘0’

A srl 3 = “00010010” --shift right logical, filled with ‘0’

A sla 3 = “10101111” --shift left arithmetic, filled with right bit

A sra 2 = “11100101” --shift right arithmetic, filled with left bit

A rol 3 = “10101100” --rotate left by 3

A ror 5 = “10101100” --rotate right by 5

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Adding Operators

• + (add), -(sub), &(concatenation)• + and – are predefined for

integer

real

physical types (e.g. time)

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Multiplying Operators

• * (mul), / (div), mod (modulus), rem (remainder)• * and / are predefined for

integer

real (except mod and rem)

physical types (e.g. time)• The rem and mod operators operate on operands of

integer type and the result is also of the same type

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• The result of rem has the sign of its first operand

A rem B = A – (A/B) * B (in which A/B in an integer)

• The result of mod has the sign of its second operand

A mod B = A – B * N (in which N is an integer), where N = ⌈A/B when A or B < 0 ⌉ = A/B when both A, B > 0 or both A, B < 0⌊ ⌋

(ceiling(x) = ⌈x is the smallest integer not less than ⌉ x

floor(x) = ⌊x is the largest integer not greater than ⌋ x)

Examples:7 rem 4 = 3 7 mod 4 = 3

(-7) rem 4 = -3 (-7) mod 4 = 1

7 rem (-4) = 3 7 mod (-4) = -1

(-7) rem (-4) = -3 (-7) mod (-4) = -3 113

• The typical algebraic operators,such as +,-,* (multiplication), and / (division) are not built-in for bit_vectors. But they are often provided in libraries that come with your VHDL software. They are used with bit_vectors by interpreting them as a binary representation of integers, which may be added, subtracted, multiplied, or divided.

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Vector Arithmetic Operations

• Vector arithmetic operations are basically the same as vector logical operations– Operands MUST be the same size – Assignment target must also have the same number of bits as

the result– Operations are applied bitwise to operands to produce the

vector result

• The only difference is the carry or borrow– Carry in/out must be specially handled– Result can be 1 bit larger than operands (CO)

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Example

If the left and right signed operands are of different lengths, the shortest operand will be sign-extended before performing an arithmetic operation. For unsigned operands, the shortest operand will be extended by filling in 0s on the left.

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Miscellaneous operators

• not, abs, **(exponentiation)• Unary ‘not’ has a higher precedence than any binary

operator• Abs (absolute) is defined for any numeric type • **(exponentiation)

– left operand : integer or real type – Right operand : integer

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