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Computer Programming TA C162

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Topics to be covered

Phases of Instruction processingInstruction Set Architecture (ISA) of LC-3 Computer

Operate Instruction

AND

ADD

NOT

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Recall LC-3 ADD Instruction

Recall LC-3 LDR Instruction

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Instruction Processing: FETCH

Load next instruction from memory intoInstruction Register (IR).

Copy contents of PC into MAR.

Send read signal to memory.

Copy contents of MDR into IR.

Then increment PC, so that it points to the

next instruction in sequence. PC becomes PC+1.

EA

OP

EX

S

F

D

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Instruction Processing: DECODE

First identify the opcode. In LC-3, this is always the first four bits of

instruction.

A 4-to-16 decoder asserts a control line

corresponding to the desired opcode.Depending on opcode, identify other operands from

the remaining bits.

Example:

For LDR, last six bits is offset

For ADD, last three bits is source operand #2

EA

OP

EX

S

F

D

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Instruction Processing: EVALUATE ADDRESS

For instructions that require memory access

to get the operands; compute address used

for access.

Example:

Add offset to base register (as in LDR)

EA

OP

EX

S

F

D

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Instruction Processing: FETCH OPERANDS

Obtain source operands needed to performthe operation.

Examples:

Load data from memory (LDR)

Read data from register file (ADD)

EA

OP

EX

S

F

D

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Instruction Processing: EXECUTE

Perform the operation, using the sourceoperands.

Examples:

Send operands to ALU and assert ADD signal

Do nothing (e.g., for loads and stores)

EA

OP

EX

S

F

D

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Instruction Processing: STORE RESULT

Write results to destination.(Register or Memory)

Examples:

Result of ADD is placed in destination register

Result of memory load is placed in destination

register

For store instruction, data is stored to memory

EA

OP

EX

S

F

D

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Instruction Set Architecture of LC-3ISA = All of theprogrammer-visible components

and operations of the computer Memory organization

Address space -- How may locations can be addressed? Address space: 216 locations (16-bit addresses)

Addressability -- How many bits per location?

Addressability: 16 bits

Register set How many? What size?

Eight general-purpose registers: R0 - R7 Each 16 bits wide Temporary storage, accessed in a single machine cycle

Accessing memory generally takes longer than a singlecycle

Other registers Not directly addressable, but used by (and affected by)

instructions

PC (program counter), condition codes

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Instruction Set Architecture of LC-3 ContInstruction set

Opcodes 15 opcodes Operate instructions: ADD, AND, NOT Data movementinstructions: LD, LDI, LDR, LEA, ST, STR, STI Controlinstructions: BR, JSR/JSRR, JMP, RTI, TRAP

Data types 16-bit 2s complement integer

Addressing modes How is the location of an operand specified? Non-memory addresses: immediate, register

Memory addresses: PC-relative, indirect, base+offset

ISA provides all information needed to write a program in machinelanguage

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Operate Instructions

Only three operations: ADD, AND, NOT

Source and destination operands are registers

These instructions do notreference memory.

ADD and AND can use immediate mode,

where one operand is hard-wired into the instruction.

Show dataflow diagram with each instruction. Illustrates when and where data moves to accomplish the

desired operation

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ADD/AND (Immediate)

Note: Immediate field is

sign-extended.

this one means immediate mode

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Lets try Using Operate Instructions

With only ADD, AND, NOT

1. How do we subtract?

i.e. A - B

2. How do we initialize a register to zero?

3. How do we copy from one register to another?

4. How do we OR? (Try your self)

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0 1 0 1 0 1 0 0 1 0 1 0 0 0 0 0

Solution 2

AND R2 R2

Register R2 is initialized to zero

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