ECE2030 Introduction to Computer Engineering

Lecture 4: CMOS Network

Prof. Hsien-Hsin Sean LeeProf. Hsien-Hsin Sean LeeSchool of Electrical and Computer EngineeringSchool of Electrical and Computer EngineeringGeorgia TechGeorgia Tech

22

CMOS Inverter• Connect the following terminals of a PMOS and an

NMOS– Gates– Drains

Vin Vout

Vdd

Gnd

Vout

Vin

Vin

Vin = HIGHVout = LOW (Gnd)

ONON

OFFOFF

Vdd

Gnd

Vout

Vin

Vin

Vin = LOWVout = HIGH (Vdd)

ONON

OFFOFF

Vdd

PMOS

Ground

NMOS

33

CMOS Voltage Transfer Characteristics

Vdd

Gnd

Vin Vout

PMOS

NMOS

OFF: V_GateToSource < V_ThresholdLINEAR (or OHMIC): 0< V_DrainToSource < V_GateToSource - V_Threshold SATURATION: 0 < V_GateToSource - V_Threshold < V_DrainToSourceNote that in the CMOS Inverter V_GateToSource = V_in

44

Pull-Up and Pull-Down Network• CMOS network consists of a

Pull-UP Network (PUN) and a Pull-Down Network (PDN)

• PUN consists of a set of PMOS transistors

• PDN consists of a set of NMOS transistors

• PUN and PDN implementations are complimentary to each other– PMOS NOMS– Series topology Parallel

topology

….I0I1

In-1

OUPTUT

Vdd

PUN

Gnd

PDN

55

PUN/PDN of a CMOS Inverter

A B0 11 Z

A B0 Z1 0

A B0 11 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Vdd

A

Gnd

B

CMOS Inverter

66

Gate Symbol of a CMOS InverterVdd

A

Gnd

B

CMOS Inverter

A B

B = Ā

77

PUN/PDN of a NAND GateA B C0 0 10 1 11 0 11 1 Z

A B C0 0 Z0 1 Z1 0 Z1 1 0

Pull-UpNetwork

Pull-DownNetwork

Vdd

A

B

A B

C

88

PUN/PDN of a NAND GateA B C0 0 10 1 11 0 11 1 Z

A B C0 0 Z0 1 Z1 0 Z1 1 0

A B C0 0 10 1 11 0 11 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Vdd

A

B

A B

C

99

NAND Gate Symbol

A B C0 0 10 1 11 0 11 1 0

Vdd

A

B

A B

C

A

B

C

Truth Table

BAC

1010

PUN/PDN of a NOR GateA B C0 0 10 1 Z1 0 Z1 1 Z

A B C0 0 Z0 1 01 0 01 1 0

Pull-UpNetwork

Pull-DownNetwork

Vdd

A

C

B

A B

1111

PUN/PDN of a NOR GateA B C0 0 10 1 Z1 0 Z1 1 Z

A B C0 0 Z0 1 01 0 01 1 0

A B C0 0 10 1 01 0 01 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

A

C

B

A B

Vdd

1212

NOR Gate Symbol

A B C0 0 10 1 01 0 01 1 0

A

B

C

Truth Table

A

C

B

A B

BAC

Vdd

1313

How about an AND gateVdd

A

B

AVdd

Gnd

C

NAND

Inverter

B

C = A B

A

B

C

1414

An OR Gate

A

B

A B

Vdd

Vdd

Gnd

C

InverterNOR

A

B

C

BAC

1515

What’s the Function of the following CMOS Network?

A B C0 0 Z0 1 11 0 11 1 Z

A B C0 0 00 1 Z1 0 Z1 1 0

A B C0 0 00 1 11 0 11 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Function = XORXOR

Vdd

A

B

A

A

A

B

B

B

C

1616

Yet Another XOR CMOS NetworkVdd

A

B

A A

A

B

BB

C

A B C0 0 Z0 1 11 0 11 1 Z

A B C0 0 00 1 Z1 0 Z1 1 0

A B C0 0 00 1 11 0 11 1 0

Pull-UpNetwork

Pull-DownNetwork

CombinedCMOSNetwork

Function = XORXOR

1717

Exclusive-OR (XOR) GateVdd

A

B

A A

A

B

BB

C

A B C0 0 00 1 11 0 11 1 0

A

B

C

Truth Table

BABABAC

1818

How about XNORXNOR Gate

A B C0 0 10 1 01 0 01 1 1

A

B

C

Truth Table

BABABAC

How do we draw thecorresponding CMOS networkgiven a Boolean equation?

1919

How about XNORXNOR Gate

A B C0 0 10 1 01 0 01 1 1

A

B

C

Truth Table

BABAC

Vdd

A

B

A A

A

B

BB

C

Vdd

XOR

Inverter

2020

A Systematic Method (I)Start from Pull-Up Network• Each variable in the given Boolean eqn

corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN

• Draw PUNPUN using PMOS based on the Boolean eqn– ANDAND operation drawn in seriesseries– OROR operation drawn in parallelparallel

• Invert each variablevariable of the Boolean eqn as the gate input for each PMOS in the PUN

• Draw PDNPDN using NMOS in complementary form– Parallel (PUN) to series (PDN)– Series (PUN) to parallel (PDN)

• Label with the same inputs of PUN• Label the output

2121

A Systematic Method (II)Start from Pull-Down Network

• Each variable in the given Boolean eqn corresponds to a PMOS transistor in PUN and an NMOS transistor in PDN

• Invert the Boolean eqn • With the Right-Hand Side of the newly inverted

equation, Draw PDNPDN using NMOS– ANDAND operation drawn in seriesseries– OROR operation drawn in parallelparallel

• Label each variablevariable of the Boolean eqn as the gate input for each NMOS in the PDN

• Draw PUNPUN using PMOS in complementary form– Parallel (PUN) to series (PDN)– Series (PUN) to parallel (PDN)

• Label with the same inputs of PUN• Label the output

2222

Systematic Approaches• Note that both methods lead to exactly the

same implementation of a CMOS network• The reason to invert Output equation in (II) is

because– Output (F) is conducting to “ground”, i.e. 0, when

there is a path formed by input NMOS transistors– Inversion will force the desired result from the

equation• Example

– F=Ā·C + B: When (A=0 and C=1) or B=1, F=1. However, in the PDN (NMOS) of a CMOS network, F=0, i.e. an inverse result.

– Revisit how a NAND CMOS network is implemented

• Inverting each PMOS input in (I) follow the same reasoning

2323

Example 1 (Method I)

BCAF In series

In parallelVdd

(1) Draw the Pull-Up Network

2424

Example 1 (Method I)

BCAF In series

In parallelVdd

(2) Assign the complemented input

A

C

B

2525

Example 1 (Method I)

BCAF In series

In parallelVdd

(3) Draw the Pull-Down Network in the complementary form

A

C

B

A C

2626

Example 1 (Method I)

BCAF In series

In parallelVdd

(3) Draw the Pull-Down Network in the complementary form

A

C

B

A C

B

2727

Example 1 (Method I)

BCAF In series

In parallelVdd

Label the output F

A

C

B

A C

B

F

2828

Example 1 (Method I)

BCAF In series

In parallelVdd

A

C

B

A C

B

FA B C F0 0 0 00 0 1 00 1 0 10 1 1 11 0 0 11 0 1 01 1 0 11 1 1 1

Truth Table

2929

Drawing the Schematic using Method II

BCAF

BC)A(F

BCA F

BCAF

Vdd

A

C

B

A C

B

F

This is exactly the same CMOS network with the schematic by Method I

3030

An Alternative for XNOR Gate (Method I)

A B C0 0 10 1 01 0 01 1 1

A

B

C

Truth Table

BABAC

Vdd

A

B

A

B

A

A B

B

C

3131

Example 3)C(ABDAF

Start from the innermost term

A

B D

AC

A D

3232

Example 3)C(ABDAF

Start from the innermost term

A

B D

AC

A D

A

C

3333

Example 3)C(ABDAF

Start from the innermost term

A

B D

AC

A D

A

CB

3434

Example 3)C(ABDAF

Start from the innermost term

A

B D

AC

A D

A

CB

Vdd

F

Pull-Up Network

Pull-DownNetwork

3535

Example 4))C(ABDA()D(EF

Start from the innermost termA

B D

AC

A D

A

CB

Vdd

F

E D

E

D

Pull-DownNetwork

Pull-UpNetwork

3636

Another Example

BCAF How ??