9. Bipolar VLSI Process Integration 9.1 Introduction The bipolar junction transistor (BJT) is the second most important type of active device in VLSI circuits. However, it is the first semiconductor device to become practical even though the concept of field effect transistor was invented before the concept of bipolar transistors was invented. It consists of two p-n junctions that are positioned within ~0.5µm of each other. The device operation is based on minority carrier injection from emitter to base. For npn transistors, electrons are injected from the n-type emitter into the p-type base and become minority carriers in the p-type base. (Electrons have to overcome the energy barrier of the emitter-base junction. This is achieved by forward-biasing the emitter base junction, resulting in a reduction of the energy barrier of the emitter-base junction. In other words, electrons have to overcome the built-in electric field of the emitter-base junction which is in a direction opposing electrons. This is achieved by forward-biasing the emitter base junction, resulting in a reduction of the electric field of the emitter-base junction.) Since the base is very thin, electrons can go through it and reach the n-type collector. (Electrons slide down the energy barrier of the base-collector junction. In other words, the built-in electric

field of the base-collector junction is in a direction helping electrons to move.) (Note: MOS field effect transistors became practical after bipolar transistors.)

Historically, Ge bipolar transistors were manufactured first before Si bipolar transistors. One method to make Ge transistors is to put one piece of indium on top and another piece of indium below a piece of n-type Ge. Then it is heated such that indium alloys with Ge and

dopes it p-type, resulting in a pnp Ge transistor. Usable Ge transistors can be made by very crude methods because of a longer minority carrier diffusion length compared to Si. For Si, the base has to be narrower than that for Ge transistors because of a smaller minority carrier diffusion length. It is difficult to pattern the narrow base region by optical lithography. However, diffusion or ion implantation can easily realize the necessary base thickness. Thus, the Si-based BJTs (unlike Si-based MOSFETs) have a vertical geometry.

Discrete bipolar transistors are quite frequently made as the double diffused epitaxial transistors. For npn transistors, a lightly doped n-type collector is needed for high breakdown voltage. A heavily doped n-type substrate is needed to reduce collector series resistance. A very heavily doped n-type emitter and a very thin p-type base are needed for high current gain. Similarly, for pnp transistors, a lightly doped p-type collector is needed for high breakdown voltage. A heavily doped p-type substrate is needed to reduce collector series resistance. A very heavily doped p-type emitter and a very thin n-type base are needed for high current gain. However, for pnp transistors, the lightly doped p-type collector under protective silicon dioxide may invert because of positive charges in the oxide, etc. A possible solution is by the use of a heavily doped p-type guard ring.

n++

p+

n-

n+

B E

C

p++

n+

p-

p+

B E

C

p+ p+

guard ring

Bipolar integrated circuits are made in a way different from discrete bipolar transistors because of the need of isolating devices from each other. Since electron mobility is higher than hole mobility, npn transistors tend to be faster than pnp transistors. Because of this, bipolar integrated circuits are based on npn transistors instead of pnp transistors. Bipolar VLSI devices are categorized by the type of isolation used: 1. p-n junction isolated (This is achieved by starting

from a lightly doped p-type substrate. Boron diffusion is done to surround the devices with a p-type region. The p-type region including the p-type substrate is electrically connected to the most negative point of the circuit such that the n-type collector to p-type substrate pn junction is always reverse biased.)

2. oxide isolated The standard buried collector (SBC) is the most important junction-isolated BJT structure.

9.2 Standard Buried Collector Process A SBC bipolar transistor consists of a heavily doped n+ collector layer buried beneath an n-type epitaxial layer. The buried layer reduces the resistance of the collector, which must be contacted from the wafer top. Adjacent SBC transistors are isolated by diffused p type perimeter regions which extend right through the epi-layer to the substrate.

A seven mask process is normally used to make SBC transistors. 9.2.1 Starting substrate This is usually a lightly doped (1015cm-3) <111> or <100> p type wafer. 9.2.2 Buried collector formation The buried collector or subcollector is usually formed by growing an oxide layer and wet etching this after lithography to form an oxide window. Arsenic or antimony is introduced through the mask window by diffusion or ion-implantation (~1015cm-3, 30keV). As or Sb are used as dopants because of their high solid solubility in Si and their small diffusion coefficients. Subcollector formation

Following n+ doping, the oxide mask is stripped and the wafer is annealed in an oxidizing ambient to: 1. drive-in the dopants to the desired depth and 2. form a new layer of oxide on the silicon. Since the silicon in the n+-regions oxidizes faster than the lightly doped p-regions, 0.1-0.2µm steps are created on the silicon surface following oxide stripping. These steps outline the edges of the subcollector regions and serve as alignment marks for other device features.

9.2.3 Epilayer Growth After HCl cleaning, a 1-10µm layer of n-type epitaxial silicon (1015-1016cm-3) is grown to bury the subcollectors. (Note: For a quartz tube furnace, HF gas cannot be used because it can etch quartz and so HCl gas is used. Actually HF solution is used to remove oxide first and then the wafers are loaded into the epitaxy chamber. Inside the epitaxy chamber, HCl gas is used for cleaning.) The epilayer is deposited by thermal decomposition of dichlorosilane at 1050oC or silane at 900-1000oC. (Note: Dichlorosilane SiH2Cl2 is safer than silane SiH4.) The epitaxial deposition is a critical process step because the device p-n junctions are formed within this layer.

9.2.4 Isolation region formation A new layer of oxide is grown on the epilayer. It is patterned by lithography to form a diffusion mask for the isolation regions. Boron is pre-deposited and driven-in by diffusion. In order to have complete isolation of collector regions: • the p+ junction depth be greater than the epilayer

thickness; • the p+ concentration in the diffused regions must be

greater than the donor concentration in the epilayer Otherwise the collectors of various transistors will not be completely isolated from each other.

9.2.5 Deep collector contact formation This optional step is sometimes performed to reduce the collector resistance further. • A mask is used to open a window within the

collector • Phosphorus is diffused to form an n+ plug (or sinker)

over the subcollector. Note: sufficient spacing must be allowed between the collector contact and the base.

9.2.6 Base region formation This is a critical step in the SBC process. • A base mask is used to open up an oxide window

within the collector. • Boron is introduced by diffusion or ion implantation

to form the base. Typical junction depths are 1-3µm. • The wafer is annealed in an oxidizing ambient to

regrow the oxide.

Both the junction depth and doping profile of the base must be tightly controlled to give a high current gain β. a. Base Doping Maximum base concentration is set by the design value of β. Minimum base concentration is determined by punchthrough, small Early voltages and high parasitic base resistance. b. Collector base junction depth Shallow junction depths reduce minority carrier transit time and improve BJT high frequency performance. However, punchthrough can occur if the base collector junction depth is made too shallow. A graded base dopant profile is often used to assist the collection of minority carriers.

9.2.7 Emitter region formation An emitter mask is used to open up an oxide window within the base. The emitter is formed by arsenic diffusion or ion-implantation (~1020cm-3) through an oxide opening. A high arsenic dose is necessary to give a high emitter injection efficiency and hence high β. The emitter region should lie entirely within the base and the emitter-base junction depth should be precisely controlled. Typical junction depths are 0.5-2.5µm. A drive-in step performed in an oxidizing ambient regrows an oxide layer.

9.2.8 Contact and interconnect layer The oxide layer is patterned into contact holes using a mask. Since the contact hole must lie within the emitter, it is the smallest feature of the device.

Metallization (1µm thick) consisting of Ti:W and Al is sputter deposited and patterned with another mask. The completed circuit is passivated with a nitride layer. This is patterned with bond pads for wire bonding. (Note: TiW or TiN is used to prevent Al junction spiking.)

9.3 Limitations of the SBC-BJT process 1. The completed SBC-BJT is relatively large. This is due to the non-self-aligned nature of the process. There are cumulative mask alignment tolerances as well as dopant diffusion and depletion layer spreads. In fact, the active part of the SBC transistor is only ~5% of the total silicon area occupied by the device. 2. Large parasitic capacitance, CBC and Cc-sub giving longer switching delay. 3. Large base resistance leading to increased power dissipation for the same logic swings. Consequence: The SBC transistor is not used for high-density digital circuits. Its applications are mainly limited to analog, power ICs.

Bipolar IC structure with buried collector and junction isolation

Bipolar integrated circuit

Basic bipolar IC process

Start from p-Si substrate → isolation

From n+ buried layer → lower collector series resistance

Grow n- epitaxial layer → high breakdown voltage • • •

Isolation : ∆ Junction isolation: p diffusion ∆ Oxide isolation: LOCOS

To further reduce collector series resistance

n-

p

B E

n++

p+ p p

C

n+

n+

p-Si region connected to the most –ve point of the circuit

C

n-

p n+

n+

As+ or Sb+

n+

Before entering the epitaxy chamber, dilute HF can be used to remove oxide on Si wafers. Inside the epitaxy chamber, HCl gas is used to remove oxide before Si epitaxy. HF cannot be used because it can attack quartz.

n+

drive in on oxidizing ambient

Alignment marks in scribe line (important for alignment)

n+

Oxide grows faster on n+-Si

Step

n+

Etch in dilute HF to remove oxide

Inside the epitaxial growth chamber

HF will attack the quartz tube. Use a high temp HCl clean inside the epitaxial growth chamber HCl hydrogen chloride gas (Insitu HCl clean)

There are more than one choice for the precursor. Dichlorosilane is the safer gas compare to silane. Double diffusion is used to form base and emitter. Diffused-base transistor has a drift field in the base which can speed up the transistor. The drift field originates from the non-uniform doping in the base. History: The early Ge transistors started with a piece of uniformly doped n-Ge with the emitter & collector formed by alloying In onto Ge to form a pnp transistor. The base is uniformly doped and so there is no drift field. Bipolar transistors with drift field were a big invention several decades ago.

SiH4 silane SiH2Cl2 dichlorosilane

Si

H

H

H

H

Si

H

Cl

Cl

H

Si-H weak

Si-Cl stronger

Silane is pyrophoric (explode spontaneously)

Dichlorosilane is the safer gas

E +ve

n- n+ n+ p

Small field due to non-uniform doping in the base

Electric field Forward bias

Reverse bias

This small field can speed up the transistor by

X2 – X5

Contact formation: Al contacts may have junction spiking problem. Possible solutions:

A. Add Si to Al B. Use a diffusion barrier such as TiW or TiN behaves like a metal and is the better diffusion barrier

compared to TiW. Oxide isolation is the better isolation technology compared to junction isolation

Junction isolation

Oxide isolation

B

450°C 30 min H2/N2 anneal is used to break through the very thin oxide between Al & Si. →Junction spiking

p+

n++

Diffusion barrier: • TiW • TiN

Al

p

n

Al

Junction isolation: Boron diffuses both downwards and also sideways. In this way, space has to be allowed for sideway diffusion of boron. In addition, the depletion region extends into the lightly doped n-type epi region. Space has to be allowes for this also. There is also parasitic capacitance with the pn junction associated with junction isolation Oxide isolation: Advantages:

A. Higher packing density B. Less parasitic capacitance

smaller