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BASICCONSTRUCTS&

CONVENTIONSOFVERILOGHDL

By-

Abhinav Vishnoi

Assistant Professor

Lovely Professional University

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LEXICALCONVENTIONS

The basic lexical conventions used by Verilog HDL are

similar to those in the C programming language.

Verilog HDL is a case-sensitive language. All keywords

are in lowercase.

Blank spaces (\b)

Newlines (\n)

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COMMENTS

Comments can be inserted in the code for readability anddocumentation.

There are two ways to write comments.

A one-line comment starts with "//". Verilog skips from that

point to the end of line. A multiple-line comment starts with "/*" and ends with "*/".

For Example-

a = b && c; // This is a one-line comment

/* This is a multiple line comment */

/* This is /* an illegal */ comment */ /* This is //a legalcomment */

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OPERATORS

Operators are of three types: unary, binary, and ternary.

o Unary operators precede the operand.

o Binary operators appear between two operands.

o Ternary operators have two separate operators thatseparate three operands.

For Example-

a = ~ b; // ~ is a unary operator. b is the operand

a = b && c; // && is a binary operator. b and c are

operands

a = b ? c : d; // ?: is a ternary operator. b, c and d areoperands

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NUMBERSPECIFICATION

There are two types of number specification in Verilog:

sized and unsized.

o Sized numbers

Sized numbers are represented as '

is written only in decimal and specifies the

number of bits in the number.

Example-o 4'b1111 // This is a 4-bit binary number

o 12'habc // This is a 12-bit hexadecimal number

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Unsized numbers

o Numbers that are specified without a

specification are decimal numbers by default.

Example- 23456 // This is a 32-bit decimal number by default

'hc3 // This is a 32-bit hexadecimal number

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X ORZ VALUES

Verilog has two symbols for unknown and high

impedance values. These values are very important for

modelling real circuits. An unknown value is denoted by

an x. A high impedance value is denoted by z.

Example-

6'hx // This is a 6-bit hex number

32'bz // This is a 32-bit high impedance number

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DESIGNMETHODOLOGIES

There are two basic types of digital design

methodologies:

o Top Down design methodology

o

Bottom Up design methodology

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TOPDOWNDESIGNMETHODOLOGY

In a top-down design methodology, we define the top-level

block and identify the sub-blocks necessary to build the top-

level block.

We further subdivide the sub-blocks until we come to leaf

cells, which are the cells that cannot further be divided. Figureshows the top-down design process.

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BOTTOMUPDESIGNMETHODOLOGY

In a bottom-up design methodology, we first identify the

building blocks that are available to us.

We build bigger cells, using these building blocks. These

cells are then used for higher-level blocks until we build

the top-level block in the design. Figure shows the bottom-up design process.

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4-BITRIPPLECARRYCOUNTER

The ripple carry counter shown in Figure-

It is made up of negative edge-triggered toggle flip-flops(T_FF).

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T_FFs can be made up from negative edge-triggered

D-flipflops (D_FF) and inverters (assuming q_bar

output is not available on the D_FF), as shown in

Figure

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Thus, the ripple carry counter is built in a hierarchical

fashion by using building blocks. The diagram for the

design hierarchy is shown in Figure-

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PORTS

Ports provide the interface by which a module can

communicate with its environment.

For example, the input/output pins of an IC chip are its

ports.

Ports can be of three types

Input port (Verilog Keyword is input)

Output port (Verilog Keyword is output) Inout port (Verilog Keyword is inout)

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PORTCONNECTIONRULES

Inputs

Internally, input ports must always be of the type net. Externally, theinputs can be connected to a variable which is a reg or a net.

Outputs

Internally, outputs ports can be of the type reg or net. Externally,outputs must always be connected to a net. They cannot beconnected to a reg.

Inouts

Internally, inout ports must always be of the type net.

Externally, inout ports must always be connected to a net.

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MODULEINSTANTIATION

A module can be instantiated in another module

Syntax:

module_name instance_name (port_associations);

Port Associations can be by position or by name; however;associations cannot be mixed

Syntax:

port_expr // By position

.PortName (port_expr) // By Name

In positional association in the specified order (MUST)

In association by name order of port associations is not important

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MODULEINSTANTIATION(2)

Example:

moduleHA (A, B, S, C);

inputA, B;

outputS, C;parameterAND_DELAY=1, XOR_DELAY=2;

assign#XOR_DELAY S = A ^ B;

assign#AND_DELAY C = A & B;

endmodule

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MODULEINSTANTIATION(3)

moduleFA ( P, Q, Cin, Sum, Cout);

inputP, Q, Cin;

outputSum, Cout;

parameterOR_DELAY=1;

wireS1, C1, C2;

HA h1( P, Q, S1, C1);

// Associating by position

HA h2 (.A(Cin), .S(Sum), .B(S1), .C(C2) );

// Associating by name// Gate instantiation

or#OR_DELAY 01(Cout, C1, C2);

endmodule

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MODULEINSTANTIATION(4)

Unconnected Ports Unconnected ports in an instantiation can be specified by

leaving the port expression blank

Example:

DFF d1(.Q(QS), .Qbar(), .Data(D), .Preset(), .Clock(CK));

//By name

DFF d2(QS, , D, , CK);

// By position

// OutputQbar

is not connected

NOTE: Unconnected module inputs are driven to value z.Unconnected module outputs are simply unused

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