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Introduction to VHDL

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Lecture overview An introduction to VHLD

At the structural level

At the mixed level

At the behavioral level

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Overview HDLHardware Description Language

A language that allows description of hardware fordocumentation, simulation, synthesis, verification,

To use an HDL you need a CAD system that supports it.

Major CAD systems support VHDL, Verilog, System C,System Verilog

CAD systems (just some of them) CadenceIncisive

Mentor Graphics (Model Sim)ModelSim, Questa Altera, XILINX

SynopsisMainly toward synthesis and production from HDLdescriptions

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Common to all systems Have source HDL file

Structure of generated files is common

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Source Files

VHDLLibrary Files

Analysis(Compile)

Simulation Synthesis

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A First Example Desire to do a VHDL description of a full adder.

A device consists of

An Interface

An operational part

InterfaceThe INPUTS AND OUTPUTS Operational PartThe FUNCTIONAL

BEHAVIOR

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VHDL Entity Design Unit Form ENTITY unit_name IS

[port_clause]

END unit_name;

For a full adder would have: ENTITY full_adder IS

PORT(a,b,cin : IN bit;

sum : OUT bit;

cout : OUT bit);

END full_adder;

The PORT portion is termed a Port Clause When specified in the port clause these signals have scope over all

architectures of this entity

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Signals/Port Modes/Types PORT(a,b,cin:IN bit; sum:OUT bit; cout: OUT bit);

Signals: Names referenced in the Port Clause aresignals.

A,b,cin,sum,cout represent wires of the physical unit.

SIGNALS are objects that have both a value and a timecomponent.

Port Modes: In this example you have inputs and

outputs. The Port Mode specifies the direction of thesignal transfer and a couple of other properties of theport.

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Signals/Port Modes/Types Modes:

INsignal can only be used (i.e., can only be read or canonly be used on the right-hand-side of an equation).CANNOT BE ASSIGNED TO!!

OUTsignal value can only be written. Cannot be seenor used in the design as it is an output and thereforeexternal.

INOUTsignal can be both written to (assigned to) andread (used). However, signals of thie type are connectedto busses and therefore this signal mode requires thesignal to be resolved.

BUFFERsignal value can be written to and usedinternally in the design.

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Basic Types Built inpart of the standard and the language proper.

TYPE BITyour typical binary type with values of0 and 1.

Declaration that established this type TYPE BIT is (0, 1);

Use of SIGNALS of TYPE bit

a

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Architectural Design Unit

Specifies the operational part

ARCHITECTURE identifierOF entity_id IS

[declarations] BEGIN

[architecture_statement_part]

END [identifier];

[architecture_statement_part]Any concurrentstatement of the language

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Example of Architecture

For a full adder

ARCHITECTURE one OF fulladder IS

BEGIN sum

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Consider a 4 bit Adder

This hardware is to modeled in VHDL

First will do a dataflow model for the unit as a

whole. Will create two alternative dataflow models. Then will create a structural model where the leaf

units are basic gates.

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A0A1A2A3 B1 B0B3 B2

SUM0SUM1SUM2SUM3

CinCout

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A Multibit Adder Example

Will model using a dataflow style

Bit Vectors for ports and individual signals internally

Bit Vectors for ports and bit vectors internally

The Entity Design Unit (same for both)

ENTITY mb_adder IS

PORT(a,b : IN bit_vector(3 downto 0);

cin : IN bit; cout : OUT bit; sum : OUT bit_vector(3 downto 0));

END mb_adder;

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The first dataflow Architecture ARCHITECTURE one OF mb_adder IS

SIGNAL c : BIT_VECTOR (4 downto 0);

BEGIN

c(0)

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The Second Dataflow Architecture ARCHITECTURE two OF mb_adder IS

SIGNAL c : BIT_VECTOR (4 downto 0);

BEGIN

c(0)

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Operations on Type BIT Consider the following declaration

SIGNAL x,y : bit;

Logical Operations x AND y Also have shift operations

x OR y arithmetic shifts ASR ASL

x NAND y

x NOR y logical shifts LSR LSL

x XOR y

x XNOR y these work on vectors NOT y

NOTE: For logical expressions the equation is onlyevaluated until the result is determined.

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Assignment and Relational Operators

Assignment Operators

For signal

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Structural Example Again consider the full adder

Before doing a structural description must have the components thatare going to be wired together. These must first be written andcompiled into the library.

Only the ENTITIES are given. Each would have an architecture. ENTITY and2 IS

PORT (A,B : IN BIT; Z : OUT BIT);

END and2;

ENTITY xor2 IS

PORT (A,B : IN BIT; Z : OUT BIT); END xor;

ENTITY or3 IS

PORT (A,B,C : IN BIT; Z : OUT BIT);

END or3;

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Structural Example for a full adder The first part

ARCHITECTURE structural OF full_adder IS

-- Must declare the components that are to be used

COMPONENT and2

PORT (A,B : IN BIT; Z : OUT BIT);

END COMPONENT ;

COMPONENT xor2

PORT (A,B : IN BIT; Z : OUT BIT);

END COMPONENT ;

COMPONENT or3

PORT (A,B,C : IN BIT; Z : OUT BIT);

END COMPONENT ;

-- State which library to find them in and which architecture to use.

FOR ALL : and2 USE ENTITY WORK.and2(behavioral);

FOR ALL : xor2 USE ENTITY WORK.xor2(behavioral);

FOR ALL : or3 USE ENTITY WORK.or3(behavioral);

-- Declare local signals required.

SIGNAL addt. ct1, ct2, ct3 : BIT;

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The second part of the Architecture From the BEGIN

BEGIN

G1: xor2 PORT MAP(a,b,addt);

G2: xor2 PORT MAP(addt, cin, sum);

G3: and2 PORT MAP(a,b,ct1);

G4: and2 PORT MAP(a,cin,ct2);

G5: and2 PORT MAP(b,cin,ct3);

G6: or3 PORT MAP(ct1,ct2,ct3,cout);

END Structural;

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Multibit adder

Can use the structural full adder to wire up amultibit adder

The ENTITY Design Unit

ENTITY mb_adder IS

PORT (a,b : IN BIT_VECTOR(3 downto 0);

cin : IN BIT; cout : OUT BIT;

sum: OUT BIT_VECTOR(3 downto 0)); END mb_adder;

Entity is the same as before

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The multibit Architecture ARCHITECTURE structural OF mb_adder IS

-- Must declare the components that are to be used

COMPONENT full_adder

PORT( a,b,cin : IN BIT;

sum : OUT BIT;

cout : OUT BIT);

END COMPONENT;

FOR ALL full_adder USE ENTITY work.full_adder(structural);

SIGNAL ic1,ic2,ic3 BIT;

BEGIN

U0: full_adder(a(0),b(0),cin,ic1,sum(0)):

U1: full_adder(a(1),b(1),ic1,ic2,sum(1)):

U2: full_adder(a(2),b(2),ic2,ic3,sum(2)):

U3: full_adder(a(3),b(3),ic3,cpit,sum(3)):

END structural;

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