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ystem ressRegisters/Memory

Management Registers Four memory management registersare used to specify the locations ofdata structures which control

segmented memory management. These registers are:

GDTR (Global Descriptor Table Register)

IDTR (Interrupt Descriptor TableRegister)

DTR ( ocal Descriptor Table Register)

TR (Tas! Register) "

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GDTR and IDTR

GDTR and IDTR can be loaded withinstructions which get a 6 byte dataitem from memory

#

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LDTR and TR

DTR and TR can be loaded withinstructions which ta!es a "$%bit

segment selector as an operand.

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LDTR and TR

The remaining bytes of theseregisters are then loaded

automatically by the processor fromsegment descriptor referenced bythe operand.

Descriptor Registers are not 'isible

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Debug Registers

Debugging of *& $ allows dataaccess brea!points as well as codeexecution brea!points.

*& $ contains $ debug registers tospecify brea!points +rea!point ,ontrol options +rea!point -tatus

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Debug Registers

$

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Linear Brea pointAddress Registers

The brea!point addresses speci edare %bit linear addresses

/hile debugging0 Intel & $ h1wcontinuously compares the linearbrea!point addresses in DR*%DR&with the linear addresses generatedby e2ecuting software.

3

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Debug !ontrol Register

L"# i(i4* % &): +rea!point ength-peci cation +its: # bit eld for each brea!point -peci es length of brea!point

elds The choices of data brea!points

are "byte0 #bytes 5 bytes

For instruction e2ecution

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L"# i "ncoding

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Debug !ontrol Register

R$ i(i4* % &): 6emory 7ccess

8uali er +it # bit eld for each brea!point -peci es the type of usage which

must occur inorder to acti'ate theassociated brea!point

"*

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Debug Registers

""

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Debug !ontrol Register

GD : Global Debug Register 7ccess

Detect Debug registers can only be

accessed in real mode or at

pri%ilege le%el & in protectedmode GD bit0 when set0 pro'ides e2tra

protection against any DebugRe ister access e'en in Real 6ode

"#

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Debug !ontrol Register GD : Global Debug Register 7ccessDetect

This additional protection feature ispro'ided to guarantee that a so't(aredebugger can ha'e full control o'erthe Debug Register resources whenre uired.

The GD bit0 when set0 causes anexception ) fault if an instructionattempts to read or write any DebugRegister.

The GD bit is then automatically cleared"&

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Debug !ontrol Register

G" and L" bit : ;2act data

brea!point match0 global and local If either GE or LE is set, any data breakpoint trap willbe reported exactly after completion of the instructionthat caused the operand transfer.

LE bit is cleared during task switch and is used fortask-local breakpoints.

GE bit is unaffected during a task switch andremain enabled durin all tasks executin in the

system. "

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Debug !ontrol Register

G i and Li(i4* % &): +rea!point ;nable0

global and local If either G i and i is set then the

associated brea!point is enabled.

"