Lecture 1 Introduction -...

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ECE611 / CHE611 – Electronic Materials Processing

Fall 2017 - John Labram

Lecture 1

Introduction

Prologue - Wolf and Tauber

Thursday 21st September 2017

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Electronic Materials Processing• The success of semiconductor technology has undoubtedly

been one of humankind's greatest achievements.

• Inexpensive electronics have revolutionised almost every facet

of society.

• We are incredibly lucky that the silicon has the properties it

does, and is the 2nd most abundant element in earth’s crust.

• In 2017 transistors can be purchased at a cost of 10-7 USD /

transistor when part of integrated circuit.

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Electronic Materials ProcessingElectronic Materials Processing is important for many

technologies:

• Integrated Circuits (computer chips, etc.)

• Microelectromechanical systems (accelerometers,

etc.)

• Displays (LCD backplanes, system on glass, etc.)

• Microfluidics (sensors, inkjet, etc.)

• Solar cells (crystalline and amorphous silicon, etc)

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Why do we Care:• Highly applicable knowledge for jobs in the semiconductor

industry.

• Information is useful / necessary for many aspects of your

research.

• It is an interesting subject (hopefully).

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Course Logistics

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Course Logistics

• Instructor: John Labram

Office: 3103 Kelley Engineering Center

e-Mail: [email protected]

Office Hours: Monday 13:00 to 14:00

• Text: Wolf and Tauber, Silicon Processing for the VLSI Era V.1

• Course Information: Website

• Course Grades:

Homework 30%

Midterm Exam 25%

Term Paper 20%

Final Exam 25%

Electronic Materials Processing

Fall 2017

mailto:[email protected]

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• Syllabus

• Course Learning Objectives

• Reading

• Homework

• Exams

• Student Conduct

• Outline

• References

Course LogisticsElectronic Materials Processing

Fall 2017

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Course TimetableLecture Day Date Topic

1 Thursday 09/21/17 Introduction

2 Tuesday 09/26/17 Silicon and CZ Growth

3 Thursday 09/28/17

Vacuum Science &

Technology

4 Tuesday 10/03/17 Cleaning

5 Thursday 10/05/17 Electrochemistry

6 Tuesday 10/10/17 Plasmas

7 Thursday 10/12/17 Oxidation

8 Tuesday 10/17/17 Thin Film Deposition

9 Thursday 10/19/17 Review

10 Tuesday 10/24/17 Mid-term Exam

11 Thursday 10/26/17 Thin Film Deposition

12 Tuesday 10/31/17 Thin Film Deposition

13 Thursday 11/02/17 Diffusion

14 Tuesday 11/07/17 Ion Implantation

15 Thursday 11/09/17 Lithography

16 Tuesday 11/14/17 Lithography

17 Thursday 11/16/17 Etching

18 Tuesday 11/21/17

Chemical Mechanical

Polishing

19 Tuesday 11/28/17 Review

20 Thursday 11/30/17 Final Exam

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Fall 2017

Course Description:

• Technology, theory, and analysis of processing

methods used in integrated circuit fabrication.

• This course is the first course of the semiconductor

materials/process sequence.

• The course provides an overview of the relevant

science and individual process technologies

underlying the manufacture of modern

semiconductor integrated circuits.

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Fall 2017

Course Learning Objectives:

By the end of the course, you will be able to:

1.State the principle mechanisms and key processing issues for the major unit processes in

microelectronics fabrication including: bulk crystal growth, cleaning, diffusion, oxidation, ion

implantation, lithography, etching, chemical mechanical planarization, and thin film deposition.

2. Describe vacuum systems and plasmas in terms of the kinetic theory of gases. Use this

framework to make order of magnitude estimates for microelectronics fabrication systems.

5. Discuss and contrast electronic materials processing technologies using common scientific

conventions.

3. Formulate and solve problems for important parameters in individual unit processes by

applying fundamental engineering analysis including heat transfer, mass transfer,

thermodynamics and reaction kinetics.

4. Compile a literature review of a selected topic in electronic materials processing in a written

report.

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Fall 2017

Textbook:

S. Wolf and R.N. Tauber, Silicon Processing for the VLSI

Era, Vol 1, Ed. 2, Lattice Press: Sunset Beach, CA (2000).

ISBN 0-9616721-6-1

Reading:

• Reading represents a significant amount of out of

class time.

• Assignments for each topic are provided with the

class outline.

• You should read ahead, about the topic that will be

discussed in class.

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Fall 2017

Homework:

• Homework solutions will be posted on the web site for 1 week

after the due date.

• Homework is instrumental in helping you grasp fundamental

concepts and in exposing you to techniques and skills for

applying these principles to real-life situations. These problems

are where the majority of learning is accomplished. • Homework will be posted on the website by Thursday and due

at the beginning of class the following Thursday.

• There will be 4 homeworks in total.

• Any late homework will receive a grade of 0 unless

arrangements are made with the instructor before it is due.

• Failure to turn in more than 2 homework assignments will result

in a grade of F in the class.

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Fall 2017

Homework:

• In preparing your homework solutions, you should

write neatly (or type it up), show all your work, state

any assumptions that you have made and indicate

the units of numerical answers.

• You may discuss homework problems with your

classmates (NOT COPY THE SOLUTIONS), but please

try them on your own first.

• Solutions must be written up independently.

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Fall 2017

Homework:

• For graphical solutions, use graph paper or computer generated plots.

Label the axes of your graph and include units.

Use the following guidelines for homework preparation:

• Use clean, letter / A4 paper. Engineering paper is preferred; neatness is

important and appreciated.

• Write on only one side of the paper, and start a new problem on a new

sheet of paper.

• Write the following in the upper right corner of each page:

CHE 611/ECE 611

Your Name

Due date, Problem Set No.

Page number/Total pages.

• Securely staple all pages; do not fold or paper clip together.

• Show all of your work. Draw a block around your final answer(s).

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Fall 2017

Term Paper:

General information including timelines for topic selection and

outline due date will be provided online. The term paper is due on

Tuesday November 14th at the beginning of class.

Exams:

The midterm exam is scheduled for Tuesday October 24th at

10:00am (80 min.). The final exam is scheduled for noon on

Thursday November 30th at 10:00am (110 min.). There will be

closed and open book portions.

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Fall 2017

Class Attendance:

• Attendance is mandatory.

• You are expected to attend every class.

• If you are not able to make class, notify the instructor before

class.

• Unexcused absences may lower your final course grade.

• If you do miss class, it is your responsibility to find out what was

covered and any administrative information that was presented.

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Fall 2017

Cheating and Student Conduct:

Academic dishonesty is defined as an intentional act of deception

in one of the following areas:

• Cheating- use or attempted use of unauthorized materials,

information or study aids.

• Fabrication- falsification or invention of any information.

• Assisting- helping another commit an act of academic

dishonesty

• Tampering- altering or interfering with evaluation instruments

and documents.

• Plagiarism- representing the words or ideas of another person as

one's own

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Fall 2017

Cheating and Student Conduct:

• When evidence of academic dishonesty comes to the

instructor's attention, the instructor will document the incident,

permit the accused student to provide an explanation, advise

the student of possible penalties, and take action.

• The instructor may impose any academic penalty up to and

including an "F" grade in the course after consulting with his or

her department chair and informing the student of the action

taken.

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Fall 2017

• While the University is a place where the free exchange of ideas

and concepts allows for debate and disagreement, all classroom

behavior and discourse should reflect the values of respect and

civility.

Disruptive Behavior:

• Behaviors which are disruptive to the learning environment will

not be tolerated.

• As your instructors, we are dedicated to establishing a learning

environment that promotes diversity of race, culture, gender,

sexual orientation, and physical disability.

• Anyone noticing discriminatory behavior in this class, or feeling

discriminated against should bring it to the attention of the

instructors or other University personnel as appropriate.

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Fall 2017

Sequence Classes:

ECE 612/ChE 612 Process Integration (3). Process integration,

simulation, and statistical quality control issues related to

integrated circuit fabrication. Offered in Winter 2018.

ECE 613/ChE 613 Electronic Materials and Characterization (3).

Physics and chemistry of electronic materials and methods of

materials characterization. Offered in Spring 2018.

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Course Overview

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Sand to Silicon

http://www.youtube.com/watch?v=d9SWNLZvA8g

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Electronic Materials ProcessingThe Process “loop”:

Processing

Deposition /

OxidationEtching /

CMP

Loop

Photo/

Pattern

Transfer

Cle

an Ion Implant /

AnnealCle

an

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Transistor: MOSWe will illustrate the process sequence with a Metal Oxide

Semiconductor(MOS) transistor.

p-Si

Insulator

n-Si

Source Drain

Gate

n-Si

3/4“

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Integrated Circuits• We can make a network of transistors which are connected to

each other and perform large and complex logic operations.

• The design of ICs will not be covered in ECE 611 / CHE 611. We will focus on

Processing.

NOT:NAND: XOR:

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Integrated Circuits• One chip is made of millions/billions of

transistors. All packed into a length and width

of less than an inch.

Packed Chip Package opened

3/4“

The Chip!

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Integrated Circuits in Pictures

LSI Logic

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IC Manufacturing Process

Customer

Need (design)ChipsProcessing

Wafers

Deposition /

OxidationEtching /

CMP

Loop

Photo/

Pattern

Transfer Cle

an

Cle

an Ion Implant /

Anneal

IC Processing consists of selectively adding material

(Conductor, insulator, semiconductor) to, removing it

from or modifying it on the Si substrate

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Making a Transistor• Starting silicon wafer:

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

Impurities

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Making a Transistor• Clean substrate

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Chemical Vapor Deposition: Si3N4

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

10 NH3(g) + 3SiH2Cl2(g) → Si3N4 (s) + 6NH4 Cl(g) + 6 H2(g)

Si

Si3N4

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Making a Transistor• Spin-coating of photoresist

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

Photoresist

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Making a Transistor• UV-

treatment of

photoresist

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

mask

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Making a Transistor• Photoresist development.

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

The complexity of an IC process is

often defined in terms of the

number of masking steps.

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Making a Transistor• Plasma Etch Si3N4

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Plasma Etch: Strip Photoresist

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Oxidation of Silicon

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

SiO2

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Making a Transistor• Etch Si3N4

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Gate Oxide: Si Oxidation

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Ion implantation:

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

IONS IONSIONS

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Making a Transistor• Anneal:

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

HEAT HEATHEAT

Activate (& diffuse) the dopant

Clean before anneal

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Making a Transistor• Oxidation of silicon

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Plasma Etch: Silicon Oxide

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Deposit interconnects: tungsten CVD.

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

Wafers

Si

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Making a Transistor• Final steps: Cu Electrodeposition and Chemical Mechanical

Planarization

Gate: +

e- e-

Source - Drain: +

Si

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Course Outline

Dep

ositio

n /

Oxid

atio

n

Loo

p

Ph

oto

/

Patte

rn

Tra

nsfe

r

Etch

ing

/

CM

P

Clean

Ion

Imp

lan

t /

An

neal

6. Cleaning 5, 2.5

7. Oxidation 8

8. Thin Film Deposition 6,7,11,15.6,15.8.3

9. Diffusion 9

10. Ion Implantation 10

11. Lithography 12-13

12. Etching 14

13. Chemical Mechanical

Polishing

15.1-15.5

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A More Detailed Look

ProcessingProcessing

Metal through the

pad etch connects

the chip to the

outside world.

SiO2

Si3N4

TiN, W

TiN, Al-Cu, TiN

p-type Si

P-well

SiO2

BPSG

SiO2

TiN, W

Al-Cu, TiN

N-wells

poly-Si

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And a Picture

From www.Intel.com

CMP = Chemical Mechanical Planarization

USG = Undoped Silicate Glass

PSG = Phosphorous Doped Silicate Glass

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Impact

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The First Transistor• Germanium was used in

first transistor.

• Bardeen Brattain

Shockley in 1947.[1]

• Bell labs.

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Record e- Mobility Held by GaAs

http://www.nature.com/nmat/journal/v9/n11/full/nmat2888.html

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Moore’s Law• Suggested in the 1960’s by

Intel’s founder George Moore.

• The number of transistors that

can inexpensively fit onto a

single integrated circuit will

double every 24 months.[1]

• In 2017 transistors can be

purchased at a cost of 10-7 USD

/ transistor when part of

integrated circuit.

[1] G. E. Moore. Cramming More Components onto Integrated Circuits.

Electronics 1965, 38 (9), 114–117.

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Moore’s Law• Remarkably, it has held up for 40 years.

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Moore’s Law• This has been driven by reducing feature size:

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Moore’s Law• This has been driven by reducing feature size:

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Wafer Size

50 mm

1972

300 mm

2002

200 mm

1997

• Increasing wafer size if a big challenge.

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Size of the Industry• Top 10 Semiconductor Vendors by Revenue, Worldwide, 2015

(Millions of Dollars):

http://www.gartner.com/newsroom/id/3182843

Rank 2014 Rank 2015 Vendor2014

Revenue

2015

Estimated

Revenue

2014-2015

Growth (%)

2015 Market

Share (%)

1 1 Intel 52,331 51,709 -1.2 15.5

2 2Samsung

Electronics34,742 38,855 11.8 11.6

5 3 SK Hynix 15,997 16,494 3.1 4.9

3 4 Qualcomm 19,291 15,936 -17.4 4.8

4 5Micron

Technology16,278 14,448 -11.2 4.3

6 6Texas

Instruments11,538 11,533 0 3.5

7 7 Toshiba 10,665 9,622 -9.8 2.9

8 8 Broadcom 8,428 8,419 -0.1 2.5

9 9STMicroelectr

onics7,376 6,890 -6.6 2.1

12 10Infineon

Technologies5,693 6,630 16.5 2

Others 157,992 153,182 -3 45.9

Total 340,331 333,718 -1.9 100

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