Lecture 1: Introduction Original Lecture notes © 2010 David Money Harris Modified by Konstantinos...

Lecture 1: Introduction

Original Lecture notes © 2010 David Money Harris

Modified by Konstantinos Tatas

1: Introduction 2ACOE419 – Digital IC and VLSI Design

ACOE419 – Digital IC and VLSI Design

ECTS: 5 Conduct hours per week: 3 (2 Lecture – 1 Lab) Evaluation:

– Final Exam: 60%– Laboratory exercises: 20%– Test: 10%– Assignment: 10%


Course outline and breakdown

Week 1:– Introduction to VLSI Design

Week 2:– Stick diagrams and layout– Lab 1: Basic schematic entry

Week 3:– The ideal MOS transistor– Lab 2: Compound gates

Week 4:– The non-ideal MOS transistor– Lab3: Basic Layout



Week 5:– Logical Effort– Lab 4: Advanced Layout

Week 6:– Power Consumption – Lab 5: MOS transistor characteristics

Week 7:– Test– Lab 6: Logical Effort

Week 8:– Simulation– Lab 7: Power Consumption



Week 9:– Combinational Circuit Design – Lab 8: Power Consumption

Week 10:– Wires– Lab 9: Combinational Circuit Design

Week 11:– Sequential Circuit Design– Lab 10

Week 12:– Adder Design– Lab 11


Introduction Integrated circuits: many transistors on one chip. Very Large Scale Integration (VLSI): bucketloads! Complementary Metal Oxide Semiconductor

– Fast, cheap, low power transistors Today: How to build your own simple CMOS chip

– CMOS transistors– Building logic gates from transistors– Transistor layout and fabrication

Rest of the course: How to build a good CMOS chip


A Brief History 1958: First integrated circuit

– Flip-flop using two transistors– Built by Jack Kilby at Texas

Instruments 2010

– Intel Core i7 processor • 2.3 billion transistors

– 64 Gb Flash memory • > 16 billion transistors

Courtesy Texas Instruments

[Trinh09]

© 2009 IEEE.


Growth Rate

53% compound annual growth rate over 50 years– No other technology has grown so fast so long

Driven by miniaturization of transistors– Smaller is cheaper, faster, lower in power!– Revolutionary effects on society

[Moore65]

Electronics Magazine


Annual Sales >1019 transistors manufactured in 2008

– 1 billion for every human on the planet


Invention of the Transistor Vacuum tubes ruled in first half of 20th century Large,

expensive, power-hungry, unreliable 1947: first point contact transistor

– John Bardeen and Walter Brattain at Bell Labs– See Crystal Fire

by Riordan, Hoddeson

AT&T Archives. Reprinted with

permission.


Transistor Types Bipolar transistors

– npn or pnp silicon structure– Small current into very thin base layer controls

large currents between emitter and collector– Base currents limit integration density

Metal Oxide Semiconductor Field Effect Transistors– nMOS and pMOS MOSFETS– Voltage applied to insulated gate controls current

between source and drain– Low power allows very high integration


1970’s processes usually had only nMOS transistors– Inexpensive, but consume power while idle

1980s-present: CMOS processes for low idle power

MOS Integrated Circuits

Intel 1101 256-bit SRAM Intel 4004 4-bit Proc

[Vadasz69]

© 1969 IEEE.

Intel Museum.

Reprinted with permission.


Moore’s Law: Then 1965: Gordon Moore plotted transistor on each chip

– Fit straight line on semilog scale– Transistor counts have doubled every 26 months

Integration Levels

SSI: 10 gates

MSI: 1000 gates

LSI: 10,000 gates

VLSI: > 10k gates[Moore65]

Electronics Magazine


And Now…


Feature Size

Minimum feature size shrinking 30% every 2-3 years


Corollaries Many other factors grow exponentially

– Ex: clock frequency, processor performance


Silicon Lattice Transistors are built on a silicon substrate Silicon is a Group IV material Forms crystal lattice with bonds to four neighbors

Si SiSi

Si SiSi

Si SiSi


Dopants Silicon is a semiconductor Pure silicon has no free carriers and conducts poorly Adding dopants increases the conductivity Group V: extra electron (n-type) Group III: missing electron, called hole (p-type)

As SiSi

Si SiSi

Si SiSi

B SiSi

Si SiSi

Si SiSi

-

+

+

-


p-n Junctions A junction between p-type and n-type semiconductor

forms a diode. Current flows only in one direction

p-type n-type

anode cathode


nMOS Transistor Four terminals: gate, source, drain, body Gate – oxide – body stack looks like a capacitor

– Gate and body are conductors

– SiO2 (oxide) is a very good insulator

– Called metal – oxide – semiconductor (MOS) capacitor

– Even though gate is

no longer made of metal

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+Body


nMOS Operation Body is usually tied to ground (0 V) When the gate is at a low voltage:

– P-type body is at low voltage– Source-body and drain-body diodes are OFF– No current flows, transistor is OFF

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

0

S


nMOS Operation Cont. When the gate is at a high voltage:

– Positive charge on gate of MOS capacitor– Negative charge attracted to body– Inverts a channel under gate to n-type– Now current can flow through n-type silicon from

source through channel to drain, transistor is ON

n+

p

GateSource Drain

bulk Si

SiO2

Polysilicon

n+D

1

S


pMOS Transistor Similar, but doping and voltages reversed

– Body tied to high voltage (VDD)

– Gate low: transistor ON– Gate high: transistor OFF– Bubble indicates inverted behavior

SiO2

n

GateSource Drain

bulk Si

Polysilicon

p+ p+


Power Supply Voltage GND = 0 V In 1980’s, VDD = 5V

VDD has decreased in modern processes

– High VDD would damage modern tiny transistors

– Lower VDD saves power

VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …


Transistors as Switches We can view MOS transistors as electrically

controlled switches Voltage at gate controls path from source to drain

g

s

d

g = 0

s

d

g = 1

s

d

g

s

d

s

d

s

d

nMOS

pMOS

OFF ON

ON OFF


0

VDD

A Y

GND

CMOS Inverter

A Y

0 1

1 0

A Y

OFF

ON 1

ON

OFF


CMOS NAND Gate

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

OFFOFF

ON

ON

1

1

OFFON

OFF

ON

0

1

ON OFF

ON

OFF

1

0

ON ON

OFF

OFF

0

0A

B

Y


CMOS NOR Gate

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

A

BY


3-input NAND Gate Y pulls low if ALL inputs are 1 Y pulls high if ANY input is 0

A

B

Y

C


Example

Sketch a 3-input CMOS NOR gate


Complementary CMOS Complementary CMOS logic gates

– nMOS pull-down network– pMOS pull-up network– a.k.a. static CMOS

pMOSpull-upnetwork

outputinputs

nMOSpull-downnetwork

Pull-up OFF Pull-up ON

Pull-down OFF Z (float) 1

Pull-down ON 0 X (crowbar)


Series and Parallel nMOS: 1 = ON pMOS: 0 = ON Series: both must be ON Parallel: either can be ON

(a)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

OFF OFF OFF ON

(b)

a

b

a

b

g1

g2

0

0

a

b

0

1

a

b

1

0

a

b

1

1

ON OFF OFF OFF

(c)

a

b

a

b

g1 g2 0 0

OFF ON ON ON

(d) ON ON ON OFF

a

b

0

a

b

1

a

b

11 0 1

a

b

0 0

a

b

0

a

b

1

a

b

11 0 1

a

b

g1 g2


Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate

– Series nMOS: Y=0 when both inputs are 1– Thus Y=1 when either input is 0– Requires parallel pMOS

Rule of Conduction Complements– Pull-up network is complement of pull-down– Parallel -> series, series -> parallel

A

B

Y


Compound Gates Compound gates can do any inverting function Ex: (AND-AND-OR-INVERT, AOI22)Y A B C D

A

B

C

D

A

B

C

D

A B C DA B

C D

B

D

YA

CA

C

A

B

C

D

B

D

Y

(a)

(c)

(e)

(b)

(d)

(f)


Example: O3AI Y A B C D

A B

Y

C

D

DC

B

A


Example

Sketch a transistor-level schematic for a single-stage CMOS logic gate for each of the following functions:– (ABC+D)΄– ((AB+C)D)΄– (AB+(C(A+B)))΄


Signal Strength Strength of signal

– How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0

nMOS pass strong 0– But degraded or weak 1

pMOS pass strong 1– But degraded or weak 0

Thus nMOS are best for pull-down network


Pass Transistors Transistors can be used as switches

g = 0

s d

g = 1

s d

0 strong 0

Input Output

1 degraded 1

g = 0

s d

g = 1

s d

0 degraded 0

Input Output

strong 1

g = 1

g = 1

g = 0

g = 01

g

s d

g

s d


Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well

g = 0, gb = 1

a b

g = 1, gb = 0

a b

0 strong 0

Input Output

1 strong 1

g

gb

a b

a b

g

gb

a b

g

gb

a b

g

gb

g = 1, gb = 0

g = 1, gb = 0


Tristates Tristate buffer produces Z when not enabled

EN A Y

0 0 Z

0 1 Z

1 0 0

1 1 1

A Y

EN

A Y

EN

EN


Nonrestoring Tristate Transmission gate acts as tristate buffer

– Only two transistors– But nonrestoring

• Noise on A is passed on to Y

A Y

EN

EN


Tristate Inverter Tristate inverter produces restored output

– Violates conduction complement rule– Because we want a Z output

A

YEN

A

Y

EN = 0Y = 'Z'

Y

EN = 1Y = A

A

EN


Multiplexers 2:1 multiplexer chooses between two inputs

S D1 D0 Y

0 X 0 0

0 X 1 1

1 0 X 0

1 1 X 1

0

1

S

D0

D1Y


Gate-Level Mux Design How many transistors are needed? 20

1 0 (too many transistors)Y SD SD

44

D1

D0S Y

4

2

2

2 Y2

D1

D0S


Transmission Gate Mux Nonrestoring mux uses two transmission gates

– Only 4 transistorsS

S

D0

D1

YS


Inverting Mux Inverting multiplexer

– Use compound AOI22– Or pair of tristate inverters– Essentially the same thing

Noninverting multiplexer adds an inverter

S

D0 D1

Y

S

D0

D1Y

0

1S

Y

D0

D1

S

S

S

S

S

S


4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects

– Two levels of 2:1 muxes– Or four tristates

S0

D0

D1

0

1

0

1

0

1Y

S1

D2

D3

D0

D1

D2

D3

Y

S1S0 S1S0 S1S0 S1S0


D Latch When CLK = 1, latch is transparent

– D flows through to Q like a buffer When CLK = 0, the latch is opaque

– Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch

CLK

D Q

Latc

h D

CLK

Q


D Latch Design Multiplexer chooses D or old Q

1

0

D

CLK

QCLK

CLKCLK

CLK

DQ Q

Q


D Latch Operation

CLK = 1

D Q

Q

CLK = 0

D Q

Q

D

CLK

Q


D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave

flip-flop

Flo

p

CLK

D Q

D

CLK

Q


D Flip-flop Design Built from master and slave D latches

QM

CLK

CLKCLK

CLK

Q

CLK

CLK

CLK

CLK

D

Latc

h

Latc

h

D QQM

CLK

CLK


D Flip-flop Operation

CLK = 1

D

CLK = 0

Q

D

QM

QMQ

D

CLK

Q


Race Condition Back-to-back flops can malfunction from clock skew

– Second flip-flop fires late– Sees first flip-flop change and captures its result– Called hold-time failure or race condition

CLK1

D Q1

Flo

p

Flo

p

CLK2

Q2

CLK1

CLK2

Q1

Q2


Nonoverlapping Clocks Nonoverlapping clocks can prevent races

– As long as nonoverlap exceeds clock skew We will use them in this class for safe design

– Industry manages skew more carefully instead 1

11

1

2

22

2

2

1

QMQD


CMOS Fabrication CMOS transistors are fabricated on silicon wafer Lithography process similar to printing press On each step, different materials are deposited or

etched Easiest to understand by viewing both top and

cross-section of wafer in a simplified manufacturing process


Inverter Cross-section Typically use p-type substrate for nMOS transistors Requires n-well for body of pMOS transistors

n+

p substrate

p+

n well

A

YGND VDD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


Well and Substrate Taps Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor connection called Shottky Diode

Use heavily doped well and substrate contacts / taps

n+

p substrate

p+

n well

A

YGND VDD

n+p+

substrate tapwell tap

n+ p+


Inverter Mask Set Transistors and wires are defined by masks Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tapnMOS transistor pMOS transistor


Detailed Mask Views Six masks

– n-well– Polysilicon– n+ diffusion– p+ diffusion– Contact– Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well


Fabrication Chips are built in huge factories called fabs Contain clean rooms as large as football fields

Courtesy of InternationalBusiness Machines Corporation. Unauthorized use not permitted.


Fabrication Steps Start with blank wafer Build inverter from the bottom up First step will be to form the n-well

– Cover wafer with protective layer of SiO2 (oxide)

– Remove layer where n-well should be built– Implant or diffuse n dopants into exposed wafer

– Strip off SiO2

p substrate


Oxidation Grow SiO2 on top of Si wafer

– 900 – 1200 C with H2O or O2 in oxidation furnace

p substrate

SiO2


Photoresist Spin on photoresist

– Photoresist is a light-sensitive organic polymer– Softens where exposed to light

p substrate

SiO2

Photoresist


Lithography Expose photoresist through n-well mask Strip off exposed photoresist

p substrate

SiO2

Photoresist


Etch Etch oxide with hydrofluoric acid (HF)

– Seeps through skin and eats bone; nasty stuff!!! Only attacks oxide where resist has been exposed

p substrate

SiO2

Photoresist


Strip Photoresist Strip off remaining photoresist

– Use mixture of acids called piranah etch Necessary so resist doesn’t melt in next step

p substrate

SiO2


n-well n-well is formed with diffusion or ion implantation Diffusion

– Place wafer in furnace with arsenic gas– Heat until As atoms diffuse into exposed Si

Ion Implanatation– Blast wafer with beam of As ions

– Ions blocked by SiO2, only enter exposed Si

n well

SiO2


Strip Oxide Strip off the remaining oxide using HF Back to bare wafer with n-well Subsequent steps involve similar series of steps

p substraten well


Polysilicon Deposit very thin layer of gate oxide

– < 20 Å (6-7 atomic layers) Chemical Vapor Deposition (CVD) of silicon layer

– Place wafer in furnace with Silane gas (SiH4)

– Forms many small crystals called polysilicon– Heavily doped to be good conductor

Thin gate oxidePolysilicon

p substraten well


Polysilicon Patterning Use same lithography process to pattern polysilicon

Polysilicon

p substrate

Thin gate oxidePolysilicon

n well


Self-Aligned Process Use oxide and masking to expose where n+ dopants

should be diffused or implanted N-diffusion forms nMOS source, drain, and n-well

contact

p substraten well


N-diffusion Pattern oxide and form n+ regions Self-aligned process where gate blocks diffusion Polysilicon is better than metal for self-aligned gates

because it doesn’t melt during later processing

p substraten well

n+ Diffusion


N-diffusion cont. Historically dopants were diffused Usually ion implantation today But regions are still called diffusion

n wellp substrate

n+n+ n+


N-diffusion cont. Strip off oxide to complete patterning step

n wellp substrate

n+n+ n+


P-Diffusion Similar set of steps form p+ diffusion regions for

pMOS source and drain and substrate contact

p+ Diffusion

p substraten well

n+n+ n+p+p+p+


Contacts Now we need to wire together the devices Cover chip with thick field oxide Etch oxide where contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact


Metalization Sputter on aluminum over whole wafer Pattern to remove excess metal, leaving wires

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+

Metal


Layout Chips are specified with set of masks Minimum dimensions of masks determine transistor

size (and hence speed, cost, and power) Feature size f = distance between source and drain

– Set by minimum width of polysilicon Feature size improves 30% every 3 years or so Normalize for feature size when describing design

rules Express rules in terms of = f/2

– E.g. = 0.3 m in 0.6 m process


Simplified Design Rules Conservative rules to get you started


Inverter Layout Transistor dimensions specified as Width / Length

– Minimum size is 4 / 2sometimes called 1 unit– In f = 0.6 m process, this is 1.2 m wide, 0.6 m

long


Gate Layout Layout can be very time consuming

– Design gates to fit together nicely– Build a library of standard cells

Standard cell design methodology

– VDD and GND should abut (standard height)

– Adjacent gates should satisfy design rules– nMOS at bottom and pMOS at top– All gates include well and substrate contacts


Example: Inverter


Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top

Metal1 GND rail at bottom 32 by 40


Stick Diagrams Stick diagrams help plan layout quickly

– Need not be to scale– Draw with color pencils or dry-erase markers

c

AVDD

GND

Y

AVDD

GND

B C

Y

INV

metal1

poly

ndiff

pdiff

contact

NAND3


Wiring Tracks A wiring track is the space required for a wire

– 4 width, 4 spacing from neighbor = 8 pitch Transistors also consume one wiring track


Well spacing Wells must surround transistors by 6

– Implies 12 between opposite transistor flavors– Leaves room for one wire track


32

40

Area Estimation Estimate area by counting wiring tracks

– Multiply by 8 to express in


Example: O3AI Sketch a stick diagram for O3AI and estimate area

– Y A B C D

AVDD

GND

B C

Y

D

6 tracks = 48

5 tracks = 40


Example

Draw a stick diagram and estimate the area for a 4-input NOR gate


Example

For a compound gate implementing the boolean function F=((A+B)C)΄:– Sketch a transistor-level schematic – Sketch a stick diagram– Estimate the area from the stick diagram


Summary MOS transistors are stacks of gate, oxide, silicon Act as electrically controlled switches Build logic gates out of switches Draw masks to specify layout of transistors

Now you know everything necessary to start designing schematics and layout for a simple chip!


Spice netlist

vdd vdd gnd 5

Vin a gnd pwl 0ps 0 10ns 0 10.5ns 5 50ns 5 50.5ns 0

*** TOP LEVEL CELL: myinv2{lay}

Mnmos@0 y a gnd gnd N L=0.8U W=0.8U AS=3.54P AD=1.72P PS=8.15U PD=5.8U

Mpmos@0 vdd a y vdd P L=0.8U W=1.6U AS=5.2P AD=3.54P PS=9.7U PD=8.15U

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Lecture 1: Introduction Original Lecture notes © 2010 David Money Harris Modified by Konstantinos...

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