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Lecture 1: Introduction to Digital Logic Design
CSE 140: Components and Design Techniques for Digital Systems
Winter 2016
CK Cheng Dept. of Computer Science and Engineering
University of California, San Diego
Information about the Instructor • Instructor: CK Cheng • Education: Ph.D. in EECS UC Berkeley • Industrial Experiences: Engineer of AMD, Mentor
Graphics, Bellcore; Consultant for technology companies
• Email: [email protected] • Office: 2130 EBU3B • Office hours will be posted on the course website • Websites
– http://cseweb.ucsd.edu/~kuan – http://cseweb.ucsd.edu/classes/wi16/cse140-a
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Information about TAs TAs • Ardeshiricham, Armaiti, [email protected] • Hingolikar, Mrinmayee Pravin, [email protected] • Kang, Ilgweon, [email protected] • Maurya, Akanksha, [email protected] • Wang, Xinyuan, [email protected] Tutors • Fakhourian, Eric, [email protected] • Shih, Linda, [email protected] • Wang, Runping, [email protected] Office hours will be posted on the course website
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Logistics: Resources All information about the class is on the class website: http://cseweb.ucsd.edu/classes/wi16/cse140-a/index.html
• Approx. Syllabus • Detailed schedule • Readings • Assignments (Piazza) • Grading policy (Website) • Forum (Piazza) • Content/announcements and grades will be posted
through Piazza *make sure you have access
I will assume that you check these daily. Office hours and emails will be available on the course website
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Logistics: Textbooks Required text: • Online Textbook: Digital Design by F. Vahid
1. Sign up at zyBooks.com 2. Enter zyBook code UCSDCSE140Winter2016 3. Click Subscribe
Reference texts (recommended and reserved in library) • Digital Design, F. Vahid, 2010 (2nd Edition). • Digital Design and Computer Architecture, D.M. Harris
and S.L. Harris, Morgan Kaufmann, 2013 (2nd Edition). • Digital Systems and Hardware/Firmware Algorithms,
Milos D. Ercegovac and Tomas Lang
Lecture: Peer Instruction • I will pose questions. You will
– Solo vote: Think for yourself and select answer – Discuss: Analyze problem in teams of three
• Practice analyzing, talking about challenging concepts • Reach consensus
– Class wide discussion: • Led by YOU (students) – tell us what you talked about in
discussion that everyone should know.
• Many questions are open, i.e. no exact solutions. – Emphasis is on reasoning and team discussion – No solution will be posted
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Grade on style, completeness and correctness • zyBook exercises: 10% • iClicker: x=5% (by participation up to 20 classes) • Homework: 10-x% (grade based on a subset of problems. If
more than 70% of class fill out CAPE evaluations, the lowest homework score will be dropped)
• Midterm 1: 25% (M 1/25) • Midterm 2: 25% (W 2/17) • Final: 30% (3-5PM, M 3/14) • Grading: The best of the following
– The absolute: A- >90% ; B- >80% of total 100% score – The curve: (A+,A,A-) top 33+ε% of class; (B+,B,B-) second 33+ε% – The bottom: C- above 45% of absolute score.
Logistics: Grading
A word on the grading components • Exercises:
– Interactive learning experience • iClicker:
– Clarification of the concepts and team discussion • HWs:
– Practice for exams. Group discussion is encouraged – However, we are required to write them individually for best
results • Exams
– (Another) Indication of how well we have absorbed the material
– Solution and grading policy will be posted after exam. – Learn from mistakes and move on ….
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Course Problems…Cheating
• What is cheating? –Studying together in groups is encouraged –Turned-in work must be completely your own. –Copying someone else’s solution on a HW or exam is cheating –Both “giver” and “receiver” are equally culpable
• We have to address the issue once the cheating is reported by TAs or tutors.
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Motivation • Microelectronic technologies have revolutionized
our world: cell phones, internet, rapid advances in medicine, etc.
• The semiconductor industry has grown from $21 billion in 1985 to $315 billion in 2013.
The Digital Revolution
WWII
Integrated Circuit: Many digital operations on the same material
ENIAC Moore’s Law
1965 1949
Integrated Circuit
Exponential Growth of Computation
Vacuum tubes
(1.6 x 11.1 mm)
Stored Program Model 11
Building complex circuits
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Transistor
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Robert Noyce, 1927 - 1990 • Nicknamed “Mayor of Silicon
Valley” • Cofounded Fairchild
Semiconductor in 1957 • Cofounded Intel in 1968 • Co-invented the integrated
circuit
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Gordon Moore
• Cofounded Intel in 1968 with Robert Noyce.
• Moore’s Law: the number of transistors on a computer chip doubles every 1.5 years (observed in 1965)
Technology Trends: Moore’s Law
• Since 1975, transistor counts have doubled every two years. 15
How do we handle complexity?
• Big idea: Coordination of many levels of abstraction
CSE 140
I/O system Processor
Compiler Operating System (Mac OSX)
Application (ex: browser)
Digital Design Circuit Design
Instruction Set Architecture
Datapath & Control
Transistors
Memory Hardware
Software Assembler
Dan Garcia
CSE 120
CSE 140,141
CSE 131
Algos: CSE 100, 101
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Principle of Abstraction
Abstraction: Hiding details when they are not important
Physics
Devices
AnalogCircuits
DigitalCircuits
Logic
Micro-architecture
Architecture
OperatingSystems
ApplicationSoftware
electrons
transistorsdiodes
amplifiersfilters
AND gatesNOT gates
addersmemories
datapathscontrollers
instructionsregisters
device drivers
programs
focu
s of t
his co
urse
CSE 30
CSE 141
CSE 140
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Scope
• The purpose of this course is that we: – Learn the principles of digital design – Learn to systematically debug increasingly
complex designs – Design and build digital systems – Learn what’s under the hood of an electronic
component
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Scope: Overall Picture of CS140
Sequential machine
Conditions
Control
Mux
Memory File
ALU
Memory Register
Conditions
Input
Pointer
CLK: Synchronizing Clock
Data Path Subsystem
Select
Control Subsystem
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fi(x,s)
x1 . . . xn
Combinational Logic vs Sequential Network
Combinational logic: yi = fi(x1,..,xn)
CLK Sequential Networks 1. Memory 2. Time Steps (Clock) yi
t = fi (x1t,…,xn
t, s1t, …,sm
t)
sit+1 = gi(x1
t,…,xnt, s1
t,…,smt)
fi(x)
x1 . . . xn
fi(x) fi(x)
x1 . . . xn
fi(x) si
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Scope
Subjects Building Blocks Theory
Combinational Logic
AND, OR, NOT, XOR
Boolean Algebra
Sequential Network
AND, OR, NOT, FF
Finite State Machine
Standard Modules
Operators, Interconnects, Memory
Arithmetics, Universal Logic
System Design Data Paths, Control Paths
Methodologies
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Combinational Logic
Basics
What is a combinational circuit?
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• No memory • Realizes one or more functions • Inputs and outputs can only have two discrete values
• Physical domain (usually, voltages) (0V, 5V) • Mathematical domain : Boolean variables ( true or false)
Differentiate between different representations: • physical circuit • schematic diagram • mathematical expressions
Representations of combinational circuits: The Schematic
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A
B
Y
• What is the simplest combinational circuit that you
know?
Representations of combinational circuits:
Truth Table
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A
B
Y
A B Y 0 0 0 0 1 0 1 0 0 1 1 1
AND
Representations of combinational circuits:
Boolean Expression/Equation
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A
B
Y A B Y 0 0 0 0 1 0 1 0 0 1 1 1
AND
Y= AB
All three forms are equivalent!
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Boolean Algebra Similar to regular algebra but defined on sets with only three basic ‘logic’ operations: 1. Intersection: AND (2-input); Operator: . 2. Union: OR (2-input); Operator: + 3. Complement: NOT ( 1-input); Operator: ‘
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Two-input AND ( ∙ )
A B Y 0 0 0 0 1 0 1 0 0 1 1 1
AND A B Y 0 0 0 0 1 1 1 0 1 1 1 1
OR A Y 0 1 1 0
NOT
Boolean algebra and switching functions
For an AND gate, 0 at input blocks the other inputs and dominates the output 1 at input passes signal A
For an OR gate, 1 at input blocks the other inputs and dominates the output 0 at input passes signal A
A 1 1
A 0 A
A 1 A
A 0 0
Two-input OR (+ ) One-input NOT (Complement, ’ )
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Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+Y? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2
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Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+X+Y? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2
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Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=X+XY? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2
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Boolean Algebra iClicker Q: For two Boolean variables X and Y with X=1, Y=0, what is function F(X,Y)=(X+Y)Y? A.F(X,Y)=0 B.F(X,Y)=1 C.F(X,Y)=2
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Boolean Algebra Boolean operations satisfy the following laws: •Commutative laws: a+b=b+a, a·b=b·a •Distributive laws: a+(b·c)=(a+b)·(a+c), a·(b+c)=a·b+a·c •Identity laws: a+0=a, a·1=a •Complement laws: a+a’=1, a·a’=0
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So, what is the point of representing gates as symbols and Boolean expressions?
ab + cd a b
c d e
cd
ab
y=e (ab+cd)
Logic circuit vs. Boolean Algebra Expression
• Given the Boolean expression, we can draw the circuit it represents by cascading gates (and vice versa)
Next class
• Designing Combinational circuits
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