Lecture 10: Sequential Networks: Timing and

Retiming

CSE 140: Components and Design Techniques for Digital Systems

Fall 2014

CK Cheng

Dept. of Computer Science and Engineering University of California, San Diego

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Timing

• Two timing constraints: Shortest and longest timing paths

• Flip-Flop timing window • Combinational timing

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Timing • Clock specifies a precise time for the next state

– In general, we allocate one clock period for signal propagation between registers.

• Too late: Fail to reach for the setup of the next state.

• Too early: Race to disturb the holding of the next state.

• Analysis: Verify the timing of the system. • Goal: A robust design.

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So far ….

Combinational

CLK

Logic-level analysis

This lecture …

• When does our (seemingly logically correct) design go wrong? • How can we design a circuit that works under real constraints?

Combinational

CLK

A typical sequential network has combinational circuit between registers (R1 to R2). The registers are synchronized by clocks (CLK1 to CLK2). Timing is set between clocks (CLK1 and CLK2). The beauty of the synchronized design is that we need only to take care of the timing of the regions separated by the registers.

Sequential Networks

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Combinational

CLK1 CLK2

A B C D

R1 R2

iClicker

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For a synchronized digital Moore machine, we need to take care of the timing of the following region(s). A. Between every pair of registers. B. Between i. input and register, and ii. register and output. C. Both A and B. D. Whole system from input to output including registers.

C1 C2

CLK

x(t) y(t)

S(t)

Combinational

CLK1 CLK2

A B C

tcq + tcomb + tsetup ≤ T thold < tcq + tcomb

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Combinational

CLK1 CLK2

A B C

Hold time constraint thold < tcq + tcomb

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Setup time constraint tcq + tcomb + tsetup ≤ T max(tcq + tcomb + tsetup )≤ T

thold < min(tcq + tcomb)

Longest delay from CLK1 to CLK2

Shortest delay from CLK1 to CLK2

Sequential Networks Timing: Setup Time and Hold Time Constraints

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CLK

D Q

Q

CLK

D Q

Q

Q

Q

D N1

CLK

L1 L2

D Q Q’

Timing Constraints of flip flops

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t1 time

What if the input transition happens late, close to the rising edge? A.Output will still be one at t1 B.Output will be zero at t1 C.Can’t say for sure

D D

Q Q’

Input Constraints: Set up and hold time

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CLK

tsetup

D

thold

taI. Setup time: tsetup Time before the clock edge that data must be stable (i.e. not change)

II. Hold time: thold Time after the clock edge that data must be stable

Aperture time: ta Time around clock edge that data must be stable (ta = tsetup + thold)

D Q Q’

Set up and hold time violations

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CLK

tsetup

D

thold

taI. Setup time violation This occurs if the input data signal does not remain unchanged for at least tsetup before the clock edge.

II. Hold time violation This occurs if the input data signal does not remain unchanged for at least tsetup before the clock edge

D Q Q’

Output Timing Constraints • Propagation delay: tpcq = time after clock edge that

the output Q is guaranteed to be stable (i.e., to stop changing)

• Contamination delay: tccq = time after clock edge that Q might be unstable (i.e., start changing)

CLK

tccqtpcq

Q

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D Q Q’

Output Timing Constraints

I. Contamination delay: tccq Time after clock edge that Q might be unstable (i.e., start changing)

II. Propagation delay: tpcq Time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing)

CLK

tccqtpcq

Q

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D Q Q’

PIQ: A hold time violation is likely to occur when

A. The input signal (into the flip flop) fails to change to a desired value fast enough

B. The output signal (out of the flip flop) takes too long to stabilize

C. The input signal (into the flip flop) does not remain stable long enough after the clock edge

D. The output signal (out of the flip flop) changes too quickly

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PIQ: The timing of which of the following signals can cause a setup-time violation?

A. The input signal T(t) B. The output signal Q(t) C. The clock signal, CLK D. Some of the above E. None of the above

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T Q Q’

T(t)

CLK

Q(t)

PIQ: For a given flip-flop implementation which of its timing parameters can we modify when designing a sequential network (depicted below)

A. Set up and hold time B. Propagation and

Contamination delays C. All of the above D. None of the above

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Combinational

CLK

Fact 1: Once a flip flop has been ‘built’ we are stuck with its timing characteristics: tsetup , thold, tccq, tpcq

Now let’s look at the timing characteristics of the combinational part

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Combinational

CLK

Combinational Logic: Output timing constraints

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X1

X2

X4

I. Why don’t we have input constraints?

Combinational circuit X3

Y1

Y2

Y4

Y3

Combinational Logic: Output timing constraints

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X1

X2

X4

Combinational circuit X3

Y1

Y2

Y4

Y3

I. Contamination delay: tcd Minimum time from when an input changes until any output starts to change

Combinational Logic: Output timing constraints

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X1

X2

X4

I. Contamination delay: tcd Minimum time from when an input changes until any output starts to change

II. Propagation delay: tpd Maximum time from when an input changes until the output or outputs of a combinational circuit are guaranteed to reach their final value (i.e., stop changing)

Combinational circuit X3

Y1

Y2

Y4

Y3

Combinational Logic: Output timing constraints

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A

B

C D

Y

PI Q: Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? A.AND- OR – NOR B.AND-OR C.NOR D.OR-NOR

Combinational Logic: Output timing constraints

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A

B

C D

Y

PI Q: Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? A.AND- OR – NOR B.AND-OR C.NOR D.OR-NOR

R1 Combinational

CLK

R2

CLK

D1 Q1 D2

An alternate view of the sequential circuit

Combinational

CLK

What should happen within a clock cycle for correct functionality?

R1 Combinational

CLK

R2

CLK

D1 Q1 D2

The delay between registers has a minimum and maximum delay, dependent on the delays of the circuit elements (Dynamic Discipline)

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

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CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

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PI Q: Suppose input to R1 changed before t1, what is the maximum delay (from t1) after which D2 reaches a stable value?

A. Setup time of R1+ Propagation delay of CL + Propagation delay of R2

B. Hold time of R1+ Propagation delay of CL + setup time of R1

C. Propagation delay of R1+ Propagation delay of CL + Propagation delay of R2

D. Propagation delay of R1+ Propagation delay of CL

E. Propagation delay of CL + Propagation delay of R2

Setup Time Constraint • The setup time constraint depends on the maximum delay from register R1

through the combinational logic. • The input to register R2 must be stable at least tsetup before the clock edge.

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2

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Maximum delay, tmax =

Setup Time Constraint:

Setup Time Constraint

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2

Tc ≥ tpcq + tpd + tsetup

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PI Q: As a designer, which of the following parameters would you modify to meet the set up time constraint? A. The clock period, Tc B. The prop. delay of R1, tpcq C. The prop. delay of CL, tpd D. The setup time of R2, tsetup E. All of the above

Setup Time Constraint

CLK

Q1

D2

Tc

tpcq tpd tsetup

CL

CLKCLK

Q1 D2

R1 R2

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PI Q: As a designer, which of the following parameters would you modify to meet the set up time constraint? A. The clock period, Tc B. The prop. delay of R1, tpcq C. The prop. delay of CL, tpd D. The setup time of R2, tsetup E. All of the above

Tc ≥ tpcq + tpd + tsetup

tpd ≤ Tc – (tpcq + tsetup)

CL

CLKCLK

R1 R2

Q1 D2

(a)

CLK

Q1

D2(b)

Tc

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PI Q: Suppose input to R1 changed before t1, what is the minimum delay (from t1) after which D2 starts to change?

A. Setup time of R1+ propagation delay of CL + propagation of R2

B. Hold time of R1+ propagation time of CL +setup time of R1

C. Hold time of R1+ Contamination delay of CL + Propagation time of R2

D. Contamination delay of R1+ Contamination delay of CL

E. Contamination delay of CL + Contamination delay of R2

Hold Time Constraint • The hold time constraint depends on the minimum delay from register R1

through the combinational logic. • The input to register R2 must be stable for at least thold after the clock edge.

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Minimum delay, tmin =

Hold Time Constraint:

CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2

Hold Time Constraint

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CLK

Q1

D2

tccq tcd

thold

CL

CLKCLK

Q1 D2

R1 R2

thold < tccq + tcd

tcd > thold - tccq

Timing Analysis CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps tpd =

tcd =

Setup time constraint:

Tc ≥

fc = 1/Tc =

Hold time constraint:

tccq + tpd > thold ?

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Timing Analysis CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

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tpd = 3 x 35 ps = 105 ps

tcd = 25 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tcd > thold ?

(30 + 25) ps > 70 ps ? No!

Fixing Hold Time Violation Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps tpd =

tcd =

Setup time constraint:

Tc ≥

fc =

Hold time constraint:

tccq + tpd > thold ?

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

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Fixing Hold Time Violation Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps tpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps

Setup time constraint:

Tc ≥ (50 + 105 + 60) ps = 215 ps

fc = 1/Tc = 4.65 GHz

Hold time constraint:

tccq + tcd > thold ?

(30 + 50) ps > 70 ps ? Yes!

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

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Clock Skew

• The clock doesn’t arrive at all registers at the same time • Skew is the difference between two clock edges • Examine the worst case to guarantee that the dynamic discipline is not

violated for any register – many registers in a system!

tskew

CLK1

CLK2

CL

CLK2

CLK1

R1 R2

Q1 D2

CLK

delay

CLK

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Setup Time Constraint with Clock Skew • In the worst case, the CLK2 is earlier than CLK1

Tc ≥ tpcq + tpd + tsetup + tskew

tpd ≤ Tc – (tpcq + tsetup + tskew)

CLK1

Q1

D2

Tc

tpcq tpd tsetuptskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

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Timing Analysis with clock skew CLK CLK

A

B

C

D

X'

Y'

X

Y

Timing Characteristics tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

tskew = 50 ps

tpd = 3 x 35 ps = 105 ps

tcd = 25 ps

Setup time constraint:

Tc ≥ 265 ps

fc = 1/Tc =3.77 GHz

Without skew we got fc =4.65 GHz

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Hold Time Constraint with Clock Skew

• In the worst case, CLK2 is later than CLK1

tccq + tcd > thold + tskew

tcd > thold + tskew – tccq

tccq tcd

thold

Q1

D2

tskew

CL

CLK2CLK1

R1 R2

Q1 D2

CLK2

CLK1

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Hold Time Violation Timing Characteristics

tccq = 30 ps

tpcq = 50 ps

tsetup = 60 ps

thold = 70 ps

tpd = 35 ps

tcd = 25 ps

tskew = 50 ps

tpd = 3 x 35 ps = 105 ps

tcd = 2 x 25 ps = 50 ps

Hold time constraint:

tccq + tcd > thold + tskew?

(30 + 50) ps > (70 ps +50) ps ?

CLK CLK

A

B

C

D

X'

Y'

X

Y

Add buffers to the short paths:

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Timing and Retiming

• Retiming: Adjust the clock skew so that the clock period can be reduced.

• Add a few more examples on timing and retiming.

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Conclusion

• Clock to Clock: Range of shortest and longest paths

• Design revision and retiming to adjust the constraints

• Research: Variation aware designs

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