1CSE370, Lecture 11

Lecture 11

Logistics HW4 due on Wednesday

Last lecture PLDs

ROMs Multilevel logic

Today Timing diagrams Hazards

2CSE370, Lecture 11

The “WHY” slide Timing diagram

Real gates have real delays and it is good to learn how to plot the information with respect to time.

Hazards Different delays can cause some output to get

glitches. If these glitches are used in the next level of calculation, it could cause miscalculation. It is good to know when that happens and how to fix it.

3CSE370, Lecture 11

Timing diagram (aka waveforms)

Shows time-response of circuits

Can use as sideways truth table

Example: F = A +BC

000 001 010 011 100 101 110 111

4CSE370, Lecture 11

FA B C D

time

Timing diagrams

Real gates have real delays

Example: A' • A = 0 Delays cause transient F=1

width of 3 gate delays

5CSE370, Lecture 11

Example: F=A+BC in 2-level logic

minimized product-of-sums

F1

F2

F3

B

C

A

F4

canonical product-of-sums

minimized sum-of-products

canonical sum-of-products

6CSE370, Lecture 11

Timing diagram for F = A + BC

Time waveforms for F1 – F4 are identical Except for timing hazards (glitches)

7CSE370, Lecture 11

Hazards/glitches

Hazards/glitches: Undesired output switching Occurs when different pathways have different delays Wastes power (wire switching consumes power) Causes circuit noise Dangerous if logic makes a decision while output is

unstable

Solutions Design hazard-free circuits

Difficult when logic is multilevel Wait until signals are stable

8CSE370, Lecture 11

10 0

1 10 0

1 10 0

01 1

Types of hazards

Static 1-hazard Output should stay logic 1 Gate delays cause brief glitch to

logic 0

Static 0-hazard Output should stay logic 0 Gate delays cause brief glitch to

logic 1

Dynamic hazards Output should toggle cleanly Gate delays cause multiple

transitions

9CSE370, Lecture 11

Static hazards

Often occurs when a literal and its complement momentarily assume the same value Through different paths with different delays Causes an (ideally) static output to glitch

F

A

B

S

S'

F

static-0 hazard

AS

B

S'

A multiplexer

10CSE370, Lecture 11

Timing diagram for F = A + BC

Time waveforms for F1 – F4 are identical Except for timing hazards (glitches)

11CSE370, Lecture 11

Example: F=A+BC in 2-level logic

minimized product-of-sums

F1

F2

F3

B

C

A

F4

canonical product-of-sums

minimized sum-of-products

canonical sum-of-products

0

0

0

1

12CSE370, Lecture 11

Timing diagram for F = A + BC

Time waveforms for F1 – F4 are identical Except for timing hazards (glitches)

13CSE370, Lecture 11

01

10

Example: F=A+BC in 2-level logic

minimized product-of-sums

F1

F2

F3

B

C

A

F4

canonical product-of-sums

minimized sum-of-products

canonical sum-of-products10

14CSE370, Lecture 11

Dynamic hazards

Often occurs when a literal assumes multiple values Through different paths with different delays Causes an output to toggle multiple times

B2

A

C

B1

F

Dynamic hazard

B3

A

C

B

F

1

2

3

Dynamic hazards

15CSE370, Lecture 11

Eliminating static hazards (only in 2 level logic)

Key idea: Glitches happen when a changing input spans separate K-map encirclements Example: 1101 to 0101 change can cause a static-1

glitch

AC'

A'D

F

0 0 1 1

1 1 1 1

1 1 0 0

0 0 0 0

ABCD

B

D

00 01 11 10

00

01

11

10C

A

F = AC' + A'D

1101

0101

0111

1

0

1

0

0

0

0

1

1

16CSE370, Lecture 11

Eliminating static hazards (con’t)

Solution: Add redundant K-map encirclements Ensure that all single-bit changes are covered by

same block First eliminate static-1 hazards: Use SOP form

If need to eliminate static-0 hazards, use POS form

AC'

A'D

F

0 0 1 1

1 1 1 1

1 1 0 0

0 0 0 0

ABCD

B

D

00 01 11 10

00

01

11

10C

A

C'D

F = AC' + A'D + C'D

17CSE370, Lecture 11

Summary of hazards

We can eliminate static hazards in 2-level logic For single-bit changes Eliminating static hazards also eliminates dynamic

hazards

Hazards are a difficult problem Multiple-bit changes in 2-level logic are hard Static hazards in multilevel logic are harder Dynamic hazards in multilevel logic are harder yet

CAD tools and simulation/testing are indispensable