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Schedule3/10
Monday Latches (1) 5.1-5.3
3/12
Wednesday Flip-flops 5.4
3/13
Thursday Flip-flops, D-latch
3/17
Monday Spring break
3/19
Wednesday Spring break
3/20
Thursday Spring break
3/24
Monday Analysis of clocked sequential circuit (1) 5.5
3/26
Wednesday Analysis of clocked sequential circuit (2) 5.5
3/27
Thursday Clocked sequential circuit
Please bring a functional random number generator to class on Thursday(3/13).
Outline
• A brief overview of sequential circuits• Memory elements– NAND based SR latch– NAND based D latch
• Verilog Modeling
Block Diagram of Sequential Circuit
New output is dependent on the inputs and the preceding states of the circuit stored in the memory.
Characteristic: the output node is intentionally connected back to inputs of combinational circuits.
Sequential Circuits
• Two types of sequential circuits– Synchronous: circuits whose behavior
can be defined from its signals at discrete instants of time. Clocks are to achieve synchronization.
– Asynchronous circuits depend on input signals and the order in which the inputs change. (No clock pulses are used!)
Block Diagram of Sequential Circuit
Sychronous circuits:Used clocked flip-flops
Asychronous circuits:Use unclocked flip-flops or time delay elements
Revise
Applications of Asynchronous Circuits
• Asynchronous circuits are important where the digital system must respond quickly without having to wait for a clock pulse
• Useful in small independent circuits that require only a few components—where it may not be practical to go to the expense of providing a circuit for generating clock pulses!
Latches
• Latches are level sensitive.• Latches propagate values from input
to output continuously.• Inputs– Active low inputs are enabled by 0s.– Active high inputs are enabled by 1s.
S=0 and R=0
0
0
1
1
S=0 and R=0:
The outputs are not complementary. This is not a state we want to be in.
Observations
0
1
0
1
S=0 and R=1:
1
0
1
0
S=1 and R=0:
Use active low inputs (i.e. logic “0”) to produce changesat the outputs.
SR Latch with NAND Gates
1. Both inputs of the latch remain at 1 unless the state has to be changed.2. When both S and R are equal to 1, the latch can be in either the set or the reset, depending on which input was most recently a 1.
R must go back to 1 (the hold mode)in order to avoid S=R=0.Q and Q’ do not change states when Rgoes back to 1.
S must go back to 1 (the hold mode) in order to avoid S=R=0.Q and Q’ do not change states when Sgoes back to 1.
SR latch with Control Line (En=1)
1. En=1, Q and Q’ will be affected by S and R.2. We now have active-high enabled circuit!
1
S’
R’
D Latch (En=1)
1
D’
D
Q follows D as long as En is asserted (En=1).Data is temporary stored when En is disabled.
Continuous Statement
The updating of a continuous statement is triggered wheneverthere is a change on the right hand side of the equation.
The assign keyword is used is used.
Procedural Statements
• Procedural statements are executed when the condition is met.– Usually the condition is implemented with initial and always statements.
– There are two types of procedural statements: blocking and non-blocking statements.
– The left-hand side of the procedural statements must be the reg data type.
Blocking versus Nonblocking Statements
• There are two kinds of procedural assignments:– Blocking statements
• Use (=) as the assignment operator• Blocking statements are executed sequentially in the
order they are listed.• Used to model behavior that are level sensitive (i.e.
in combinational logic)
– Nonblocking statements• Use (<=) as the assignment operator• Non-blocking statements are executed concurrently.• Used to model synchronous/concurrent behavior.
Non-blocking Statements
• B<=A• C<=B+1– The value of A is kept in one storage location – The value of B+1 is stored in another storage
location– After all the expressions in the block are
evaluated and stored, the assignment to the targets on the left-hand side is made.
– C will contain the original value of B, plus 1. This is the value of B before A is written into B.