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Lecture 12 SRAM

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    Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.11

    EE4800 CMOS Digital IC Design & Analysis

    Lect!e 12 S"AM

    Z#$ Feng

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    Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.22

    Outline

    Me%$!y A!!ays S"AM A!c#itect!e

    SRAM Cell

    Decoders

    Column Circuitry

    Multiple Ports

    Se!ial Access Me%$!ies

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    Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.

    Memory Arrays

    Random Access Memory Serial Access Memory Content Addressable Memory

    (CAM)

    Read/Write Memory

    (RAM)(Volatile)

    Read Only Memory

    (ROM)(Nonolatile)

    Static RAM

    (SRAM)

    Dynamic RAM

    (DRAM)

    S!i"t Re#isters $ueues

    %irst &n

    %irst Out

    (%&%O)

    'ast &n

    %irst Out

    ('&%O)

    Serial &n

    Parallel Out

    (S&PO)

    Parallel &n

    Serial Out

    (P&SO)

    Mas ROM Pro#rammable

    ROM

    (PROM)

    rasable

    Pro#rammable

    ROM

    (PROM)

    lectrically

    rasable

    Pro#rammable

    ROM

    (PROM)

    %las! ROM

    Memory Arrays

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    Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.44

    Array Architecture 2nwords$' 2%bitseac#

    I' n (( %) '$l* +y 2,int$ 'e-e! rows$' %$!e columns

    $$* !egla!ity / easy t$ *esign

    e!y #ig# *ensity i' g$$* cells a!e se*

    r

    o*decoder

    column

    decoder

    n

    n+

    ,mbits

    column

    circuitry

    bitline conditionin#

    memory cells-

    ,n+ro*s .

    ,mcolumns

    bitlines

    *ordlines

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    Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.

    12T SRAM Cell

    asic +il*ing +l$c,3 S"AM Cell 0olds one bit o" in"ormation1 lie a latc!

    Must be read and *ritten

    12t!ansist$! 512T6 S"AM cell 2se a simple latc! connected to bitline

    34 . 56 unit cell

    bit

    *rite

    *rite7b

    read

    read7b

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    Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.77

    6T SRAM Cell

    Cell sie acc$nts '$! %$st $' a!!ay sie Reduce cell si8e at e.pense o" comple.ity

    7T S"AM Cell 2sed in most commercial c!ips

    Data stored in cross+coupled inerters

    "ea*3 Prec!ar#e bit1 bit7b

    Raise *ordline

    9!ite3

    Drie data onto bit1 bit7b Raise *ordline

    bit bit7b

    *ord

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    SRAM Read ;!ec#a!ge +$t# +itlines #ig#

    T#en t!n $n -$!*line One $' t#e t-$ +itlines -ill +e 0) A?+ > 1 bit disc!ar#es1 bit7b stays !i#!

    9ut A bumps up sli#!tly Read stability

    A must not "lip

    bit bit7b

    N:

    N,P:

    A

    P,

    N;

    N3

    A7b

    *ord

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    8/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.88

    SRAM Read ;!ec#a!ge +$t# +itlines #ig#

    T#en t!n $n -$!*line One $' t#e t-$ +itlines -ill +e 0) A?+ > 1 bit disc!ar#es1 bit7b stays !i#!

    9ut A bumps up sli#!tly

    Read stability

    A must not "lip

    bit bit7b

    N:

    N,P:

    A

    P,

    N;

    N3

    A7b

    *ord

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    SRAM Write D!ie $ne +itline #ig#) t#e $t#e! l$-

    T#en t!n $n -$!*line

    itlines $e! 0) A?+ > 1) +it > 1) +it?+ > 0 %orce A7b lo*1 t!en A rises !i#!

    Writability Must oerpo*er "eedbac inerter

    time (ps)

    *ord

    A

    A7b

    bit7b

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    10/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.1010

    SRAM Write D!ie $ne +itline #ig#) t#e $t#e! l$-

    T#en t!n $n -$!*line

    itlines $e! 0) A?+ > 1) +it > 1) +it?+ > 0 %orce A7b lo*1 t!en A rises !i#!

    Writability Must oerpo*er "eedbac inerter

    time (ps)

    *ord

    A

    A7b

    bit7b

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    11/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.1111

    SRAM Sizing Big# +itlines %st n$t $e!

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    12/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.1212

    SRAM Column Eam!le

    ,

    More

    Cells

    SRAM Cell

    *ord7>:

    bit7:"

    bit7b7:"

    data7s:

    *rite7>:

    9itline Conditionin#

    Read Write

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    13/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.11

    SRAM "ayout

    Cell sie is c!itical3 27 = 4 5een s%alle! in in*st!y6

    Tile cells s#a!ing DD) D) +itline c$ntacts

    VDD

    ?ND ?ND9&@ 9&@79

    WORD

    Cell boundary

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    Thin Cell In nan$%ete! CMOS

    Aoid bends in polysilicon and di""usion Orient all transistors in one direction

    Lithographically friendly$! thin celllay$t =est#is

    Also reduces len#t! and capacitance o" bitlines

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    15/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.11

    Commercial SRAMs Fie gene!ati$ns $' Intel S"AM cell

    %ic!$g!a

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    16/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.1717

    #ecoders n32n*ec$*e! c$nsists $' 2nnin

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    17/37Z. Feng MTU EE4800 CMOS Digital IC Design &Z. Feng MTU EE4800 CMOS Digital IC Design &12.12.1:1:

    #ecoder "ayout

    Dec$*e!s %st +e

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    "arge #ecoders F$! n ( 4) AD gates +ec$%e sl$-

    9rea lar#e #ates into multiple smaller #ates

    *ord


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