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1 Introduction to CMOS VLSI Design Lecture 13: SRAM David Harris Harvey Mudd College Spring 2004
1
Introduction toCMOS VLSI
Design
Lecture 13: SRAM
David Harris
Harvey Mudd CollegeSpring 2004
2
13: SRAM Slide 2CMOS VLSI Design
OutlineMemory ArraysSRAM Architecture– SRAM Cell– Decoders– Column Circuitry– Multiple Ports
Serial Access Memories
3
13: SRAM Slide 3CMOS VLSI Design
Memory ArraysMemory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory(CAM)
Read/Write Memory(RAM)
(Volatile)
Read Only Memory(ROM)
(Nonvolatile)
Static RAM(SRAM)
Dynamic RAM(DRAM)
Shift Registers Queues
First InFirst Out(FIFO)
Last InFirst Out(LIFO)
Serial InParallel Out
(SIPO)
Parallel InSerial Out
(PISO)
Mask ROM ProgrammableROM
(PROM)
ErasableProgrammable
ROM(EPROM)
ElectricallyErasable
ProgrammableROM
(EEPROM)
Flash ROM
4
13: SRAM Slide 4CMOS VLSI Design
Array Architecture2n words of 2m bits eachIf n >> m, fold by 2k into fewer rows of more columns
Good regularity – easy to designVery high density if good cells are used
row decoder
columndecoder
n
n-kk
2m bits
columncircuitry
bitline conditioning
memory cells:2n-k rows x2m+k columns
bitlines
wordlines
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13: SRAM Slide 5CMOS VLSI Design
12T SRAM CellBasic building block: SRAM Cell– Holds one bit of information, like a latch– Must be read and written
12-transistor (12T) SRAM cell– Use a simple latch connected to bitline– 46 x 75 λ unit cell
bit
write
write_b
read
read_b
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13: SRAM Slide 6CMOS VLSI Design
6T SRAM CellCell size accounts for most of array size– Reduce cell size at expense of complexity
6T SRAM Cell– Used in most commercial chips– Data stored in cross-coupled inverters
Read:– Precharge bit, bit_b– Raise wordline
Write:– Drive data onto bit, bit_b– Raise wordline
bit bit_b
word
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13: SRAM Slide 7CMOS VLSI Design
SRAM ReadPrecharge both bitlines highThen turn on wordlineOne of the two bitlines will be pulled down by the cellEx: A = 0, A_b = 1– bit discharges, bit_b stays high– But A bumps up slightly
Read stability– A must not flip
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600time (ps)
word bit
A
A_b bit_b
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13: SRAM Slide 8CMOS VLSI Design
SRAM ReadPrecharge both bitlines highThen turn on wordlineOne of the two bitlines will be pulled down by the cellEx: A = 0, A_b = 1– bit discharges, bit_b stays high– But A bumps up slightly
Read stability– A must not flip– N1 >> N2
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600time (ps)
word bit
A
A_b bit_b
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13: SRAM Slide 9CMOS VLSI Design
SRAM WriteDrive one bitline high, the other lowThen turn on wordlineBitlines overpower cell with new valueEx: A = 0, A_b = 1, bit = 1, bit_b = 0– Force A_b low, then A rises high
Writability– Must overpower feedback inverter
time (ps)
word
A
A_b
bit_b
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600 700
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
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13: SRAM Slide 10CMOS VLSI Design
SRAM WriteDrive one bitline high, the other lowThen turn on wordlineBitlines overpower cell with new valueEx: A = 0, A_b = 1, bit = 1, bit_b = 0– Force A_b low, then A rises high
Writability– Must overpower feedback inverter– N2 >> P1
time (ps)
word
A
A_b
bit_b
0.0
0.5
1.0
1.5
0 100 200 300 400 500 600 700
bit bit_b
N1
N2P1
A
P2
N3
N4
A_b
word
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13: SRAM Slide 11CMOS VLSI Design
SRAM SizingHigh bitlines must not overpower inverters during readsBut low bitlines must write new value into cell
bit bit_b
med
A
weak
strong
med
A_b
word
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13: SRAM Slide 12CMOS VLSI Design
SRAM Column ExampleRead Write
H H
SRAM Cell
word_q1
bit_v1f
bit_b_v1f
out_v1rout_b_v1r
φ1
φ2
word_q1
bit_v1f
out_v1r
φ2
MoreCells
Bitline Conditioning
φ2
MoreCells
SRAM Cell
word_q1
bit_v1f
bit_b_v1f
data_s1
write_q1
Bitline Conditioning
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13: SRAM Slide 13CMOS VLSI Design
SRAM LayoutCell size is critical: 26 x 45 λ (even smaller in industry)Tile cells sharing VDD, GND, bitline contacts
VDD
GND GNDBIT BIT_B
WORD
Cell boundary
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13: SRAM Slide 14CMOS VLSI Design
Decodersn:2n decoder consists of 2n n-input AND gates– One needed for each row of memory– Build AND from NAND or NOR gates
Static CMOS Pseudo-nMOS
word0
word1
word2
word3
A0A1
A1word
A0 1 1
1/2
2
4
8
16word
A0
A1
11
11
4
8word0
word1
word2
word3
A0A1
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13: SRAM Slide 15CMOS VLSI Design
Decoder LayoutDecoders must be pitch-matched to SRAM cell– Requires very skinny gates
GND
VDD
word
buffer inverterNAND gate
A0A0A1A2A3 A2A3 A1
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13: SRAM Slide 16CMOS VLSI Design
Large DecodersFor n > 4, NAND gates become slow– Break large gates into multiple smaller gates
word0
word1
word2
word3
word15
A0A1A2A3
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13: SRAM Slide 17CMOS VLSI Design
PredecodingMany of these gates are redundant– Factor out common
gates into predecoder– Saves area– Same path effort
A0
A1
A2
A3
word1
word2
word3
word15
word0
1 of 4 hotpredecoded lines
predecoders
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13: SRAM Slide 18CMOS VLSI Design
Column CircuitrySome circuitry is required for each column– Bitline conditioning– Sense amplifiers– Column multiplexing
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13: SRAM Slide 19CMOS VLSI Design
Bitline ConditioningPrecharge bitlines high before reads
Equalize bitlines to minimize voltage difference when using sense amplifiers
φbit bit_b
φ
bit bit_b
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13: SRAM Slide 20CMOS VLSI Design
Sense AmplifiersBitlines have many cells attached– Ex: 32-kbit SRAM has 256 rows x 128 cols– 128 cells on each bitline
tpd ∝ (C/I) ΔV– Even with shared diffusion contacts, 64C of
diffusion capacitance (big C)– Discharged slowly through small transistors
(small I)Sense amplifiers are triggered on small voltage swing (reduce ΔV)
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13: SRAM Slide 21CMOS VLSI Design
Differential Pair AmpDifferential pair requires no clockBut always dissipates static power
bit bit_bsense_b sense
N1 N2
N3
P1 P2
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13: SRAM Slide 22CMOS VLSI Design
Clocked Sense AmpClocked sense amp saves powerRequires sense_clk after enough bitline swingIsolation transistors cut off large bitline capacitance
bit_bbit
sense sense_b
sense_clk isolationtransistors
regenerativefeedback
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13: SRAM Slide 23CMOS VLSI Design
Twisted BitlinesSense amplifiers also amplify noise– Coupling noise is severe in modern processes– Try to couple equally onto bit and bit_b– Done by twisting bitlines
b0 b0_b b1 b1_b b2 b2_b b3 b3_b
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13: SRAM Slide 24CMOS VLSI Design
Column MultiplexingRecall that array may be folded for good aspect ratioEx: 2 kword x 16 folded into 256 rows x 128 columns– Must select 16 output bits from the 128 columns– Requires 16 8:1 column multiplexers
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13: SRAM Slide 25CMOS VLSI Design
Tree Decoder MuxColumn mux can use pass transistors– Use nMOS only, precharge outputs
One design is to use k series transistors for 2k:1 mux– No external decoder logic needed
B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7A0
A0
A1
A1
A2
A2
Y Yto sense amps and write circuits
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13: SRAM Slide 26CMOS VLSI Design
Single Pass-Gate MuxOr eliminate series transistors with separate decoder
A0A1
B0 B1 B2 B3
Y
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13: SRAM Slide 27CMOS VLSI Design
Ex: 2-way Muxed SRAM
MoreCells
word_q1
write0_q1
φ2
MoreCells
A0
A0
φ2
data_v1
write1_q1
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13: SRAM Slide 28CMOS VLSI Design
Multiple PortsWe have considered single-ported SRAM– One read or one write on each cycle
Multiported SRAM are needed for register filesExamples:– Multicycle MIPS must read two sources or write a
result on some cycles– Pipelined MIPS must read two sources and write
a third result each cycle– Superscalar MIPS must read and write many
sources and results each cycle
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13: SRAM Slide 29CMOS VLSI Design
Dual-Ported SRAMSimple dual-ported SRAM– Two independent single-ended reads– Or one differential write
Do two reads and one write by time multiplexing– Read during ph1, write during ph2
bit bit_b
wordBwordA
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13: SRAM Slide 30CMOS VLSI Design
Multi-Ported SRAMAdding more access transistors hurts read stabilityMultiported SRAM isolates reads from state nodeSingle-ended design minimizes number of bitlines
bA
wordBwordA
wordDwordC
wordFwordE
wordG
bB bC
writecircuits
readcircuits
bD bE bF bG
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13: SRAM Slide 31CMOS VLSI Design
Serial Access MemoriesSerial access memories do not use an address– Shift Registers– Tapped Delay Lines– Serial In Parallel Out (SIPO)– Parallel In Serial Out (PISO)– Queues (FIFO, LIFO)
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13: SRAM Slide 32CMOS VLSI Design
Shift RegisterShift registers store and delay dataSimple design: cascade of registers– Watch your hold times!
clk
Din Dout8
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13: SRAM Slide 33CMOS VLSI Design
Denser Shift RegistersFlip-flops aren’t very area-efficientFor large shift registers, keep data in SRAM insteadMove read/write pointers to RAM rather than data– Initialize read address to first entry, write to last– Increment address on each cycle
Din
Dout
clk
counter counterreset
00...00
11...11
readaddr
writeaddr
dual-portedSRAM
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13: SRAM Slide 34CMOS VLSI Design
Tapped Delay LineA tapped delay line is a shift register with a programmable number of stagesSet number of stages with delay controls to mux– Ex: 0 – 63 stages of delay
SR
32
clk
Din
delay5
SR
16
delay4
SR
8
delay3S
R4
delay2
SR
2
delay1
SR
1
delay0
Dout
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13: SRAM Slide 35CMOS VLSI Design
Serial In Parallel Out1-bit shift register reads in serial data– After N steps, presents N-bit parallel output
clk
P0 P1 P2 P3
Sin
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13: SRAM Slide 36CMOS VLSI Design
Parallel In Serial OutLoad all N bits in parallel when shift = 0– Then shift one bit out per cycle
clkshift/load
P0 P1 P2 P3
Sout
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13: SRAM Slide 37CMOS VLSI Design
QueuesQueues allow data to be read and written at different rates.Read and write each use their own clock, dataQueue indicates whether it is full or emptyBuild with SRAM and read/write counters (pointers)
Queue
WriteClk
WriteData
FULL
ReadClk
ReadData
EMPTY
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13: SRAM Slide 38CMOS VLSI Design
FIFO, LIFO QueuesFirst In First Out (FIFO)– Initialize read and write pointers to first element– Queue is EMPTY– On write, increment write pointer– If write almost catches read, Queue is FULL– On read, increment read pointer
Last In First Out (LIFO)– Also called a stack– Use a single stack pointer for read and write
