3D1-Microprocessor Systems 1

Lecture 18: Instruction Execution and TimingEverything—all the instructions, operands and addressing modes—is encoded in binary code. In Reduced Instruction Set Computers (RISCs), every instruction should be exactly the same length in machine code, typically 32 bits. This makes looking ahead at upcoming instructions simpler. In the 68000, instructions are of variable length, composed of a one-word operation word and zero or more extension words.You need to understand the scheme by which instructions are encoded to understand how to select the fastest or most compact instructions. In this lecture we will look at encoding schemes and approximate speed calculations.Learning Outcomes:On completion of this lecture, you will be able to:

Discuss the stages of the fletch-decode-execute cycle; Describe the internal organisation of the CPU; Describe the makeup of a 68000 instruction; Discuss instructions execution time calculation;

18.1 Instruction ExecutionThe Von Newman architecture model of a computer states that the CPU is responsible for reading instructions from the memory system and executing them. The CPU operates by following the so called fletch-decode-execute cycle:

1. Fetch the operation word2. Decode the operation word*3. Fetch the rest of the instruction—the extension words4. Fetch any off-processor operands5. Perform the operation itself.

The cycle repeats after the CPU takes the time to put away results to off-processor locations. Fig. 19.1 illustrates the CPU’s functional units that make possible the instruction execution cycle. The CPU registers and units involved in the process are:MAR The Memory Address Register holds the address of the next location in the store to

be accessed. The contents of the MAR point to the location of information in memory. For example, if the MAR contains the value $4000, the CPU is going to access address number $4000 in the memory.

PC The Program Counter contains the address of the next instruction to be executed.MBR The Memory Buffer Register holds the data just read from the main store, or data to

be written into the main store. All information that flows into or out of memory passes through the MBR.

IR The Instruction Register holds the most recently read instruction from the main store.ALU The Arithmetic and Logic Unit calculates a function of one or two inputs. The actual

function performed by the ALU is determined by the bit pattern of the instruction in the IR.

CU The Control Unit interprets the instruction in the IR. That is, the CU is responsible for converting the bit pattern of an instruction into the sequence of actions necessary to execute the instruction.

D0 Data Register D0 can be used as an accumulator to hold temporary data in the CPU during arithmetic and logical operations.

CCR The Condition Code Register is used to implement conditional branches.

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3D1-Microprocessor Systems 1

Fetching an instruction begins with the contents of the Program Counter being moved to the Memory Address Register ([MAR] <- [PC]). The MAR is now pointing at the next instruction to be executed. Once the PC has done its job, it is automatically incremented to point the next instruction in sequence. After the increment, the PC points at the next instruction while the current instruction is being executed.

The next step is to read the contents of the memory location pointed at by the MAR. The data read from memory is first deposited in a temporary holding register, the Memory Buffer Register ([MBR]<-[MAR]).

In the final step of the fletch cycle the contents of the MBR are copied the Instruction Register ([IR]<-[MBR]). The IR holds the instruction while it is decoded by the Control Unit. One field of the IR contains the operation code (op-code) that tells the CPU what operation is to be carried out. A second field, called the operand field, contains the address of the data to be used by the instruction.

The fletch phase is followed by an execution phase in which the Control Unit generates all signals necessary to execute the instruction. The CU controls all parts of the CPU including all programmable registers and the Arithmetic and Logic Unit.

A path between the CCR and the CU is used by the CU to decide whether to continue with the next instruction in series, or to jump to the address field specified by the branch field of a conditional instruction.

18.2 Makeup a 68000 instruction

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Fig. 18.1: Structure of a typical CPU

3D1-Microprocessor Systems 1

         

op-word zero or more extension words (max: four)

         

The operation word contains: the operation and size, e.g. MOVE.W, MULU, BNE the types of addressing mode(s) used to reference the operand(s)

Exception: in a quick immediate mode, the op-word also indicates the destination register.

Extension words are used to hold the components of operands that won’t fit into the operation word, which include:

Addresses -- for absolute memory long and short; Immediate values -- byte, word, longword (not Quick Immediate -- they are stored in

the operation word); Offsets -- for the addressing mode ‘Address Register Indirect with Offset’; Index Register and Offset -- for the addressing mode ‘Address Register Indirect with

Index Register and Offset.

MODE SIZE EXTENSION WORDS

Immediatebyteword

longwordAbsolute short

longAddress Register Indirect

(and PC-Relative)With [16-bit signed offset]

With index register and [8-bit signed offset]All Other Modes __ 0 word

18.3 Instruction Execution TimingYou can get a good estimate of an instruction execution time by calculating the number of bus transactions required to:

Fetch the instruction and its extension words; Fetch the off-processor operands; Put away the off-processor results.

The bus can transfer one word (or part) in each transaction (a bus cycle). On the 8MHz 68000, a transaction takes 0.5μS.These estimates assume that bus transactions always take a fixed amount of time. However:

an instruction cache could shorten bus transactions fetching an instruction; a data cache could do the same for fetching or putting away data.

So, these would be worst-case estimates for a machine with a cache. But the 68000 doesn’t have a cache. The 68000 has a one-instruction look-ahead facility:

While the current instruction is being executed, the operation word of the next one is being fetched.

Any operation that takes less than one bus transaction is ‘invisible’ and doesn’t add any overall time to instruction execution (as per our assumption).

A branch requires the pre-fetched operation word to be discarded—penalty: one half of a bus transaction.

Multiply and divide instructions take way in excess on one transaction.18.4 Conclusion

A computer operates following a fletch-decode-execute cycle in which the CPU reads an instruction from memory and then decodes and executes it.

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3D1-Microprocessor Systems 1

Instructions are made of two parts: the operation code and the address of the operands. The op-code is composed of an op-word associated with extension words. Knowledge of instruction timing allows the programmer determine the best instructions and addressing modes to use and the duration a sequence of instructions will take to execute

REFERENCES

Clements; The CPU and its Memory, In: 68000 Family Assembly Language; pp.45-59; PWS Publishing Company; 1994.

Dr. Mike Brady, Microprocessor Systems 1, dept of Computer Science, Trinity College Dublin: http://www.tcd.ie/Engineering/Courses/BAI/JS_Subjects/3D1/.

Look on the Web. Look at http://www.mee.tcd.ie/~assambc/3D1.

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