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Lecture 3: CMOS Transistor Theory
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 2
Outline Introduction MOS Capacitor nMOS I-V Characteristics pMOS I-V Characteristics Gate and Diffusion Capacitance
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Goal of this section Present intuitive understanding of device
operation Introduction of basic device equations Introduction of models for manual
analysis Introduction of models for SPICE
simulation Future trends
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diodes Diodes do not appear in CMOS digital design as
separate devices. However, they are present as junctions and parasitic
elements in all devices. We will use a simple 1D analysis. We will not concern ourselves too much with the DC
behavior too much.
3: CMOS Transistor Theory 4
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Depletion Regionhole diffusion
electron diffusion
p n
hole driftelectron drift
ChargeDensity
Distancex+
-
ElectricalxField
x
PotentialV
W2-W1
(a) Current flow.
(b) Charge density.
(c) Electric field.
(d) Electrostaticpotential.
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
DC Characteristics
3: CMOS Transistor Theory 6
€
φ0 = φT lnNA ND
ni2
⎛
⎝ ⎜
⎞
⎠ ⎟
φT =kT
q= 25.8mV
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diode Current
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Forward Bias
x
pn0
np0
-W1 W20p n
(W2)
n-regionp-region
Lp
diffusionTypically avoided in Digital ICs
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Reverse Bias
x
pn0
np0
-W1 W20n-regionp-region
diffusion
The Dominant Operation Mode
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Models for Manual Analysis
VD
ID = IS(eVD/T – 1)+
–
VD
+
–
+
–VDon
ID
(a) Ideal diode model (b) First-order diode model
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Junction Capacitance
3: CMOS Transistor Theory 11
€
Q j = AD 2ε SiqNA ND
ni2
⎛
⎝ ⎜
⎞
⎠ ⎟ φ0 −VD( )
W =2ε Si
q
NA + ND
NA ND
φ0 −VD( )
Ε j =2q
ε Si
NA ND
NA + ND
⎛
⎝ ⎜
⎞
⎠ ⎟ φ0 −VD( )
C j =dQ j
dVD
= AD
qε Si
2
NA + ND
NA ND
⎛
⎝ ⎜
⎞
⎠ ⎟ φ0 −VD( )
−1
C j =C j 0
1 −VD
φ0
where
C j 0 = AD
qε Si
2
NA + ND
NA ND
⎛
⎝ ⎜
⎞
⎠ ⎟ φ0( )
−1
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Junction Capacitance
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Junction Capacitance m is known as the grading coefficient. Keep in mind that Cj is a small signal parameter. For
large signal switching, an equivalent capacitance has to be calculated as
Ceq has been defined such that the same amount of charge is transferred as the nonlinear model
3: CMOS Transistor Theory 13
€
Ceq =ΔQ j
ΔVD
=Q Vhigh( ) − Q Vlow( )
Vhigh −Vlow
= KeqC j 0
€
Keq =−φ0
m
Vhigh −Vlow( ) 1− m( )φ0 −Vhigh( )
1−m( )− φ0 −Vlow( )
1−m( ) ⎡ ⎣ ⎢
⎤ ⎦ ⎥
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Junction Capacitance As a numerical example, a diode is switched
between 0 and -2.5 V. The diode has Cj0 = 2 X 10-3 F/m2, AD = 0.5 (m)2, 0 = 0.64 V, m = 0.5.
Keq = 0.622, Ceq = 1.24 fF/(m)2.
3: CMOS Transistor Theory 14
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion Capacitance
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion Capacitance Effective in forward bias
3: CMOS Transistor Theory 16€
Qp = qAD pn x( ) − pn 0( )dxW2
Wn
∫
= qAD
Wn −W2( )pn 0 eVD
φ T −1 ⎛
⎝ ⎜
⎞
⎠ ⎟
2
≈Wn
2
2Dp
IDp = τ TpIDp
ID =Qp
τTp
+Qn
τ Tn
≡QD
τT
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Diffusion Capacitance From this lifetime analysis of excess charge,
Note that Cd is also a small signal capacitance
3: CMOS Transistor Theory 17
€
Cd =dQD
dVD
= τT
dID
dVD
≈τ T ID
φT
€
Ceq =ΔQD
ΔVD
=τT ID Vhigh( ) − ID Vlow( )( )
Vhigh −Vlow
=Cd high( ) − Cd low( )
Vhigh −Vlow
φT
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Other Diode Parameters Secondary Effects
– Resistivity of regions outside junction– Breakdown voltage– Temperature dependence
T has a linear dependence
• IS doubles every 8˚C
• Overall, current doubles every 12˚C.
3: CMOS Transistor Theory 18
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SPICE Model The following summarize diode behavior:
n is called the emission coefficient and concentrates the non-idealities listed above.
3: CMOS Transistor Theory 19
€
ID = IS eVD
nφ T −1 ⎛
⎝ ⎜
⎞
⎠ ⎟
CD =τT IS
φT
eVD
nφ T +C j 0
1−VDφ0
⎛ ⎝ ⎜ ⎞
⎠ ⎟m
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SPICE Parameters
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 21
Introduction So far, we have treated transistors as ideal switches An ON transistor passes a finite amount of current
– Depends on terminal voltages– Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance– I = C (V/t) -> t = (C/I) V– Capacitance and current determine speed
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 22
polysilicon gate
(a)
silicon dioxide insulator
p-type body+-
Vg < 0
MOS Capacitor Gate and body form MOS
capacitor Operating modes
– Accumulation– Depletion– Inversion
(b)
+-
0 < Vg < Vt
depletion region
(c)
+-
Vg > Vt
depletion regioninversion region
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 23
Terminal Voltages Mode of operation depends on Vg, Vd, Vs
– Vgs = Vg – Vs
– Vgd = Vg – Vd
– Vds = Vd – Vs = Vgs - Vgd
Source and drain are symmetric diffusion terminals– By convention, source is terminal at lower voltage
– Hence Vds 0
nMOS body is grounded. First assume source voltage is 0 too. Three regions of operation
– Cutoff– Linear (Resistive)– Saturation (Active)
Vg
Vs Vd
VgdVgs
Vds+-
+
-
+
-
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 24
nMOS Cutoff No channel Ids ≈ 0
+-
Vgs = 0
n+ n+
+-
Vgd
p-type body
b
g
s d
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 25
nMOS Linear Channel forms Current flows from d to s
– e- from s to d Ids increases with Vds
Similar to linear resistor
+-
Vgs > Vt
n+ n+
+-
Vgd = Vgs
+-
Vgs > Vt
n+ n+
+-
Vgs > Vgd > Vt
Vds = 0
0 < Vds < Vgs-Vt
p-type body
p-type body
b
g
s d
b
g
s dIds
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 26
nMOS Saturation Channel pinches off Ids independent of Vds
We say current saturates Similar to current source
+-
Vgs > Vt
n+ n+
+-
Vgd < Vt
Vds > Vgs-Vt
p-type body
b
g
s d Ids
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 27
I-V Characteristics In Linear region, Ids depends on
– How much charge is in the channel?– How fast is the charge moving?
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 28
Channel Charge MOS structure looks like parallel plate capacitor
while operating in inversions– Gate – oxide – channel
Qchannel = CV
C = Cg = oxWL/tox = CoxWL
V = Vgc – Vt = (Vgs – Vds/2) – Vt
n+ n+
p-type body
+
Vgd
gate
+ +
source
-
Vgs
-drain
Vds
channel-
Vg
Vs Vd
Cg
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.9)
polysilicongate
Cox = ox / tox
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 29
Carrier velocity Charge is carried by e- Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
Carrier velocity v proportional to lateral E-field – v = E called mobility
Time for carrier to cross channel:– t = L / v
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 30
nMOS Linear I-V Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
channel
ox 2
2
ds
dsgs t ds
dsgs t ds
QI
tW VC V V VL
VV V V
ox = W
CL
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 31
nMOS Saturation I-V If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
Now drain voltage no longer increases current
2
2
2
dsatds gs t dsat
gs t
VI V V V
V V
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 32
nMOS I-V Summary
2
cutoff
linear
saturatio
0
2
2n
gs t
dsds gs t ds ds dsat
gs t ds dsat
V V
VI V V V V V
V V V V
Shockley 1st order transistor models
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 33
Example Your book will be using a 0.6 m process
– From AMI Semiconductor
– tox = 100 Å
– = 350 cm2/V*s
– Vt = 0.7 V
Plot Ids vs. Vds
– Vgs = 0, 1, 2, 3, 4, 5
– Use W/L = 4/2
14
28
3.9 8.85 10350 120 μA/V
100 10ox
W W WC
L L L
0 1 2 3 4 50
0.5
1
1.5
2
2.5
Vds
I ds (m
A)
Vgs = 5
Vgs = 4
Vgs = 3
Vgs = 2
Vgs = 1
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 34
pMOS I-V All dopings and voltages are inverted for pMOS
– Source is the more positive terminal Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2/V•s in AMI 0.6 m process Thus pMOS must be wider to
provide same current– In this class, assume
n / p = 2-5 -4 -3 -2 -1 0
-0.8
-0.6
-0.4
-0.2
0
I ds(m
A)
Vgs = -5
Vgs = -4
Vgs = -3
Vgs = -2
Vgs = -1
Vds
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 35
Capacitance Any two conductors separated by an insulator have
capacitance Gate to channel capacitor is very important
– Creates channel charge necessary for operation Source and drain have capacitance to body
– Across reverse-biased diodes– Called diffusion capacitance because it is
associated with source/drain diffusion
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Level 1 Implementation in SPICE
Including the channel length modulation, body effect and overlaps,
3: CMOS Transistor Theory 36€
ID =με SiO2
tox
W
L − 2LD
VGS −VT −VDS
2
⎛
⎝ ⎜
⎞
⎠ ⎟VDS resistive
ID =με SiO2
tox
W
L − 2LD
VGS −VT
2
⎛
⎝ ⎜
⎞
⎠ ⎟2
1+ λVDS( ) active
VT = VFB + φS +1
Cox
2qε SiNA φS +VSB
VT = VFB + φS + γ φS +VSB
VT = VT 0 + γ VSB + φS − φS( )
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
The Body Effect
-2.5 -2 -1.5 -1 -0.5 00.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
0.85
0.9
VBS
(V)
VT (
V)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SPICE Model
Name Symbol SPICE Name
Type
Lateral Diffusion LD LD Physical
Oxide Thickness tox TOX Physical
Channel length modulation LAMBDA Physical
Surface Mobility U0 Physical
Substrate Doping NA NSUB Physical
Current Parameter kp KP Electrical
Work Function S PHI Electrical
Threshold Voltage VT0 VTO Electrical
Body Effect Parameter GAMMA Electrical
3: CMOS Transistor Theory 38
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
SPICE Model Electrical parameters override when provided. Otherwise, they are calculated from physical
parameters. LAMBDA is an empirical parameter.
3: CMOS Transistor Theory 39
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Level 2 Implementation in SPICE
Now, let us remove some of the wrong assumptions. Voltage across channel is not constant any more The threshold voltage is not a constant any more
3: CMOS Transistor Theory 40
€
VT Vc( ) = VFB + φS + γ φS +VSB +Vc
Vc = Vc y( )
μdVc
dy=
dyQ
ID
IDdy0
L
∫ = μCoxW VGS −VT −Vc( )dVc0
VDS
∫
ID = μCox
W
LVGS −VFB − φS −
VDS
2
⎛
⎝ ⎜
⎞
⎠ ⎟VDS −
2
3γ VDS +VSB + φS( )
32 − φS +VSB( )
32 ⎡
⎣ ⎢ ⎤ ⎦ ⎥
⎧ ⎨ ⎩
⎫ ⎬ ⎭
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Level 2 Implementation in SPICE
To find the equation in the active region, take the derivative of ID and equate to 0.
VDS = VDS,sat when ID is maximum.
Note that ID is dependent on even if VSB = 0.
VT is not explicitly used in the equations.
3: CMOS Transistor Theory 41
€
VDS,sat = VGS −VFB − φS − γ 2 1 − 1+2
γ 2 VGS −VFB( ) ⎛
⎝ ⎜
⎞
⎠ ⎟
12 ⎡
⎣
⎢ ⎢
⎤
⎦
⎥ ⎥
ID,act = ID VDS = VDS,sat( )
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
More Corrections Mobility is reduced with increasing gate voltage.
– We will study this effect in detail later. Current conduction occurs below the threshold
voltage.– We will study this effect later.
Channel length modulation has to be corrected. Threshold voltage depends on W and L. Parasitic resistances in the source and drain Latchup Speed limit of carriers
3: CMOS Transistor Theory 42
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Speed Limit of Carriers Ohm’s Law is not true
3: CMOS Transistor Theory 43
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Speed Limit of Carriers Velocity is proportional to electric field for low fields
Velocity is saturated for high fields
To ensure continuity, use the following approximation for velocity.
Then,
3: CMOS Transistor Theory 44
€
v = μnΕ
€
v = vsat
€
v =μnΕ
1+Ε
Εc
, Εc =2vsat
μn
€
ID =μnCox
1+VDSΕcL
W
LVGS −VT( )VDS −
VDS2
2
⎡
⎣ ⎢
⎤
⎦ ⎥
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Speed Limit of Carriers That equation is still too complex for hand analysis. Substitute the values at the critical electric field to
find the current at the transition point.
An even simpler approach is as follows
3: CMOS Transistor Theory 45
€
Εc =2vsat
μn
ID VDS,sat( ) =2vsatL
μnVDS
μnCox
W
LVGS −VT( )VDS −
VDS2
2
⎡
⎣ ⎢
⎤
⎦ ⎥
= 2vsatCoxW VGS −VT −VDS,sat
2
⎛
⎝ ⎜
⎞
⎠ ⎟
€
v = μnΕ for Ε ≤ E c and v = vsat = μnΕc for Ε ≥Εc
VDS,sat = LΕc =Lvsat
μn
ID,sat = ID VDS = VDS,sat( ) = vsatCoxW VGS −VT −VDS,sat
2
⎛
⎝ ⎜
⎞
⎠ ⎟
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
A Unified Model for Manual Analysis
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Transistor Model for Manual Analysis
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
The Transistor as a Switch
VGS VT
RonS D
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
ID
VDS
VGS = VD D
VDD/2 VDD
R0
Rmid
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Drain-Source Resistance Large signal drain-source resistance is a nonlinear
quantity varying across operating regions. One can define an equivalent resistance
For a weakly nonlinear function,
3: CMOS Transistor Theory 49
€
Req =1
t2 − t1
Vds t( )Id t( )
dtt1
t2
∫
€
Req =1
2
Vds t1( )
Id t1( )+
Vds t2( )
Id t2( )
⎡
⎣ ⎢ ⎢
⎤
⎦ ⎥ ⎥
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Drain-Source Resistance Applying the general formula for a transistor
switching from VDD to VDD/2,
Alternatively, using the endpoints and averaging,
3: CMOS Transistor Theory 50
€
Req ≈3
4
VDD
ID,sat
1−7
9λVDD
⎛
⎝ ⎜
⎞
⎠ ⎟
€
Req ≈3
4
VDD
ID,sat
1−5
6λVDD
⎛
⎝ ⎜
⎞
⎠ ⎟
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Drain-Source Resistance
0.5 1 1.5 2 2.50
1
2
3
4
5
6
7x 10
5
VDD
(V)
Req
(O
hm)
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Drain-Source Resistance
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Drain-Source Resistance Note the following
– R is inversely proportional to W/L
– For VDD >> VT + VD,sat/2, R is independent of VDD.
– When VDD is close to VT, resistance increases.
3: CMOS Transistor Theory 53
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
MOS Capacitances
3: CMOS Transistor Theory 54
DS
G
B
CGDCGS
CSB CDBCGB
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 55
Gate Capacitance Approximate channel as connected to source Cgs = oxWL/tox = CoxWL = CpermicronW
Cpermicron is typically about 2 fF/m
n+ n+
p-type body
W
L
tox
SiO2 gate oxide(good insulator, ox = 3.90)
polysilicongate
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Gate Capacitance
Operation Region Cgb Cgs Cgd
Cut-off CoxWLeff Cov Cov
Resistive 0 CoxWLeff/2 + Cov CoxWLeff/2 + Cov
Active 0 (2/3) CoxWLeff + Cov Cov
3: CMOS Transistor Theory 56
CMOS VLSI DesignCMOS VLSI Design 4th Ed.3: CMOS Transistor Theory 57
Diffusion Capacitance Csb, Cdb
Undesirable, called parasitic capacitance Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Capacitances in 0.25 m CMOS Process
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sub-Threshold Conduction
0 0.5
1 1.5
2 2.5
10
-12
10
-10
10
-8
10
-6
10
-4
10
-2
VGS (V)
I D (A
)
VT
Linear
Exponential
Quadratic
Typical values for S:60 .. 100 mV/decade
The Slope Factor
ox
DnkT
qV
D C
CneII
GS
1 ,~ 0
S is VGS for ID2/ID1 =10
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sub-Threshold ID vs VGS
VDS from 0 to 0.5V
kT
qV
nkT
qV
D
DSGS
eeII 10
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Sub-Threshold ID vs VDS
DSkT
qV
nkT
qV
D VeeIIDSGS
110
VGS from 0 to 0.3V
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Scaling
Parameter Relation Full Scaling Fixed V scaling
General Scaling
W, L, tox - 1/S 1/S 1/S
VDD, VT - 1/S 1 1/U
NSUB V/W2depl S S2 S2/U
Area/Device WL 1/S2 1/S2 1/S2
Cox 1/tox S S S
Cgate CoxWL 1/S 1/S 1/S
kn, kp CoxW/L S S S
3: CMOS Transistor Theory 62
CMOS VLSI DesignCMOS VLSI Design 4th Ed.
Scaling (Continued)
Parameter Relation Full Scaling Fixed V Scaling
General Scaling
ID,sat CoxWV 1/S 1 1/U
Current Density
ID,sat/Area S S2 S2/U
Ron V/ID,sat 1 1 1
Intrinsic Delay
RonCgate 1/S 1/S 1/S
Power ID,satV 1/S2 1 1/U2
Power Density
Power/Area 1 S2 S2/U2
3: CMOS Transistor Theory 63