Lecture 4 Design Rules,Layout
and Stick Diagram
Pradondet Nilagupta
Department of Computer Engineering
Kasetsart University
April 11, 2023 204424 Digital Design Automation2
Acknowledgement
This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished.
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Roadmap for the term: major topics
VLSI Overview CMOS Processing & Fabrication Components: Transistors, Wires, & Parasitics Design Rules & Layout Combinational Circuit Design & Layout Sequential Circuit Design & Layout Standard-Cell Design with CAD Tools Systems Design using Verilog HDL Design Project: Complete Chip
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P substrate
Review - CMOS Mask Layers
Determine placement of layout objects
Color coding specifies layers
Layout objects: Rectangles Polygons Arbitrary shapes
Grid types Absolute (“micron”) Scaleable (“lambda”) wafer
n well
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Mask Generation
Mask Design using Layout Editor user specifies layout objects on different layers output: layout file
Pattern Generator Reads layout file Generates enlarged master image of each mask layer Image printed on glass
Step & repeat camera Reduces & copies image onto mask One copy for each die on wafer Note importance of mask alignment
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Symbolic Mask Layers
Key idea: Reduce layers to those that describe design Generate physical layers as needed
Magic Layout Editor: "Abstract Layers” metal1 (blue) - 1st layer metal (equiv. to physical layer) Poly (red) - polysilicon (equivalent to physical layer) ndiff (green) - n diffusion (combination of active, nselect) ntranistor (green/red crosshatch) - combined poly, ndiff pdiff (brown) - p diffusion (combination of active, pselect) ptransistor (brown/red crosshatch) - combined poly, pdiff contacts: combine layers, cut mask
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About Magic
Scalable Grid for Scalable Design Rules Grid distance: lambda) Value is process-dependent:
= 0.5 X minimum transistor length Painting metaphor
Paint squares on grid for each mask layer Layers to interact to form components (e.g.
transistors)
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Mask Layers in Magic
Poly (red) N Diffusion (green) P Diffusion (brown) Metal (blue) Metal 2 (purple) Well (cross-hatching) Contacts (X)
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Magic User-Interface
Graphic Display Window Cursor Box - specifies area to paint
Command window (not shown) accepts text commands:paint poly:paint red:paint ndiff:paint green:write
prints error & status messages
Cursor
Box
Paint(poly)
Paint(pdiff)
Paint(ntransistor)
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Layer Interaction in Magic
Transistors - where poly, diffusion cross poly crosses ndiffusion - ntransistor poly crosses pdiffusion - ptransistor
Vias - where layers connect Metal 1 connecting to Poly - polycontact Metal 1 connecting to P-Diffusion (normal) - pdc Metal 1 connecting to P-Diffusion (substrate contact) - psc Metal 1 connecting to N-Diffusion (normal) - ndc Metal 1 connecting to N-Diffusion (substrate contact) - nsc Metal 1 connecting to Metal 2 - via
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Magic Layers - Example
nwell
nsc
psc
p-transistor
ntransistor
metal1
metal1
metal1
poly
poly
ndc ndc
polycontact
polycontact
pdc
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Why we need design rules
Masks are tooling for manufacturing. Manufacturing processes have inherent
limitations in accuracy. Design rules specify geometry of masks
which will provide reasonable yields. Design rules are determined by experience.
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Manufacturing problems
Photoresist shrinkage, tearing. Variations in material deposition. Variations in temperature. Variations in oxide thickness. Impurities. Variations between lots. Variations across a wafer.
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Transistor problems
Varaiations in threshold voltage: oxide thickness; ion implanatation; poly variations.
Changes in source/drain diffusion overlap. Variations in substrate.
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Wiring problems
Diffusion: changes in doping -> variations in resistance, capacitance.
Poly, metal: variations in height, width -> variations in resistance, capacitance.
Shorts and opens:
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Oxide problems
Variations in height. Lack of planarity -> step coverage.
metal 1metal 2
metal 2
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Via problems
Via may not be cut all the way through. Undesize via has too much resistance. Via may be too large and create short.
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MOSIS SCMOS design rules
Designed to scale across a wide range of technologies.
Designed to support multiple vendors. Designed for educational use. Ergo, fairly conservative.
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and design rules
is the size of a minimum feature. Specifying particularizes the scalable rules. Parasitics are generally not specified in
units
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Design Rules
Typical rules:Minumum sizeMinimum spacingAlignment / overlapCompositionNegative features
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Types of Design Rules
Scalable Design Rules (e.g. SCMOS) Based on scalable “coarse grid” - (lambda) Idea: reduce value for each new process, but keep rules
the sameKey advantage: portable layoutKey disadvantage: not everything scales the same
Not used in “real life” Absolute Design Rules
Based on absolute distances (e.g. 0.75µm) Tuned to a specific process (details usually proprietary) Complex, especially for deep submicron Layouts not portable
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SCMOS Design Rules
Intended to be Scalable Original rules: SCMOS Submicron: SCMOS-SUBM Deep Submicron: SCMOS-DEEP
Pictorial Summary: Book Fig. 2-24, p. 27 Authoritative Reference: www.mosis.org
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SCMOS Design Rule Summary
Line size and spacing: metal1: Minimum width=3, Minimum Spacing=3 metal2: Minimum width=3, Minimum Spacing=4 poly: Minimum width= 2, Minimum Spacing=2 ndiff/pdiff: Minimum width= 3, Minimum Spacing=3
minimum ndiff/pdiff seperation=10 wells: minimum width=10,
min distance form well edge to source/drain=5 Transistors:
Min width=3 Min length=2 Min poly overhang=2
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SCMOS Design Rule Summary
Contacts (Vias) Cut size: exactly 2 X 2 Cut separation: minimum 2 Overlap: min 1 in all directions Magic approach: Symbolic contact layer min. size 4 X 4 Contacts cannot stack (i.e., metal2/metal1/poly)
Other rules cut to poly must be 3 from other poly cut to diff must be 3 from other diff metal2/metal1 contact cannot be directly over poly negative features must be at least 2 in size CMP Density rules (AMI/HP subm): 15% Poly, 30% Metal
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Design Rule Checking in Magic
Design violations displayed as error paint
Find which rule is violated with ":drc why” Poly must overhang transistor by at least 2 (MOSIS rule #3.3)
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Scaling Design Rules
Effects of scaling down are positive See book, p. 78-79 - if “everything” scales,
scaling circuit by 1/x increases performance by x
Problem: not everything scales proportionally
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Aside - About MOSIS
MOSIS - MOS Implementation Service Rapid-prototyping for small chips
Multi-project chip idea - several designs on the same wafer
Reduced mask costs per design Accepts layout designs via email Brokers fabrication by foundries
(e.g. AMI, Agilent, IBM, TSMC) Packages chips & ships back to designers
Our designs will use AMI 1.5µm process (more about this later)
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Aside - About MOSIS
Some Typical MOSIS Prices (from www.mosis.org) AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) $1,080 AMI 1.5µm 9.4mm X 9.7mm $17,980 AMI 0.5µm 0-5mm2 $5,900 TSMC 0.25µm 0-10mm2 $15,550 TSMC 0.18µm 0-7mm2 $24,500 TSMC 100-159mm2 $63,250 + $900 X size
MOSIS Educational Program (what we use) AMI 1.5µm “Tiny Chip” (2.2mm X 2.2mm) FREE* AMI 0.5mm “Tiny Chip” (1.5mm X 1.5mm) FREE*
*sponsored by Semiconductor Industry Assn., Semiconductor Research Corp., | AMI, Inc., DuPont Photomasks, and MOSIS
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Layout Considerations
Break layout into interconnected cells Use hierarchy to control complexity Connect cells by
Abutment Added wires
Key goals: Minimize size of overall layout Meet performance constraints Meet design time deadlines
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Hierarchy in Layout
Chips are constructed as a hierarchy of cells Leaf cells - bottom of hierarchy Root cells - contains overall cell
Example - hypothetical “UART” Pad frame - “ring” that contains I/O pads Core - contains logic organized as subcells
Shift registerFSMOther cells
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Hierarchy Example
Root Cell: UART
Root Cell: UART
Pad Frame
Core
Pad 1 Pad 2 ... Pad NShift
RegisterFSM
Other Cells
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Wires
metal 36
metal 23
metal 13
pdiff/ndiff3
poly2
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Transistors
2
3
1
3 2
5
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Vias
Types of via: metal1/diff, metal1/poly, metal1/metal2.
4
1
4
2
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Metal 3 via
Type: metal3/metal2. Rules:
cut: 3 x 3 overlap by metal2: 1 minimum spacing: 3 minimum spacing to via1: 2
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Tub tie
4
1
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Spacings
Diffusion/diffusion: 3 Poly/poly: 2 Poly/diffusion: 1 Via/via: 2 Metal1/metal1: 3 Metal2/metal2: 4 Metal3/metal3: 4
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Overglass
Cut in passivation layer. Minimum bonding pad: 100 m. Pad overlap of glass opening: 6 Minimum pad spacing to unrelated metal2/3:
30 Minimum pad spacing to unrelated metal1,
poly, active: 15
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Stick diagrams (1/3)
A stick diagram is a cartoon of a layout. Does show all components/vias (except
possibly tub ties), relative placement. Does not show exact placement, transistor
sizes, wire lengths, wire widths, tub boundaries.
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Stick Diagrams (2/3)
Key idea: "Stick figure cartoon" of a layout Useful for planning layout
relative placement of transistors assignment of signals to layers connections between cells cell hierarchy
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Stick Diagrams (3/3)
Metal (BLUE)
Polysilicion (RED )
N-Diffusion (Green)
P-Diffusion (Brown)
Contact / Via
poly
n-diff
p-diff
metal
poly n-diff p-diff metal
S N P NC
S X NC
S NC
S
Connection RulesLayers
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Example - Stick Diagrams (1/2)
A B
A
B
Circuit Diagram. Pull-Down Network(The easy part!)
Alternatives - Pull-up Network
Complete Stick Diagram
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Example - Stick Diagrams (2/2)
Inverter
Vdd
In
Gnd
Out
NAND Gate
Vdd
AOut
Gnd
B
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Dynamic latch stick diagram
VDD
in
VSSphiphi’
out
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Stick Diagram XOR Gate Examples
Exclusive OR Gate
Vdd
A
Out
GndB
A’ B’
A’
B’
BA’
Out
A A’
B B’
A
B’
A
B
A’
B’
A’
B
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Hierarchical Stick Diagrams
Define cells by outlines & use in a hierarchy to build more complex cells
VddA
Out
Gnd
B
Vdd
Gnd
VddA
Out
Gnd
B
Vdd
Gnd
NAND
NAND CellStick Diagram
NAND CellOutline
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Cell Connection Schemes
External connection - wire cells together Abutment - design cells to connect when
adjacent Reflection, mirroring - use to make abutment
possible
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Example: 2-input multiplexer
First cut:Vdd
A
Out
NAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
NAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
NAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
S
B
S’
Gnd
A
S
B
S’
OUT
OUT = A*S + B*S’
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Sticks design of multiplexer
Start with NAND gate:
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NAND sticks
VDD
a
VSS
out
b
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Refined one-bit Mux Design
Use NAND cell as black box Arrange easy power connections Vertical connections for allow multiple bits
NAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
select’ select
NAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
VddAB
Gnd
Out
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3-bit mux sticks
m2(one-bit-mux)select’ select VDD
VSSoi
ai
bi
m2(one-bit-mux)select’ select VDD
VSSoi
ai
bi
m2(one-bit-mux)select’ select VDD
VSSoi
ai
bi
select’ select
a2
b2
a1
b1
a0
b0
o2
o1
o0
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Multiple-Bit Mux
select’ select
NAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
VddA0A0
Gnd
Out0
NAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
VddA1B1
Gnd
Out1
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Cell Mirroring, Overlap
Use mirroring, overlap to save area
VddA0B0
Gnd
NAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
OutNAND
A
B
Gnd
Vdd
Gnd
Vdd
Out
B1A1
Vdd
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Example: Layout / Stick Diagram
Create a layout for a NAND gate given constraints: Use minimum-size transistors Assume power supply lines “pass through” cell
from left to right at top and bottom of cell Assume inputs are on left side of cell Assume output is on right side of cell Optimize cell to minimize width Optimize cell to minimize overall area
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Layout Example
A B
A
B
A
B
OUT
Vdd!Vdd!
Gnd! Gnd!
Circuit Diagram. Exterior of Cell
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Example - Magic Layout
Overall Layout: 52 X 16
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Review - VLSI Levels of Abstraction
Specification(what the chip does, inputs/outputs)
Architecturemajor resources, connections
Register-Transferlogic blocks, FSMs, connections
Circuittransistors, parasitics, connections
Layoutmask layers, polygons
Logicgates, flip-flops, latches, connections
You are Here
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Levels of Abstraction - Perspective
Right now, we’re focusing on the “low level”: Circuit level - transistors, wires, parasitics Layout level - mask objects
We’ll work upward to higher levels: Logic level - individual gates, latches, flip-flops Register- transfer level - Verilog HDL Behavior level - Specifications
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The Challenge of Design
Start: higher level (spec) Finish: lower level (implementation) Must meet design criteria and constraints
Design time - how long did it take to ship a product?
Performance - how fast is the clock? Cost - NRE + unit cost
CAD tools - essential in modern design
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CAD Tool Survey: Layout Design
Layout Editors Design Rule Checkers (DRC) Circuit Extractors Layout vs. Schematic (LVS) Comparators Automatic Layout Tools
Layout Generators ASIC: Place/Route for Standard Cells, Gate
Arrays
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Layout Editors
Goal: produce mask patterns for fabrication Grid type:
Absolute grid (MAX, LASI, LEdit, Mentor ICStation, other commercial tools)
Magic: lambda-based grid - easier to learn, but less powerful
Mask description: Absolute mask (one layer for each mask) Magic: symbolic masks (layers combine to
generate actual mask patterns)
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Design Rule Checkers
Goal: identify design rule violations Often a separate tool (built in to Magic) General approach: “scanline” algorithm Computationally intensive, especially for
large chips
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Circuit Extractors
Goal: extract netlist of equivalent circuit Identify active components Identify parasitic components
CapacitorsResistors
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Layout Versus Schematic (LVS)
Goal: Compare layout, schematic netlists Compare transistors, connections (ignore
parasitics) Issue error if two netlists are not equivalent Important for large designs
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Automatic Layout Tools
Layout Generators - produce cell from spec. Simple: Procedural specification of layout (see book Fig. 2-33, p. 95) Complex: Netlist - places & wires individual
transistors ASIC - Place, route modules with fixed shape
Standard Cells - use predefined cells as "cookie cutters"
Gate Arrays - configurable pre-manufactured gates (only change metal masks)
FPGAs - electrically configurable array of gates
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Layout design and analysis tools
Layout editors are interactive tools. Design rule checkers are generally batch---
identify DRC errors on the layout. Circuit extractors extract the netlist from the
layout. Connectivity verification systems (CVS)
compare extracted and original netlists.
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Automatic layout
Cell generators (macrocell generators) create optimized layouts for ALUs, etc.
Standard cell/sea-of-gates layout creates layout from predesigned cells + custom routing. Sea-of-gates allows routing over the cell.
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Standard cell layout
routing area
routing arearout
ing
area
routing area