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Lecture 7: Power
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Page 1: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

Lecture 7: Power

Page 2: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 2CMOS VLSI DesignCMOS VLSI Design 4th Ed.

OutlinePower and EnergyDynamic PowerStatic Power

Page 3: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 3CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Power and EnergyPower is drawn from a voltage source attached to the VDD pin(s) of a chip.

Instantaneous Power:

Energy:

Average Power:

( ) ( ) ( )P t I t V t=

0

( )T

E P t dt= ∫

avg0

1 ( )TEP P t dt

T T= = ∫

Page 4: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 4CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Power in Circuit Elements

( ) ( )VDD DD DDP t I t V=

( ) ( ) ( )2

2RR R

V tP t I t R

R= =

( ) ( ) ( )

( )

0 0

212

0

C

C

V

C

dVE I t V t dt C V t dtdt

C V t dV CV

∞ ∞

= =

= =

∫ ∫

Page 5: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 5CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Charging a CapacitorWhen the gate output rises– Energy stored in capacitor is

– But energy drawn from the supply is

– Half the energy from VDD is dissipated in the pMOS transistor as heat, other half stored in capacitor

When the gate output falls– Energy in capacitor is dumped to GND– Dissipated as heat in the nMOS transistor

212C L DDE C V=

( )0 0

2

0

DD

VDD DD L DD

V

L DD L DD

dVE I t V dt C V dtdt

C V dV C V

∞ ∞

= =

= =

∫ ∫

Page 6: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 6CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Switching WaveformsExample: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

Page 7: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 7CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Switching Power

[ ]

switching0

0

sw

2sw

1 ( )

( )

T

DD DD

TDD

DD

DDDD

DD

P i t V dtT

V i t dtT

V Tf CVT

CV f

=

=

=

=

C

fswiDD(t)

VDD

Page 8: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 8CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Activity FactorSuppose the system clock frequency = fLet fsw = αf, where α = activity factor– If the signal is a clock, α = 1– If the signal switches once per cycle, α = ½

Dynamic power:2

switching DDP CV fα=

Page 9: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 9CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Short Circuit CurrentWhen transistors switch, both nMOS and pMOS networks may be momentarily ON at onceLeads to a blip of “short circuit” current.< 10% of dynamic power if rise/fall times are comparable for input and outputWe will generally ignore this component

Page 10: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 10CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Power Dissipation SourcesPtotal = Pdynamic + Pstatic

Dynamic power: Pdynamic = Pswitching + Pshortcircuit

– Switching load capacitances– Short-circuit current

Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD

– Subthreshold leakage– Gate leakage– Junction leakage– Contention current

Page 11: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 11CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Dynamic Power Example1 billion transistor chip– 50M logic transistors

• Average width: 12 λ• Activity factor = 0.1

– 950M memory transistors• Average width: 4 λ• Activity factor = 0.02

– 1.0 V 65 nm process– C = 1 fF/μm (gate) + 0.8 fF/μm (diffusion)

Estimate dynamic power consumption @ 1 GHz. Neglect wire capacitance and short-circuit current.

Page 12: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 12CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Solution( )( )( )( )( )( )( )( )

( ) ( )

6logic

6mem

2dynamic logic mem

50 10 12 0.025 / 1.8 / 27 nF

950 10 4 0.025 / 1.8 / 171 nF

0.1 0.02 1.0 1.0 GHz 6.1 W

C m fF m

C m fF m

P C C

λ μ λ μ

λ μ λ μ

= × =

= × =

⎡ ⎤= + =⎣ ⎦

Page 13: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 13CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Dynamic Power Reduction

Try to minimize:– Activity factor– Capacitance– Supply voltage– Frequency

2switching DDP CV fα=

Page 14: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 14CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Activity Factor EstimationLet Pi = Prob(node i = 1)– Pi = 1-Pi

αi = Pi * Pi

Completely random data has P = 0.5 and α = 0.25Data is often not completely random– e.g. upper bits of 64-bit words representing bank

account balances are usually 0 Data propagating through ANDs and ORs has lower activity factor– Depends on design, but typically α ≈ 0.1

Page 15: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 15CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Switching Probability

Page 16: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 16CMOS VLSI DesignCMOS VLSI Design 4th Ed.

ExampleA 4-input AND is built out of two levels of gatesEstimate the activity factor at each node if the inputs have P = 0.5

Page 17: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 17CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Clock GatingThe best way to reduce the activity is to turn off the clock to registers in unused blocks– Saves clock activity (α = 1)– Eliminates all switching activity in the block– Requires determining if block will be used

Page 18: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 18CMOS VLSI DesignCMOS VLSI Design 4th Ed.

CapacitanceGate capacitance– Fewer stages of logic– Small gate sizes

Wire capacitance– Good floorplanning to keep communicating

blocks close to each other– Drive long wires with inverters or buffers rather

than complex gates

Page 19: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 19CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Voltage / FrequencyRun each block at the lowest possible voltage and frequency that meets performance requirementsVoltage Domains– Provide separate supplies to different blocks– Level converters required when crossing

from low to high VDD domains

Dynamic Voltage Scaling– Adjust VDD and f according to

workload

Page 20: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 20CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Static PowerStatic power is consumed even when chip is quiescent.– Leakage draws power from nominally OFF

devices– Ratioed circuits burn power in fight between ON

transistors

Page 21: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 21CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Static Power ExampleRevisit power estimation for 1 billion transistor chipEstimate static power consumption– Subthreshold leakage

• Normal Vt: 100 nA/μm• High Vt: 10 nA/μm• High Vt used in all memories and in 95% of

logic gates– Gate leakage 5 nA/μm– Junction leakage negligible

Page 22: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 22CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Solution

( )( )( )( )

( )( )( ) ( )( ) ( )

( )

t

t

t t

t t

6 6normal-V

6 6 6high-V

normal-V high-V

normal-V high-V

50 10 12 0.025 m / 0.05 0.75 10 m

50 10 12 0.95 950 10 4 0.025 m / 109.25 10 m

100 nA/ m+ 10 nA/ m / 2 584 mA

5 nA/ m / 2

sub

gate

W

W

I W W

I W W

λ μ λ μ

λ λ μ λ μ

μ μ

μ

= × = ×

⎡ ⎤= × + × = ×⎣ ⎦⎡ ⎤= × × =⎣ ⎦⎡ ⎤= + × =⎣ ⎦( )( )

275 mA

P 584 mA 275 mA 1.0 V 859 mWstatic = + =

Page 23: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 23CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Subthreshold LeakageFor Vds > 50 mV

Ioff = leakage at Vgs = 0, Vds = VDD

( )

10gs ds DD sbV V V k V

Ssub offI I

γη+ − −

Typical values in 65 nmIoff = 100 nA/μm @ Vt = 0.3 VIoff = 10 nA/μm @ Vt = 0.4 VIoff = 1 nA/μm @ Vt = 0.5 Vη = 0.1kγ = 0.1S = 100 mV/decade

Page 24: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 24CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Stack EffectSeries OFF transistors have less leakage– Vx > 0, so N2 has negative Vgs

– Leakage through 2-stack reduces ~10x– Leakage through 3-stack reduces further

( ) ( )( )

2 1

10 10x DD x DD xx DD V V V V k VV V

S Ssub off off

N N

I I Iγηη − + − − −−

= =

1 2DD

xVV

ηη

=+ +

11 2

10 10DD

DD

kV

k VS S

sub off offI I I

γ

γ

ηη

η η

⎛ ⎞+ +− ⎜ ⎟⎜ ⎟+ + −⎝ ⎠

= ≈

Page 25: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 25CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Leakage ControlLeakage and delay trade off– Aim for low leakage in sleep and low delay in

active modeTo reduce leakage:– Increase Vt: multiple Vt

• Use low Vt only in critical circuits– Increase Vs: stack effect

• Input vector control in sleep– Decrease Vb

• Reverse body bias in sleep• Or forward body bias in active mode

Page 26: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 26CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Gate LeakageExtremely strong function of tox and Vgs

– Negligible for older processes– Approaches subthreshold leakage at 65 nm and

below in some processesAn order of magnitude less for pMOS than nMOSControl leakage in the process using tox > 10.5 Å– High-k gate dielectrics help– Some processes provide multiple tox

• e.g. thicker oxide for 3.3 V I/O transistorsControl leakage in circuits by limiting VDD

Page 27: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 27CMOS VLSI DesignCMOS VLSI Design 4th Ed.

NAND3 Leakage Example100 nm processIgn = 6.3 nA Igp = 0Ioffn = 5.63 nA Ioffp = 9.3 nA

Data from [Lee03]

Page 28: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 28CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Junction LeakageFrom reverse-biased p-n junctions– Between diffusion and substrate or well

Ordinary diode leakage is negligibleBand-to-band tunneling (BTBT) can be significant– Especially in high-Vt transistors where other

leakage is small– Worst at Vdb = VDD

Gate-induced drain leakage (GIDL) exacerbates– Worst for Vgd = -VDD (or more negative)

Page 29: Lecture 7: Power - Harvey Mudd Collegepages.hmc.edu/harris/cmosvlsi/4e/lect/lect7.pdf7: Power CMOS VLSI DesignCMOS VLSI Design 4th Ed. 8Activity Factor Suppose the system clock frequency

7: Power 29CMOS VLSI DesignCMOS VLSI Design 4th Ed.

Power GatingTurn OFF power to blocks when they are idle to save leakage– Use virtual VDD (VDDV)– Gate outputs to prevent

invalid logic levels to next block

Voltage drop across sleep transistor degrades performance during normal operation– Size the transistor wide enough to minimize

impactSwitching wide sleep transistor costs dynamic power– Only justified when circuit sleeps long enough


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