Lecture 8 Frequency Synthesizer PLL - Auburn Universityagrawvd/COURSE/RFIC_July08... · RFIC Design...

RFIC Design and Testing for Wireless Communications

A PragaTI (TI India Technical University) CourseJuly 18, 21, 22, 2008

Lecture 8: Frequency synthesizer design I (PLL)

By

Vishwani D AgrawalVishwani D. AgrawalFa Foster Dai

200 Broun Hall, Auburn UniversityAuburn, AL 36849-5201, USA

1

RFIC Design and Testing for Wireless Communications

TopicsMonday, July 21, 2008

9:00 – 10:30 Introduction – Semiconductor history, RF characteristics

11:00 – 12:30 Basic Concepts – Linearity, noise figure, dynamic range2:00 – 3:30 RF front-end design – LNA, mixer4:00 – 5:30 Frequency synthesizer design I (PLL)

T d J l 22 2008Tuesday, July 22, 2008

9:00 – 10:30 Frequency synthesizer design II (VCO)

11:00 – 12:30 RFIC design for wireless communications2:00 – 3:30 Analog and mixed signal testing

Frequency synthesizer design I (PLL), FDAI, 2008 2

Phase Lock Loop Integer-N Frequency Synthesizer

f

Transfer function that controls

loop dynamics (LPF)Phase

Comparator reffNfo ⋅=fr

C t ll bl Si l

+ F(s)F(s)reference

(input) ffb

÷N

Controllable Signal Source (VCO)

Divider

fo synthesized signal(output)Digital signal

to control the value of N

N is an integer the minimum step size = fr to get a smaller step size, the reference frequency must be made smaller N must be higher in order to generate the same fo

larger phase noise (in band noise magnified 20logN times by the loop)


larger phase noise (in-band noise magnified 20logN times by the loop).

Fractional-N Conceptp

If the loop divisor N is a fractional number, e.g., N=K/F, where K and F are integer numbers the minimum step size = fr /F can achieve small step size without lowering the reference frequency loop divisor N can be small in order to generatelowering the reference frequency loop divisor N can be small in order to generate the same fo better phase noise (in-band noise magnified 20logN times by the loop).

How can we design a fractional divider? Divider is a digital block and its output transits only at the input clock edge we can only generate integer frequency divider!!only at the input clock edge we can only generate integer frequency divider!!

Dual-modulus divider P/P+1: by toggling between the two integer division ratios, a fractional division ratio can be achieved by time-averaging the divider output. As an example if the control changes the division ratio between 8 and 9 and the dividerexample, if the control changes the division ratio between 8 and 9, and the divider divides by 8 for 9 cycles and by 9 for 1 cycle and then the process repeats itself, then the average division ratio will be:

1.810

1998=

×+×=N


Fractional-N synthesizer with a dual modulus prescaler


l d i (LPF)

⎥⎦⎤

⎢⎣⎡ +=⎥⎦

⎤⎢⎣⎡ −++

=FKP

Rf

FKFPKP

Rff rr

o)()1(

fr÷R + F(s)F(s)

loop dynamics (LPF)

f

RFfr=SizeStep

Dual Modulus Divider

÷P/P+1


ffb

÷P/P+1

Cout

+CLK

Carryout bit

fosynthesized

signal(output)

+z-1 Klog2F+

FractionalAccumulator

yI

yI-1

FKff clk

C =out


Fractional-N frequency synthesizer with a multi modulus dividerwith a multi-modulus divider

nn

nn

n PPPPN 222...2 11

22

11MMD ++++= −

−−

fr÷R + F(s)F(s)


loop dynamics (LPF)

f

Modulus

Multi-Modulus Divider

MMD

f


ffb

⎥⎦⎤

⎢⎣⎡ +=

FKI

Rff r

o

F ti l di i K/F

+ Integer divisor I+

+Total divisor I+K/F

Moduluscontrol nbit fo

⎦⎣

Fractional divisor K/F

+z-1 Klog2F

Cout

+

+

FractionalAccumulator

CLK1bit


Fractional-N Spurious ComponentsAny repeatable pattern in the time domain causes spurious tones in the frequency domain.

The fractional accumulator periodically generates the carry out that toggles theThe fractional accumulator periodically generates the carry out that toggles the loop division ratio spurious tones at multiples of the carryout frequency fr⋅(K/F), which is the step size of the fractional-N synthesizer. the smaller the step size is, the closer the spur locates to the carrier.

102 20)

(a)

99

100

101

102

-20

0

20

agni

tude

(dB

)

98

4030 4040 4050 4060 4070 4080 4090Clock Cycles

0.1

-40M

1.0 10


PLL Frequency Synthesizer

( )oRe Ksv θθ −= PD)( ( )oRPDCPd KKi θθ −= ( )( )( )

1 1CPPD RsCKKv oRc

+−=

θθ

UP id

I

VDD

θR(s) Kphase

vc(s)Crystal

Loop Filterθ (s)

( )( ) )1(21 RsCCCs s

c ++

Magnitude Response

21

21

CCCCCs +

=

DN

I

R

C1

C2

θo(s)Kvco

PFD

CrystalOscillator

θe(s)

2CCRK S

phase

21CCCS =where

Gain

1

1RC SRC

1

Response

ω

Ks VCOVCO )(=

θsK

Nvc

VCOo 1⋅=

θ

÷Ns

VCODivider

21 CCCS +

where S

Phase∠

Phase Response

cvKVCOVCO =ω

ssvc )(=

1

1RC SRC

1 ω


Open Loop Transfer Function

( )( ) )1(

1

212

1CPPDVCO

loopopen

o

RsCCCNsRsCKKK

sR +++

=⎟⎟⎠

⎞⎜⎜⎝

⎛θθ C2 (about C1/10) adds a high

frequency pole to clean up high f i l th t l li

Magnitude of -20 dB/dec

-40 dB/dec

0

,

21

2

==CCC

CWithout

frequency ripple on the control line.

the Loop Gain

ω

20 dB/dec

40 dB/dec

021

=+

=CC

Cs

Phase of the Loop Gain

°− 90

-40 dB/dec

1RC RC

1 ω

°−135°−180


1RC SRC

Closed Loop Transfer Function

( )( ) ( )RsCKKKRsCCCNs

RsCKKK

sR 1CPPDVCO212

1CPPDVCOo

1)1(1

+++++

=θθ

0, 2

2 =−

sCCWithoutorderPLLnd ( )

( )RsCKKKNCsRsCKKK

R 1CPPDVCO12

1CPPDVCOo

11

+++

=θθ

22

2

o

12

nn s

ωζω

θ ⎟⎟⎠

⎞⎜⎜⎝

⎛+

=

natural frequency 5

0R

o

θθ

(dB)

0.7070.5ζ=0.3

NCK

n =ω22 2 nnR ss ωζωθ ++

damping constant 242

-5

-10

R

1.414

2R

CVN

Kω

⋅VCO (dB)

ζ=5or1NC

NKCR 1

2=ζ

24421 242dB3 ++++= ζζζωω n -15

-200.1 1 10

ω /ω n

0.2 0.4 0.7 2 4 70.3

1

0.5

0.707

5.12dB3 >=≈ ζζωω NKn

( ) 5.121d3 <+≈ ζωζω nB


PLL frequency response dB3 ζζ n

MMD Architecture Using 2/3 Cells

15~8248)3(bit MMD, 3For 2222

012

0122

11

=+++==+++++= −

−−

−

CCCnNCCCCN

MMD

nn

nnn

MMD L

Say, we need an MMD with division ratios: 128-135.

)(, 012MMD

The division ratios obtained using 2/3 cells: 128-255.01

12

23

34

45

56

67 2222222 CCCCCCCN +++++++=


Dual Modulus Prescaler – 2/3 Cell

modin=1 and C=1 Fo/Fin=1/3; modin=1 and C=0 Fo/Fin=1/2modin=0 and p=x Fo/Fin=1/2

Dualmoduluscontrol


Tri-State PFD Circuit IN

FFOUTH UP CLK

CLK RSTvR OUT

CLK

IN

FFOUT

RST

H

vo

DN RSTH DN

Positive edge-triggered D flip flop with active lowflip-flop with active low reset and hidden D=1


PFD Dead Zone

idI

dead zone

−π0

-I

2π θe−2π

Tτπ π

Tτπ−

Dead Zone

vo

Δ

Pha

se N

oise

In band Noise

VCO Noise

vR

DN

Δ Δ

P

Thermal Noise Floor

UP

AND Gate Threshold

τ/2 τ/2

Frequency Offset


Phase/Frequency Detector

D Q Phir1

rst_fr

active highlock detect

LDw r

eset

t

rst

LD

activ

e lo

w polarityif low, KV>0if high, KV<0

reset_Delay

D Q

rst_fV

PhiV1


Differential charge pump circuitry

VVCC

CPoutUP+ DOWN+

Vref

UP-

Vref

DOWN-


2nd Order Passive Loop Filters

IPPFD

Charge Pump

VCOL Filt

RC CI

VCOUP

DN

+

-

K

ICP

Loop FilterVCP

÷N

C1 C2InphaseK

( ) ( )( ) )1(

1 1

RsCCCsRsCsF++

+=The 2nd-order filter is the

highest order passive RC filter ( ) )1(21 RsCCCs s++

21

21

CCCCCs +

=

highest order passive RC filter that can be built without series resistors between the charge pump and the VCO tune line


21

Spectrum analyzer basic block diagram

IF Gain

IF Filter

LogAmpFilter

RF Input Attenuator

Input

Detector

LO VideoFilter

FrequencyReference

SweepGenerator

DisplayDisplay


PLL Phase Noise Sources

( ) θREF θR θPD+θLPF

kPD GLPFkVCO/s

t t

θVCO

( ) skGksG VCOLPFPD=

%R

REF

+ PD+ +

VC

OLPFoutput

S0+

LP in band noise HP out of band noiseNTFREF

%N+

θ kGNkG ⎞⎛Close loop transfer function

θN

Total output noise power spectral density

22⎤⎡

VCOLPFPD

VCOLPFPD

kGkNskGNk

NGG

+=⎟

⎠⎞

⎜⎝⎛

+ /1

( )22

220 /11

/1⎟⎠⎞

⎜⎝⎛

++⎟

⎠⎞

⎜⎝⎛

+⎥⎦

⎤⎢⎣

⎡ ++++=

NGS

NGG

kSSSS

RSfS VCO

PD

LPFPDNR

REF

HPFLPF ⎞⎛⎞⎛ G11


⎟⎠⎞

⎜⎝⎛

+−=⎟

⎠⎞

⎜⎝⎛

+ NGG

NNG /111

/11

In-band PLL Phase Noise

( ) 2220

2

220 Nk

SSSSR

SkGkNs

kGNkk

SSSSR

SfSPD

LPFPDNR

REF

sVCOLPFPD

VCOLPFPD

PD

LPFPDNR

REF⎥⎦

⎤⎢⎣

⎡ ++++→⎟⎟

⎠

⎞⎜⎜⎝

⎛+⎥

⎦

⎤⎢⎣

⎡ ++++=

→

PLL magnifies the noise from the reference, phase detector, LPF and the dividers by the amount of 20logN dB Smaller N leads to lower in-band noise.noise.

For integer-N Synthesizer: output frequency Fo=Fref*N, step size = Fref cannot simultaneously achieve fine step size and small N. poor in-band

i fnoise performance.

For fractional-N Synthesizer: output frequency Fo=Fref*(N+K/F), step size = Fref/F can achieve fine step size and small N simultaneously. better in-p yband noise performance.


Out-Of-Band PLL Phase Noise

( ) VCOVCO Skk

SfS →⎟⎟⎞

⎜⎜⎛

=2

01

The noise outside of the PLL bandwidth is determined by the VCO phase noise, namely,

( ) VCOsVCOLPFPD

VCO NskGkf

∞→⎟⎠

⎜⎝ +0 1

⎪⎬⎫⎪

⎨⎧

⎥⎤

⎢⎡

⎥⎤

⎢⎡

⎟⎞

⎜⎛

ΔffFkTfS c11l10)(

2

0

⎪⎭

⎪⎬

⎪⎩

⎪⎨

⎥⎥⎦⎢

⎢⎣ Δ

+⋅⎥⎥⎦⎢

⎢⎣

⎟⎟⎠

⎞⎜⎜⎝

⎛⋅Δ

+=Δf

fQf

fP

FkTfS c

LsVCO 1

21

2log10)( 0

Flicker 1/f noise is caused by trapping in the semiconductor material. Flicker noise corner fc is y pp gan empirical parameter depending on the device size and processing. For CMOS, fc is found to be 3~7 kHz typically and for bipolar transistors fc is about as 50 kHz. Notice that fc has impact only on close-in noise. QL is the loaded Q of the resonant circuit, ranging from 5~20 for on-chip resonator and 40~80 for off-chip tank. Ps is the average signal power at output of the oscillator active device and F is oscillator effective noise factoroscillator active device, and F is oscillator effective noise factor.


Simulated PLL Phase Noise Sources

3. Crystal/CP Intercept

2. CP/VCO InterceptCP noiseCP noiseCrystal noise

Crystal noise

Divider noise

Divider noise

1. ΣΔ/VCO InterceptPD noise

ΣΔno

iseΣΔ

noise

VCO noise

VCO noise


Simulated PLL Phase Noise With Loop Effect

Divider noise

Divider noise Crystal noiseCrystal noise Total noise

Total noiseCPCP

oiseoise

PD noisePD noiseeeP noise

P noise

ΣΔno

iseΣΔ

noise

VCO noi

VCO noi

LPF noise

LPF noise


Comparison of measured and simulated phase noise

Frequency Band

Simulated Phase Noise

Measured Phase Noise

Bc /

Hz)

-60

-70

-80

-90

3.2-3.3GHz 0.44°rms 0.50°rms

4.1-4.3GHz 0.50°rms 0.535°rms

Phas

e N

oise

(dB

-100

-110

-120

-130

Parameter Value

C1 3nF

0.1 1.0 10 100 1000 10000

P

-140

-150

-160

C2 600pF

R 600Ω

Frequency Offset (kHz)


References

• John W.M. Rogers, Calvin Plett, and Foster F. Dai, “Integrated Circuit Design for High-Speed Frequency Synthesis ” ARTECHCircuit Design for High Speed Frequency Synthesis, ARTECH HOUSE PUBLISHERS, INC., ISBN: 1-58053-982-3, February, 2006.

• Fa Foster Dai and Charles Stroud, “Chapter 15 Analog and Mixed-Signal Test Architectures,” in System-on-Chip Test Architectures: Nanometer Design for Testability, Morgan Kaufmann Publishers,Nanometer Design for Testability, Morgan Kaufmann Publishers, ISBN: 978-0-12-373973-5, November 2007.

• John Rogers, Foster Dai and Calvin Plett, “Chapter 15 Frequency Synthesis for Multi-band Wireless Networks,” in “Emerging Wireless Technologies -- From System to Transistors,” CRC Press, ISBN: g y978-0849379963, October 2007.

• RF Microelectronics by Behzad Razavi• John W.M. Rogers, Foster F. Dai, Mark S. Cavin, and Dave G. Rahn,

“A Fully Integrated Multi-Band SD Fractional-N Frequency y g q ySynthesizer for a MIMO WLAN Transceiver RFIC,” IEEE Journal of Solid-State Circuits, vol. 40, no. 3, pp. 678-689, March, 2005.


Date post:	10-Feb-2018
Category:	Documents
Upload:	buingoc
View:	221 times
Download:	2 times

Lecture 8 Frequency Synthesizer PLL - Auburn Universityagrawvd/COURSE/RFIC_July08... · RFIC Design...

Documents