Lecture Notes in Computer Science 9523 Commenced Publication in 1973 Founding and Former Series Editors: Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen Editorial Board David Hutchison Lancaster University, Lancaster, UK Takeo Kanade Carnegie Mellon University, Pittsburgh, PA, USA Josef Kittler University of Surrey, Guildford, UK Jon M. Kleinberg Cornell University, Ithaca, NY, USA Friedemann Mattern ETH Zurich, Zürich, Switzerland John C. Mitchell Stanford University, Stanford, CA, USA Moni Naor Weizmann Institute of Science, Rehovot, Israel C. Pandu Rangan Indian Institute of Technology, Madras, India Bernhard Steffen TU Dortmund University, Dortmund, Germany Demetri Terzopoulos University of California, Los Angeles, CA, USA Doug Tygar University of California, Berkeley, CA, USA Gerhard Weikum Max Planck Institute for Informatics, Saarbrücken, Germany
Transcript
Lecture Notes in Computer Science 9523
Commenced Publication in 1973Founding and Former Series Editors:Gerhard Goos, Juris Hartmanis, and Jan van Leeuwen
Editorial Board
David HutchisonLancaster University, Lancaster, UK
Takeo KanadeCarnegie Mellon University, Pittsburgh, PA, USA
Josef KittlerUniversity of Surrey, Guildford, UK
Jon M. KleinbergCornell University, Ithaca, NY, USA
Friedemann MatternETH Zurich, Zürich, Switzerland
John C. MitchellStanford University, Stanford, CA, USA
Moni NaorWeizmann Institute of Science, Rehovot, Israel
C. Pandu RanganIndian Institute of Technology, Madras, India
Bernhard SteffenTU Dortmund University, Dortmund, Germany
Demetri TerzopoulosUniversity of California, Los Angeles, CA, USA
Doug TygarUniversity of California, Berkeley, CA, USA
Gerhard WeikumMax Planck Institute for Informatics, Saarbrücken, Germany
More information about this series at http://www.springer.com/series/7407
Sascha Hunold • Alexandru CostanDomingo Giménez • Alexandru IosupLaura Ricci • María Engracia Gómez RequenaVittorio Scarano • Ana Lucia VarbanescuStephen L. Scott • Stefan LankesJosef Weidendorfer • Michael Alexander (Eds.)
Euro-Par 2015:Parallel ProcessingWorkshopsEuro-Par 2015 International WorkshopsVienna, Austria, August 24–25, 2015Revised Selected Papers
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EditorSascha HunoldVienna University of TechnologyViennaAustria
Workshop Editors see next page
ISSN 0302-9743 ISSN 1611-3349 (electronic)Lecture Notes in Computer ScienceISBN 978-3-319-27307-5 ISBN 978-3-319-27308-2 (eBook)DOI 10.1007/978-3-319-27308-2
Library of Congress Control Number: 2015955875
LNCS Sublibrary: SL1 – Theoretical Computer Science and General Issues
Euro-Par is an annual, international conference on European ground, covering allaspects of parallel and distributed processing, ranging from theory to practice, fromsmall to the largest parallel and distributed systems and infrastructures, from funda-mental computational problems to full-fledged applications, from architecture, com-piler, language and interface design and implementation to tools, supportinfrastructures, and application performance aspects. The Euro-Par conference itself iscomplemented by a workshop program, where workshops dedicated to more special-ized themes, to cross-cutting issues, and to upcoming trends and paradigms can beeasily and conveniently organized with little administrative overhead.
This year, 17 workshop proposals were submitted, and after a careful revisionprocess, which was led by the workshop co-chairs, 13 workshops were accepted. Oneworkshop had to be canceled later owing to a low number of submissions.
The workshops took place on the two days before the Euro-Par conference and theprogram included the following 12 workshops:
1. Big Data Management in Clouds (BIGDATACLOUD)2. Parallel and Distributed Computing Education for Undergraduate Students (EURO-
EDUPAR)3. Algorithms, Models, and Tools for Parallel Computing on Heterogeneous Plat-
forms (HETEROPAR)4. Large-Scale Distributed Virtual Environments (LSDVE)5. On-Chip Memory Hierarchies and Interconnects: Organization, Management and
Implementation (OMHI)6. Parallel and Distributed Agent-Based Simulations (PADABS)7. Performance Engineering for Large-Scale Graph Analytics (PELGA)8. Reproducibility in Parallel Computing (REPPAR)9. Resiliency in High-Performance Computing with Clouds, Grids, and Clusters
(RESILIENCE)10. Runtime and Operating Systems for the Many-Core Era (ROME)11. UnConventional High Performance Computing (UCHPC)12. Virtualization in High-Performance Cloud Computing (VHPC)
All workshops together received a total of 121 submissions from 34 differentcountries. Each workshop had an independent Program Committee, which was incharge of selecting the papers. The workshop papers received more than three reviews
per paper on average (403 reviews in total). Out of the 121 submissions, 67 papers wereselected to be presented at the workshops.
The success of the Euro-Par workshops depends on the work of many individualsand organizations. We therefore thank all workshop organizers and reviewers for thetime and effort that they invested. The Euro-Par vice-chair Luc Bougé providedguidance and support throughout the whole organizational process of the workshops.We would also like to express our sincere thanks to Springer for their help in pub-lishing the proceedings.
Lastly, we thank all participants, panelists, and keynote speakers of the Euro-Parworkshops for contributing to a productive meeting. It was a pleasure to organize andhost the Euro-Par workshops 2015 in Vienna.
October 2015 Sascha Hunold
VIII Preface
Organization
Euro-Par Steering Committee
Chair
Christian Lengauer University of Passau, Germany
Vice-Chair
Luc Bougé ENS Rennes, France
European Representatives
Marco Danelutto University of Pisa, ItalyEmmanuel Jeannot LaBRI-Inria, Bordeaux, FranceChristos Kaklamanis Computer Technology Institute, GreecePaul Kelly Imperial College, UKThomas Ludwig University of Hamburg, GermanyEmilio Luque Autonomous University of Barcelona, SpainTomàs Margalef Autonomous University of Barcelona, SpainWolfgang Nagel Dresden University of Technology, GermanyRizos Sakellariou University of Manchester, UKFernando Silva University of Porto, PortugalHenk Sips Delft University of Technology, The NetherlandsDomenico Talia University of Calabria, ItalyFelix Wolf Technische Universität Darmstadt, Germany
Honorary Members
Ron Perrott Oxford e-Research Centre, UKKarl Dieter Reinartz University of Erlangen-Nuremberg, Germany
Observers
Jesper Larsson Träff Vienna University of Technology, AustriaDenis Trystram Grenoble Institute of Technology, France
Euro-Par 2015 Organization
Chair
Jesper Larsson Träff Vienna University of Technology, Austria
Proceedings
Francesco Versaci Vienna University of Technology, Austria
Workshops
Sascha Hunold Vienna University of Technology, Austria
Local Organization
Alexandra Carpen-Amarie Vienna University of Technology, AustriaChristine Kamper Vienna University of Technology, AustriaMargret Steinbuch Vienna University of Technology, Austria
X Organization
Workshop Introductionand Organization
4th Workshop on Big Data Management in Clouds(BigDataCloud)
Workshop Description
The Workshop on Big Data Management in Clouds was created to provide a platformfor the dissemination of recent research efforts that explicitly aim at addressing thechallenges related to executing Big Data applications on the cloud. Initially designedfor powerful and expensive supercomputers, such applications have seen an increasingadoption on clouds, exploiting their elasticity and economical model. WhileMap/Reduce covers a large fraction of the development space, there are still manyapplications that are better served by other models and systems. In such a context, weneed to embrace new programming models, scheduling schemes, and hybridinfrastructures and scale out of single datacenters to geographically distributeddeployments in order to cope with these new challenges effectively.
Against this backdrop, the BigDataCloud workshop aims to provide a venue forresearchers to present and discuss results on all aspects of data management in clouds,new developments, and deployment efforts in running data-intensive computingworkloads. In particular, we are interested in how the use of cloud-based technologiescan meet the data-intensive scientific challenges of HPC applications that are not wellserved by the current supercomputers or grids, and are being ported to cloud platforms.The goal of the workshop is to support the assessment of the current state, introducefuture directions, and present architectures and services for future clouds supportingdata-intensive computing.
BigDataCloud 2015 followed the successful previous editions held in conjunctionwith EuroPar. Its goal is to aggregate the data management and clouds/grids/P2Pcommunities in order to complement the Big Data handling issues with a compre-hensive system/infrastructure perspective. This year’s edition was held on August 24and gathered around 30 enthusiastic researchers from academia and industry. Wereceived six papers, out of which three were selected for presentation. The Big Datatheme was strongly reflected in the keynote given this year by Prof. Luc Bougé fromÉcole Normale Supérieure Rennes. The talk focused on the challenges of computing indistributed, very-large clouds from the execution and programming modelsperspective.
We wish to thank all the authors, the keynote speaker, the Program Committeemembers and the workshop chairs of EuroPar 2015 for their contribution to the successof this edition of BigDataCloud.
Program Chairs
Alexandru Costan IRISA/INSA Rennes, FranceFrédéric Desprez Inria ENS Lyon, France
Program Committee
Gabriel Antoniu Inria, FranceLuc Bougé ENS Rennes, FranceShadi Ibrahim Inria, FranceOlivier Nano Microsoft Research ATLE, GermanyBogdan Nicolae IBM Research, IrelandMaria S. Pérez Universidad Politecnica de Madrid, SpainFlorin Pop University Politehnica of Bucharest, RomaniaAnna Queralt Barcelona Supercomputing Center, SpainLeonardo Querzoni University of Rome La Sapienza, ItalyBalaji Subramaniam Virginia Tech, USADomenico Talia University of Calabria, ItalyOsamu Tatebe University of Tsukuba, JapanRadu Tudoran Huawei European Research Center, Germany
XIV 4th Workshop, BigDataCloud
First European Workshop on Parallel and DistributedComputing Education for Undergraduate Students
(Euro-EDUPAR)
Workshop Description
Today, parallel and distributed computing (PDC) is omnipresent. It is encountered inall computational environments, from mobile devices, laptops, and desktops, to clustersof multicore nodes and supercomputers, usually comprising one or several coproces-sors of different types (GPU, MIC, FPGA). This explains why it is vital to educate newgenerations of scientists and engineers about a range of PDC-related topics as weprepare them to effectively use modern computational systems. In a word, PDC-relatedtopics must appear early and often in modern courses in computational science,computer science, and computer engineering.
In 2010, the IEEE Computer Society Technical Committee on Parallel Processing(TCPP) launched the Curriculum Initiative on Parallel and Distributed Computing, withCore Topics for Undergraduates. This led in 2011 to the EduPar workshop, which isdedicated to parallel and distributed computing education. Given the differences ineducational environments in different parts of the world, the Euro-EDUPAR workshopstarts with the aim of analyzing PDC education in a European context, i.e., within thestructure and organization of European education.
Thus, Euro-EDUPAR is dedicated to analyzing where and how to include topicsrelated to both PDC and HPC (high-performance computing) within the curricula ofprograms in computer science and engineering and computational science, whileemphasizing European undergraduate teaching. The workshop especially seeks papersthat report on experiences with incorporating PDC-related topics into undergraduatecore courses taken by the majority of students on a degree course. Methods,pedagogical approaches, tools, and techniques that have potential for adoption acrossthe European teaching community are of particular interest.
Topics of interest include: PDC teaching in the European space; pedagogical issuesin PDC, educational methods, and learning mechanisms; novel ways of teaching PDCtopics, including informal learning environments; curriculum design, models forincorporating PDC topics in core CS/CE curriculum; experience with incorporatingPDC topics into core CS/CE courses; experience with incorporating PDC topics in thecontext of other applications learning; pedagogical tools, programming environments,and languages for PDC; e-Learning, e-Laboratory, Massive Open Online Courses(MOOC), Small Private Online Courses (SPOC); PDC experiences at non-universitylevels, secondary school, postgraduate, industry, diffusion of PDC.
Program Chairs
Domingo Giménez University of Murcia, SpainSushil K. Prasad Georgia State University, USAArnold L. Rosenberg Northeastern University, Boston, USA
Program Committee
Marco Aldinucci University of Turin, ItalyPaolo Bientinesi RWTH Aachen University, GermanyFlorina Ciorba Technische Universität Dresden, GermanyPierre-François Dutot Université Pierre-Mendès Grenoble, FranceAnshul Gupta IBM Research, USAEmmanuel Jeannot Inria, FranceEleni Karatza Aristotle University of Thessaloniki, GreeceKishore Kothapalli International Institute of Information Technology,
Hyderabad, IndiaFriedhelm Meyer auf der
HeideUniversity of Paderborn, Germany
Milan D. Mihajlovic The University of Manchester, UKJulio Ortega University of Granada, SpainDana Petcu West University of Timisoara, RomaniaCynthia Phillips Sandia National Laboratories, USAMartin Quinson University of Lorraine/Inria Nancy, FranceNoemi Rodriguez PUC-Rio, BrazilJulio Sahuquillo Technical University of Valencia, SpainMitsuhisa Sato RIKEN Advanced Institute of Computational Science,
JapanChristian Scheideler Universität Paderborn, GermanyLeonel Sousa INESC-ID, IST, Universidade de Lisboa, PortugalPeter Strazdins Australian National University, AustraliaFrédéric Vivien Inria, FranceRoman Wyrzykowski Czestochowa University of Technology, PolandJulius Žilinskas Vilnius University, Lithuania
Additional Reviewers
Javier Cuenca University of Murcia, SpainDiego Fabregat-Traver RWTH Aachen University, GermanyDaniel Ruprecht University of Leeds, UK
XVI First European Workshop, Euro-EDUPAR
13th International Workshop on Algorithms, Models,and Tools for Parallel Computing
on Heterogeneous Platforms (HeteroPar)
Workshop Description
HeteroPar is a forum for researchers working on algorithms, programming languages,tools, and theoretical models aimed at efficiently solving problems on heterogeneousplatforms. Heterogeneity is emerging as one of the most profound and challengingcharacteristics of today’s parallel environments. From the macro level, where networksof distributed computers, composed by diverse node architectures, are interconnectedwith potentially heterogeneous networks, to the micro level, where deeper memoryhierarchies and various accelerator architectures are increasingly common, the impactof heterogeneity on all computing tasks is increasing rapidly. Traditional parallelalgorithms, programming environments and tools, designed for legacy homogeneousmultiprocessors, will at best achieve a small fraction of the efficiency and the potentialperformance that we should expect from parallel computing in tomorrow’s highlydiversified and mixed environments. New ideas, innovative algorithms, and specializedprogramming environments and tools are needed to efficiently use these new andmultifarious parallel architectures.
The 13th International Workshop on Algorithms, Models and Tools for ParallelComputing on Heterogeneous Platforms (HeteroPar 2015) was held in Vienna, Austria.For the seventh time, this workshop was organized in conjunction with the Euro-Par2015 annual series of international conferences. The format of the workshop includes akeynote, followed by technical presentations, and ending with a panel. The workshopwas well attended–there was 40 attendees.
This year, we received 26 articles, from 15 countries for review. After a thoroughpeer-reviewing process, we selected eight articles for presentation at the workshop. Thereview process focused on innovation and on proven applicability to heterogeneoussettings. As a consequence, the quality and the relevance of the selected articles arevery high. The acceptance ratio of 31 % is a result of the reviewers’ discussion and notof cut-off selection; none of the articles submitted to HeteroPar 2015 was rejectedbecause of the acceptance of other articles. The accepted articles represent aninteresting mix of topics, techniques, applications, and scales, exhibiting nicely thediversity and growth of the heterogeneous computing field.
The Panel on Next Generation Heterogeneous Computing was led by, inalphabetical order, Prof. Dr. Henri Bal (VU Amsterdam, The Netherlands), Dr.Guojing Cong (IBM T.J. Watson Research Center, NY, USA), Prof. Dr. Miriam Leeser(Northeastern University in Boston, MA, USA), Dr. Martin Schultz (LawrenceLivermore National Lab, CA, USA), and Christian Iwainsky (TU Darmstadt,Germany).
Last, but certainly not least, I would like to thank the HeteroPar SteeringCommittee and the HeteroPar 2015 Program Committee, who made the workshoppossible. I would also like to thank Euro-Par for hosting our community, and theEuro-Par workshops chair Dr. Sascha Hunold for his timely help.
Steering Committee
Domingo Giménez University of Murcia, SpainAlexey Kalinov Cadence Design Systems, RussiaAlexey Lastovetsky University College Dublin, IrelandYves Robert Ecole Normale Supérieure de Lyon, FranceLeonel Sousa INESC-ID/IST, TU Lisbon, PortugalDenis Trystram LIG, Grenoble, France
Program Chair
Alexandru Iosup Delft University of Technology, The Netherlands
Program Committee
Rosa M. Badia Barcelona Supercomputing Center, SpainJorge Barbosa Faculdade de Engenharia do Porto, PortugalOlivier Beaumont Inria Futurs Bordeaux, LABRI, FranceCristina Boeres Universidade Federal Fluminense, BrazilGeorge Bosilca ICL, UTK, USALouis-Claude Canon University of Franche-Comte, FranceAlexandre Denis Inria, FranceToshio Endo Tokyo Institute of Technology, JapanJianbin Fang NUDT, ChinaEdgar Gabriel University of Houston, USAShuichi Ichikawa Toyohashi University of Technology, JapanEmmanuel Jeannot Inria, FranceHelen Karatza Aristotle University of Thessaloniki, GreeceHatem Ltaief KAUST, Saudi ArabiaPierre Manneback University of Mons, BelgiumSatoshi Matsuoka Tokyo Institute of Technology, JapanRafael Mayo Universidad Jaume I, SpainWahid Nasri ESST de Tunis, TunisiaNacho Navarro Barcelona Supercomputing Center, SpainDana Petcu University of Timisoara, RomaniaAntonio J. Plaza University of Extremadura, SpainThomas Rauber University of Bayreuth, GermanyMatei Ripeanu University of British Columbia, CanadaVladimir Rychkov University College Dublin, IrelandMitsuhisa Sato University of Tsukuba, JapanErik Saule University of North Carolina at Charlotte, USA
XVIII 13th International Workshop, HeteroPar
Tom Scogland Lawrence Livermore National Laboratory, USAHenk Sips Delft University of Technology, The NetherlandsAna Lucia Varbanescu University of Amsterdam, The NetherlandsAntonio M. Vidal Universidad Politecnica de Valencia, SpainFrederic Vivien Inria, FranceJon Weissman University of Minnesota, USA
13th International Workshop, HeteroPar XIX
Third Workshop on Large-Scale Distributed VirtualEnvironments (LSDVE)
Workshop Description
The focus of the workshop has been the investigation of different aspects of distributedcooperative applications. Several novel applications have emerged in this area in thelast few years. These include distributed social networks, distributed social games,collaborative recommender systems, collaborative learning systems, large-scalecrowd-based applications, supported collaborative work (CSCW), and massivelymulti-player games.
The realization of these applications requires affording several challenges, such asthe definition of user interfaces, coordination protocols, and proper middleware andarchitectures supporting distributed cooperation. Collaborative applications maygreatly benefit from the support of different kinds of platforms, both cloud and peerto peer and also platforms recently proposed for the Internet of Things (IoT), such asfog computing. The integration of different platforms, for instance, mobile and cloudenvironments, is currently a challenge.
Some important challenges in the area of large-scale virtual environments arecollaborative protocols design, latency reduction/hiding techniques for guaranteeingreal-time constraints, large-scale processing of user information, privacy and securityissues, state consistency/persistence.
The workshop investigated open challenges in this area, related to the design ofnew applications and to the definition of proper environments and frameworks for theirdevelopment. LSDVE 2015 was a venue for researchers to present and discussimportant aspects of large-scale collaborative applications and of the platformssupporting them.
The workshop opened with the keynote “Distributed Virtual Environments: FromClient Server to Cloud and P2P Architectures: A Tutorial” given by Prof. Laura Ricci,University of Pisa, Italy.
The workshop organizers want to thank the authors of the papers for joining us inVienna, the Program Committee and all the referees for doing the hard work ofreviewing all the submissions, the conference organizers for proving a great support,and the researchers attending the workshop in Vienna.
Program Chairs
Laura Ricci University of Pisa, ItalyAlexandru Iosup TU Delft, Delft, The NetherlandsRadu Prodan University of Innsbruck, Austria
Program Committee
Michele Amoretti University of Parma, ItalyEmanuele Carlini ISTI CNR, Pisa, ItalyMassimo Coppola ISTI CNR, Pisa, ItalyPatrizio Dazzi ISTI CNR, Pisa, ItalyJuan J. Durillo University of Innsbruck, AustriaKalman Graffi University of Dusseldorf, GermanyBarbara Guidi University of Pisa, ItalyAlexandru Iosup TU Delft, The NetherlandsPedro Garcia Lopez University Rovira i Virgili, SpainPietro Michiardi EURECOM, FranceDana Petcu West University of Timisoara, RomaniaRadu Prodan University of Innsbruck, AustriaLaura Ricci University of Pisa, Pisa, ItalyAlexey Vinel Tampere University of Technology, Finland
4th International Workshop on On-Chip MemoryHierarchies and Interconnects (OMHI)
Workshop Description
Current chip multiprocessors (CMPs) include several levels of on-chip caches to avoidthe huge latencies of accessing the off-chip DRAM main memory modules. Thesecaches must be efficiently interconnected to avoid performance penalties. On-chipnetworks are used to interconnect the memory hierarchy inside the processorchip. Latencies can be significantly affected by the devised on-chip memory hierarchyand the interconnect design, whose impact on the overall latency strongly depends onthe core count. Consequently, this problem aggravates with the increasing core counts,which is the current commercial trend. By contrast, the main concern in GPUs is onmemory bandwidth instead of latencies. Current GPUs are designed to hide memorylatencies through fine-grained multithreading. The main goal of on-chip memories incurrent GPUs is to reduce off-chip memory traffic. In this context, the programmerplays a key role in improving cache access locality. Hence we can conclude that CPUsand GPUs require memory organizations with different characteristics. Thus, as currentheterogeneous CPU-GPU systems are proliferating in the market, the memory systemmust be designed to efficiently support both types of memory organizations:latency-oriented and bandwidth-oriented.
The on-chip memory hierarchy occupies two thirds of the processor area andconsumes a significant fraction of the overall system power. To deal with processorscalability issues, new technologies have emerged to implement the on-chip hierarchy.Regarding on-chip memory technologies, current SRAM technologies deployed inon-chip caches present important design challenges in terms of density and leakagecurrents. Instead, alternative technologies addressing leakage and density, such aseDRAM or MRAM, are being implemented and explored in large CMPs. Also thecurrent electronic technology used in on-chip networks has important performance andpower scalability limitations and designs using alternative technologies such asphotonics or wireless are being proposed.
To efficiently leverage any on-chip memory hierarchy design, efforts must befocused on the management of shared resources, especially in the context of multicoresystems where multiple threads contend while accessing these resources. Thismanagement involves, among others, thread allocation policies, cache managementstrategies, and NoC design. In this context, the synergy between the research onmemory organization and management, interconnection networks, as well as noveltechnologies becomes a key strategy for fostering further developments. With this aim,the International Workshop on On-chip Memory Hierarchy and Interconnects (OMHI)started in 2012 and continued with its fourth edition in 2015, which was held inVienna, Austria. This workshop is organized in conjunction with the Euro-Par annual
series of international conferences dedicated to the promotion and advancement of allaspects of parallel computing.
The goal of the OMHI workshop is to provide a forum for engineers and scientiststo address the aforementioned challenges, and to present new ideas for future on-chipmemory hierarchies and interconnects focusing on organization, management, andimplementation. The specific topics covered by the OMHI workshop have been kept upto date according to technology advances and industrial and academia interests.
The chairs of OMHI were proud to present Prof. Sandro Bartolini as keynotespeaker, who gave an interesting talk focusing on the key topics of the workshopentitled “Illuminating Processors: How Photonics Will Help Computing,” whichtogether with the paper session resulted in an interesting and very exciting one-dayprogram.
Finally, the chairs would like to thank the members of the Program Committee fortheir reviews, the Euro-Par organizers, Sandro Bartolini, and all of the attendees. Basedon the positive feedback from all of them, we plan to continue the OMHI workshop inconjunction with Euro-Par 2016.
Program Chairs
Julio Sahuquillo Universitat Politècnica de València, SpainMaría Engracia Gόmez Universitat Politècnica de València, SpainSalvador Petit Universitat Politècnica de València, Spain
Program Committee
Manuel Acacio Universidad de Murcia, SpainSandro Bartolini Università di Siena, ItalyJoão M.P. Cardoso University of Porto, PortugalMarcello Coppola STMicroelectronics, FranceGiorgos Dimitrakopoulos Democritus University of Thrace, GreecePierfrancesco Foglia Università di Pisa, ItalyHolger Fröning University of Heidelberg, GermanyCrispín Gómez Universitat Politècnica de València, SpainKees Goossens NXP Semiconductors and Delft University of
Technology, The NetherlandsDavid Kaeli Northeastern University, USASonia López Rochester Institute of Technology, USAIakovos Mavroidis Foundation for Research and Technology - Hellas
(FORTH), GreecePierre Michaud Inria, FranceTor Skei Simula Research Laboratory, NorwayRafael Ubal Northeastern University, USA
4th International Workshop, OMHI XXIII
Third Workshop on Parallel and Distributed Agent-BasedSimulations (PADABS)
Workshop Description
Agent-based simulation models are an increasingly popular tool for research andmanagement in many fields such as ecology, economics, sociology, etc. In some fields,such as social sciences, these models are seen as a key instrument to the generativeapproach, essential for understanding complex social phenomena. But also inpolicy-making, biology, military simulations, control of mobile robots and economics,the relevance and effectiveness of agent-based simulation models has been recentlyrecognized. The computer science community has responded to the need for platformsthat can help the development and testing of new models in each specific field byproviding tools, libraries, and frameworks that speed up and make massive simulations.The key objective of this workshop is to bring together researchers who are interestedin getting more performance from their simulations, by using synchronized, many-coresimulations (e.g., GPUs), strongly coupled, parallel simulations (e.g., MPI) and looselycoupled, distributed simulations (distributed heterogeneous setting).
Several frameworks have been recently developed and are active in this field. Theyrange from the GPU-manycore approach, to parallel, to distributed simulation environ-ments. In the first category, you can find FLAME GPU, which also allows non-GPUspecialists to harness the GPUs performance for real-time simulation and visualization.For tightly-coupled, large computing clusters and supercomputers a very popularframework is Repast for High-Performance Computing (REPAST-HPC), a C++-basedmodeling system. On the distributed side, recent work on Distributed Mason, allowsnon-specialists to use heterogeneous hardware and software in local area networks forenlarging the size and speeding up the simulation of complex agent-based models.
Therefore, our focus and positioning is on the applied side of parallel computing,with a particular emphasis on performance but also on the expressivity of theframeworks, since the field that is the target of our research is multidisciplinary anddoes not include only “hard-science” scientists.
Program Chairs
Vittorio Scarano (Chair) Università di Salerno, ItalyGennaro Cordasco Seconda Università di Napoli, ItalyUgo Erra Università della Basilicata, ItalyCarmine Spagnuolo
(Publicity Chair)Università di Salerno, Italy
Program Committee
Maria Chli Aston University, UKClaudio Cioffi-Revilla George Mason University, USABiagio Cosenza University of Innsbruck, AustriaNick Collier Argonne National Laboratory, USARosaria Conte CNR, ItalyAndrew Evans University of Leeds, UKBernardino Frola The MathWorks, Cambridge, UKJoanna Kolodziej Cracow University of Technology and AGH University
of Science and Technology, Cracow, PolandNicola Lettieri Università del Sannio and ISFOL, ItalySean Luke George Mason University, USAMichael North Argonne National Laboratory, USAMario Paolucci CNR, ItalyPaul Richmond The University of Sheffield, UKArnold Rosenberg Northeastern University, USAFlaminio Squazzoni Università di Brescia, ItalyMichela Taufer University of Delaware, USA
Additional Reviewers
Carmine Spagnuolo Università di Salerno, ItalyLuca Vicidomini Università di Salerno, Italy
Third Workshop, PADABS XXV
First Workshop on Performance Engineeringfor Large-Scale Graph Analytics (PELGA)
Workshop Description
The knowledge economy is based on data, of which graphs represent an increasingpart, in advanced marketing, in social networking, in life sciences, in health andbioinformatics services, in academic networks, in hiring of professionals, etc. As aconsequence, graph analytics is fast becoming a significant consumer of computingresources, due to the ever larger graphs of hundreds of millions up to hundreds ofbillions of edges, and to the increased complexity of analysis tasks. To enable existingalgorithms to fit modern architectures and scale with these new requirements, there is agrowing need for performance engineering.
PELGA is a venue that aims to address this need. Its goal is to bring togetherspecialists from both industry and academia to discuss the state of the art of graphprocessing systems, with a special focus on performance. Hosting PELGA withEuroPar allows the largest community of parallel and distributed systems in Europe andelsewhere to participate in the discussion and acknowledge the new researchopportunities that large-scale graph processing presents.
PELGA is a venue that welcomes contributions focusing on graph-centricperformance engineering tools and methods, workload characterization, new algo-rithms and new graph processing systems, and performance modeling. Lessconventional workshop topics such as surveys, performance studies, comparativeanalyses are also encouraged, given the young age of the large-scale graph processingcommunity. We strive to cover the specifics of three large classes of topics.
1. Systems invites contributions focusing on new graph processing systems focused onhigh-performance analytics, performance studies of existing systems to be used forgraph processing, and comparative and/or in-depth analysis of graph processingsystems.
2. Algorithms, Applications, and Architectures is the largest topic cluster, includingwork focusing on new high-performance graph processing algorithms, newperformance-aware applications for graph processing algorithms, platform-specificalgorithms and their performance optimization (e.g., GPUs, Xeon Phi, heteroge-neous platforms) for graph analytics, algorithms and/or architectures for large-scalegraph analytics, and partitioning methods for large-scale or otherwise challenginggraphs.
3. Characterization, Modeling, and Engineering is the core of the workshop. Weencourage novel contributions focusing on graph models for performance tuningand/or prediction of analytics workloads, performance models for prediction orranking of graph processing platforms, performance analysis and engineering of
existing graph processing algorithms, and tools and benchmarks for graph-centricperformance engineering.
In summary, large-scale graph processing is a high-impact field in full develop-ment, driven by both data owners and the analytics world. As we recognize the need toadapt traditional performance evaluation, analysis, and modeling to the needs of thisdynamic new topic, PELGA is a workshop with a strong community focus, aiming tobring the challenges of large-scale graph processing to the attention of the EuroParcommunity as an unconventional, yet very relevant topic for parallel and distributedcomputing.
Program Chairs
Ana Lucia Varbanescu University of Amsterdam, The NetherlandsAlexandru Iosup Delft University of Technology, The Netherlands
Program Committee
Arnau Prat-Perez UPC, SpainClaudio Martella VU University Amsterdam, The NetherlandsHannes Muhleisen CWI Amsterdam, The NetherlandsHassan Chafi Oracle Labs, USASungpack Hong Oracle Labs, USAJan Hidders Delft University of Technology, The NetherlandsJosep Lluis Larriba Pey UPC, SpainMatei Ripeanu The University of British Columbia, CanadaMihai Capota Intel Labs, USATed Willke Intel Labs, USA
First Workshop, PELGA XXVII
Second International Workshopon Reproducibility in Parallel Computing (REPPAR)
Workshop Description
Conducting sound and reproducible experiments in parallel computing is not easy, ashardware and software architectures of current parallel computers are most often verycomplex. This high complexity makes it difficult—and often impossible—for computerscientists to model such systems mathematically. For that reason, scientists rely onexperiments to study new parallel algorithms, different software solutions (e.g.,operating systems), or novel hardware architectures. The situation in parallelcomputing is made even more difficult than it would be otherwise, as parallel systemsare in a constant state of flux, e.g., the total core count is rapidly growing and manyprogramming paradigms for parallel machines have emerged and are actively beingused in a hybrid fashion, e.g., MPI, OpenMP, or PGAS.
For these reasons, the workshop is concerned with experimental practices inparallel computing research. We solicit research papers and experience reports on anumber of relevant topics, particularly: methods for analysis and visualization ofexperimental data, best-practice recommendations, results of attempts to replicatepreviously published experiments, and tools for experimental computational sciences.Some examples of the latter include workflow management systems, experimentaltestbeds, and systems for archiving and querying large data files.
Program Chairs
Sascha Hunold Vienna University of Technology, AustriaArnaud Legrand CNRS, LIG, Grenoble, FranceLucas Nussbaum Université de Lorraine, LORIA, FranceMark Stillwell Imperial College London, UK
Program Committee
Andrew Davison CNRS, UNIC, Gif-sur-Yvette, FranceGeorg Hager University of Erlangen-Nuremberg, GermanySascha Hunold Vienna University of Technology, AustriaArnaud Legrand CNRS, LIG, Grenoble, FranceLucas Nussbaum Université de Lorraine, LORIA, FranceOlivier Richard Université Joseph Fourier, LIG, Grenoble, FranceLucas M. Schnorr Universidade Federal do Rio Grande do Sul, Porto
Alegre, BrazilMark Stillwell Imperial College London, UKJesper Larsson Träff Vienna University of Technology, Austria
8th Workshop on Resiliency in High-PerformanceComputing in Clusters, Clouds, and Grids (Resilience)
Workshop Description
Clouds, grids, and clusters are three different computational paradigms with thepotential to support high-performance computing (HPC) and enterprise IT infrastruc-ture. Currently, they consist of hardware, management, and usage models particular todifferent computational regimes [e.g., high-performance cluster systems designed tosupport tightly coupled scientific simulation codes typically utilize high-speedinterconnects and commercial cloud systems designed to support software as a service(SAS) typically do not]. However, in order to support HPC, all must at least utilizelarge numbers of resources and hence effective HPC in any of these paradigms mustaddress the same issue of resiliency at a very large scale.
Recent trends in HPC systems have clearly indicated that future increases inperformance, in excess of those resulting from improvements in single-processorperformance, will be achieved through corresponding increases in system scale, i.e.,using a significantly larger component count. As the raw computational performanceof the world’s fastest HPC systems increases from today’s current multi-petascale tonext-generation exascale capability and beyond, their number of computational,networking, and storage components will grow from the ten to one hundred thousandcompute nodes of today’s systems to several hundreds of thousands of compute nodesin the foreseeable future. This substantial growth in system scale, and the resultingcomponent count, poses a challenge for HPC system and application software withrespect to reliability, availability, and serviceability (RAS).
The goal of this workshop is to bring together experts in the area of fault toleranceand resilience for HPC to present the latest achievements and to discuss the challengesahead. The program of the Resilience 2015 workshop included one keynote and fivehigh-quality papers. The keynote was given by Christian Engelmann from Oak RidgeNational Laboratory with the title “Toward A Fault Model and Resilience DesignPatterns for Extreme Scale Systems.”
Workshop Chairs
Stephen L. Scott Tennessee Tech University and Oak Ridge NationalLaboratory, USA
Chokchai(Box) Leangsuksun
Louisiana Tech University, USA
Workshop Program Chairs
Patrick G. Bridges University of New Mexico, USAChristian Engelmann Oak Ridge National Laboratory, USA
Workshop Program Committee
Ferrol Aderholdt Tennessee Tech University, USAVassil Alexandrov Barcelona Supercomputer Center, SpainDorian Arnold University of New Mexico, USAWesley Bland Intel Corporation, USAGreg Bronevetsky Lawrence Livermore National Laboratory, USAFranck Cappello Argonne National Laboratory and University of Illinois
at Urbana-Champaign, USAZizhong Chen University of California at Riverside, USAAndrew A. Chien University of Chicago and Argonne National
Laboratory, USANathan DeBardeleben Los Alamos National Laboratory, USAJames Elliott North Carolina State University, USAKurt Ferreira Sandia National Laboratory, USAMichael Heroux Sandia National Laboratories, USALarry Kaplan Cray Inc., USADieter Kranzlmueller Ludwig Maximilians University of Munich, GermanySriram Krishnamoorthy Pacific Northwest National Laboratory, USAIgnacio Laguna Lawrence Livermore National Laboratory, USAScott Levy University of New Mexico, USACelso Mendes University of Illinois at Urbana-Champaign, USAKathryn Mohror Lawrence Livermore National Laboratory, USAChristine Morin Inria Rennes, FranceNageswara Rao Oak Ridge National Laboratory, USAAlexander Reinefeld Zuse Institute Berlin, GermanyRolf Riesen Intel Corporation, USAMartin Schulz Lawrence Livermore National Laboratory, USAMarc Snir Argonne National Laboratory, USAKeita Teranishi Sandia National Laboratories, USA
XXX 8th Workshop, Resilience
Third Workshop on Runtime and Operating Systemsfor the Many-Core Era (ROME)
Workshop Description
Since the beginning of the multicore era, parallel processing has become prevalentacross the board. However, in order to continue a performance increase according toMoore’s law, the next step needs to be taken: away from common multicores towardinnovative many-core architectures. Such systems, equipped with a significantly higheramount of cores per chip than multicores, pose challenges in both hardware andsoftware design. On the hardware side, complex on-chip networks, scratchpads, hybridmemory cubes, non-volatile memory and stacked memory as well as deep cachehierarchies and novel cache-coherence strategies will enrich the current research areasin the future.
However, the ROME workshop (Runtime and Operating Systems for theMany-Core Era) focuses on the software side because without complying systemsoftware, runtime and operating system support, all these new hardware facilitiescannot be exploited. Hence, the new challenges in hardware/software co-design are tostep beyond traditional approaches and to create new programming models andoperating system designs in order to exploit the theoretically available performance offuture hardware as effectively and as power-aware as possible.
This focus of the ROME workshop stands in the tradition of a successful series ofevents originally hosted by the Many-Core Applications Research Community(MARC). Prior MARC symposia took place at ONERA Research Center in Toulouse,at the Hasso Plattner Institute in Potsdam, and at the RWTH Aachen University.Starting in 2013, the organizers continued this series by establishing ROME as oneof the co-located workshops of Euro-Par, the prime European conference for paralleland distributed computing.
While the first ROME workshop, which was hosted at Euro-Par 2013 in Aachen,was still a MARC-related follow-up event but for a broader audience, the secondROME workshop, held in conjunction with Euro-Par 2014 in Porto, already expandedits focus to research questions arising from the upcoming generation of heterogeneousand/or massive parallel systems stepping toward a many-core-dominated exascale era.
In 2015, this broader focus was essentially retained for the third ROME workshop,which was held in conjunction with Euro-Par 2015 in Vienna, but the relevance ofruntime and operating system aspects was stressed once again as being the primaryscope of the ROME workshop series. In this spirit, the organizers were very happy thatDr. Carsten Weinhold from the Operating Systems Group of TU Dresden, Germany,volunteered to give an invited keynote for this third ROME workshop with the title “AMicrokernel-Based Operating System for Exascale Computing.”
Program Chairs
Stefan Lankes RWTH Aachen University, GermanyCarsten Clauss ParTec Cluster Competence Center GmbH
Program Committee
Jens Breitbart TU München, GermanyAndré Brinkmann Johannes Gutenberg-Universität Mainz, GermanyCarsten Clauss ParTec Cluster Competence Center GmbHChristos Kartsaklis Oak Ridge National Laboratory, USAStefan Lankes RWTH Aachen University, GermanyTimothy Mattson Intel Labs, USAJörg Nolte BTU Cottbus, GermanyMichael Riepen IAV GmbH, GermanyBettina Schnor University of Potsdam, GermanyChristian Terboven RWTH Aachen University, GermanyTheo Ungerer Universität Augsburg, GermanyJosef Weidendorfer TU München, Germany
Additional Reviewers
Steffen Christgau University of Potsdam, GermanySonja Kolen RWTH Aachen University, GermanyStefan Petri University of Potsdam, GermanySimom Pickartz RWTH Aachen University, GermanyLukas Razik RWTH Aachen University, Germany
XXXII Third Workshop, ROME
8th Workshop on UnConventional High-PerformanceComputing 2015 (UCHPC)
Workshop Description
Recent issues regarding the power consumption of conventional HPC hardware hasresulted both in new interest in accelerator hardware and in usage of mass-markethardware originally not designed for HPC. The most prominent examples are GPUs butFPGAs, DSPs, and embedded designs are also possible candidates to providehigher-power efficiency, as they are used in energy-restricted environments, such assmartphones or tablets. The so-called dark silicon forecast, i.e., not all transistors maybe active at the same time, may lead to even more specialized hardware in futuremass-market products. Exploiting this hardware for HPC can be a worthwhilechallenge.
As the word “UnConventional” in the title suggests, the workshop focuses on usageof hardware or platforms for HPC, which are not (yet) conventionally used today, andmay not have been designed for HPC in the first place. Reasons for its use can be rawcomputing power, good performance per watt, or low cost in general. To address thisunconventional hardware, often new programming approaches and paradigms arerequired to make best use of it. Another focus of the workshop is on innovative,(yet) unconventional, new programming models and algorithms (e.g., Big Data)exploiting unconventional HPC hardware or software.
To this end, UCHPC tries to capture solutions for HPC that are unconventionaltoday but could become conventional and significant tomorrow, and thus provide aglimpse into the future of HPC.
This year was the eigth time the UCHPC workshop took place, and it was the sixthtime in a row it was co-located with Euro-Par (each year since 2010). Before that, itwas held in conjunction with the International Conference on Computational Scienceand Its Applications 2008 and with the ACM International Conference on ComputingFrontiers 2009. However, UCHPC is a perfect addition to the scientific fields ofEuro-Par, and this is confirmed by the continuous interest we see among Euro-Parattendees for this workshop.
While the general focus of the workshop is fixed, the topic is actually a movingtarget. GPUs were quite unconventional for HPC a few years ago, but today a notableportion of the machines in the Top500 list are making use of them. Currently, theexploitation of mobile processors for HPC – including on-chip GPU and DSPs – is ahot topic. A recent technological breakthrough is mass-market production of 3Dstacking technology, which allows us to put memory and logic nearer together. Thismay result in a revival of the processing-in-memory idea, which is quite unconven-tional from a programmer’s point of view and seems to be a good fit for UCHPC. Tothis end, we invited Zehra Sura from the IBM T.J. Watson Center to give a keynote
about IBM’s recent research on “The Active Memory Cube: A Processing-in-MemorySystem for High-Performance Computing.”
These proceedings include the final versions of the papers presented at UCHPC andaccepted for publication. They take the feedback from the reviewers and workshopaudience into account.
The workshop organizers/program chairs want to thank the authors of the papersfor joining us in Vienna, the Program Committee for doing the hard work of reviewingall submissions, the conference organizers for providing such a nice venue, and last butnot least the large number of attendees this year.
Program Chairs
Jens Breitbart Technische Universität München, GermanyJosef Weidendorfer Technische Universität München, Germany
Program Committee
Michael Bader Technische Universität München, GermanyDenis Barthou University of Bordeaux, FranceAlex Bartzas National Technical University of Athens, GreeceLars Bengtsson Chalmers University of Technology, SwedenJames Beyer Cray Inc., USAJens Breitbart Technische Universität München, GermanyGeorgios Dimitrakopoulos Democritus University of Thrace, GreeceKarl Fürlinger LMU München, GermanyFrank Hannig University of Erlangen-Nuremberg, GermanyAnders Hast Uppsala University, SwedenPaul Keir University of the West of Scotland, UKRainer Keller Hochschule für Technik Stuttgart, GermanyGaurav Khanna University of Massachusetts Dartmouth, USAHarald Köstler University of Erlangen-Nuremberg, GermanyStefan Lankes RWTH Aachen, GermanyDimitar Lukarski Paralution Labs, GermanyManfred Mücke Materials Center Leoben, AustriaYannis Papaefstathiou Technical University of Crete, GreeceBertil Schmidt University of Mainz, GermanyIoannis Sourdis Chalmers University of Technology, SwedenDylan Stark Sandia National Laboratories, USARobert Strzodka Universität Heidelberg, GermanyCarsten Trinitis Technische Universität München, GermanyJosef Weidendorfer Technische Universität München, GermanyJan-Philipp Weiss COMSOL, SwedenGerhard Wellein University of Erlangen-Nuremberg, GermanyRen Wu Baidu, ChinaPeter Zinterhof jun University of Salzburg, Austria
XXXIV 8th Workshop, UCHPC
10th Workshop on Virtualizationin High-Performance Cloud Computing (VHPC)
Workshop Description
Virtualization technologies constitute a key enabling factor for flexible resourcemanagement in modern data centers, cloud environments, and increasingly in HPC aswell. Providers need to dynamically manage complex infrastructures in a seamlessfashion for varying workloads and hosted applications, independently of the customersdeploying software or users submitting highly dynamic and heterogeneous workloads.Thanks to virtualization, we have the ability to manage vast computing and networkingresources dynamically and close to the marginal cost of providing the services, which isunprecedented in the history of scientific and commercial computing.
OS-level virtualization, such as provided by Docker, allows for multiple isolateduser-space environments within the same OS kernel. It promises to provide many of theadvantages of machine virtualization with high levels of responsiveness andperformance; coupled with lightweight OSs it forms a potent architecture with thepotential of becoming a mainstream environment for HPC workloads.
Machine virtualization, with its capability to enable consolidation of multipleunder-utilized servers with heterogeneous software and operating systems (OSs), andits capability to live-migrate a fully operating virtual machine (VM) with a very shortdowntime, enables novel and dynamic ways to manage physical servers.
I/O virtualization allows physical network adapters to take traffic from multipleVMs; network virtualization, with its capability to create logical network overlays thatare independent of the underlying physical topology and IP addressing, provides thefundamental ground on top of which evolved network services can be realized with anunprecedented level of dynamicity and flexibility. These technologies have to beinter-mixed and integrated in an intelligent way, to support workloads that areincreasingly demanding in terms of absolute performance, responsiveness, andinteractivity, and have to respect well-specified service-level agreements (SLAs), asneeded for industrial-grade provided services.
The Workshop on Virtualization in High-Performance Cloud Computing (VHPC)aims to bring together researchers and industrial practitioners facing the challengesposed by virtualization in order to foster discussion, collaboration, and mutualexchange of knowledge and experience, thereby enabling research to ultimatelyprovide novel solutions for virtualized computing systems of tomorrow.
Program Chairs
Michael Alexander TU Wien, AustriaAnastassios Nanos NTUA, GreeceBalazs Gerofi RIKEN, Japan
Program Committee
Stergios Anastasiadis University of Ioannina, GreeceCostas Bekas IBM, SwitzerlandJakob Blomer CERN, SwitzerlandRon Brightwell Sandia National Laboratories, USARoberto Canonico University of Napoli Federico II, ItalyJulian Chesterfield OnApp, UKPiero Castoldi Sant’Anna School of Advanced Studies, ItalyPatrick Dreher MIT, USAWilliam Gardner University of Guelph, CanadaKyle Hale Northwestern University, USAMarcus Hardt Karlsruhe Institute of Technology, GermanyIftekhar Hussain Infinera, USAKrishna Kant Temple University, USAEiji Kawai National Institute of Information and Communications
Technology, JapanRomeo Kinzler IBM, SwitzerlandKornilios Kourtis ETH, SwitzerlandNectarios Koziris National Technical University of Athens, GreeceMassimo Lamanna CERN, SwitzerlandChe-Rung Roger Lee National Tsing Hua University, TaiwanWilliam Magato University of Cincinnati, USAHelge Meinhard CERN, SwitzerlandJean-Marc Menaud Ecole des Mines de Nantes, FranceChristine Morin Inria, FranceAmer Qouneh University of Florida, USASeetharami Seelam IBM T.J. Watson Research Center, USAJosh Simons VMWare, USABorja Sotomayor University of Chicago, USAKurt Tutschku Blekinge Institute of Technology, SwedenYasuhiro Watashiba Osaka University, JapanChao-Tung Yang Tunghai University, Taiwan
Teaching Heart Modeling and Simulation on Parallel Computing Systems . . . 102Andrey Sozykin, Mikhail Chernoskutov, Anton Koshelev,Vladimir Zverev, Konstantin Ushenin, and Olga Solovyova
Integration of ICT in Concurrent and Parallel Programming Lectures. . . . . . . 114Antonio J. Tomeu-Hardasmal, Alberto G. Salguero, and Manuel I. Capel
LSDVE - Large Scale Distributed Virtual Environments
Community Discovery for Interest Management in DVEs: A Case Study . . . . 273Emanuele Carlini, Patrizio Dazzi, Matteo Mordacchini,Alessandro Lulli, and Laura Ricci
Continuation Complexity: A Callback Hell for Distributed Systems. . . . . . . . 286Edgar Zamora-Gómez, Pedro García-López, and Rubén Mondéjar
Offloading Service Provisioning on Mobile Devices in Mobile CloudComputing Environments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299
Marco Conti, Davide Mascitti, and Andrea Passarella
ROME - Runtime and Operating Systems for the Many-Core Era
Energy Characterization and Optimization of Parallel Prefix-Sums Kernels . . . 685Angelos Papatriantafyllou
An OS-Oriented Performance Monitoring Tool for Multicore Systems . . . . . . 697Juan Carlos Saez, Jorge Casas, Abel Serrano,Roberto Rodríguez-Rodríguez, Fernando Castro, Daniel Chaver,and Manuel Prieto-Matias
