Reversible Machine Code

and Its Abstract Processor Architecture

Holger Bock Axelsen, Robert Gluck, and Tetsuo Yokoyama

DIKU, Dept. of Computer Science, University of CopenhagenDK-2100 Copenhagen, Denmark

{funkstar,glueck,yokoyama}@diku.dk

Abstract. A reversible abstract machine architecture and its reversiblemachine code are presented and formalized. For machine code to be re-versible, both the underlying control logic and each instruction must bereversible. A general class of machine instruction sets was proven to bereversible, building on our concept of reversible updates. The presenta-tion is abstract and can serve as a guideline for a family of reversibleprocessor designs. By example, we illustrate programming principles forthe abstract machine architecture formalized in this paper.

1 Introduction

This paper presents the principles behind a reversible processor architecture. Weare interested in the von Neumann architecture, a classic computer design forsequential computation with a single random access memory. One of the firstreversible programmable processors built, Pendulum, is of this type [16,17,7].We shall define an abstract machine and prove that all instruction sets for thismachine that satisfy certain formal conditions, identified and presented in thispaper, are reversible; i.e., their semantics are forward and backward determin-istic. A unique feature of the reversible abstract machine is a control logic thatallows us to change the direction of execution by flipping the direction bit. It isnoteworthy that any program written in reversible machine code is guaranteedto be reversible; no programming error can break the reversibility.

The purpose of this paper is to provide a clear specification of the interplaybetween the physical and software levels. Our goal is for this formalization to pro-vide a better understanding of the essence of reversible processor architectures.From here, hardware designers may extend the model and work downward to-ward a physical realization (e.g., at the circuit level) and software designers maywork upward through the various abstraction layers (e.g., assembler, high-levellanguages, compilers). Understanding this interface is important, as a challengeof reversible computing is that the entire computing system must be reversible,from the physical bottom to the abstract top.

We believe that reversible computation models have properties that arenoteworthy in their own right and have interesting implications in other areas.For example, reversible computing holds the promise of reducing power

V. Diekert, M. Volkov, and A. Voronkov (Eds.): CSR 2007, LNCS 4649, pp. 56–69, 2007.c© Springer-Verlag Berlin Heidelberg 2007

Reversible Machine Code and Its Abstract Processor Architecture 57

��

dirbrpc

registers

memory

control logic

processor

data +reversibleinstructions

Fig. 1. Reversible abstract machine

consumption [13,2], and unconventional physical computation models, such asquantum computing, require that all computations are organized reversibly [6].

After presenting the architecture (Sect. 2), we describe the instruction set andstate its formal properties (Sect. 3). We explain the principles of programmingthe processor (Sect. 4), and conclude with related work (Sect. 5) and future work(Sect. 6). An appendix (App. A) containing proof sketches is also included.

2 Reversible Abstract Machine

This section presents the principles behind an abstract reversible processor archi-tecture. The design of the control logic is based on work by Vieri [16], Frank [7],Hall [12], and Cezzar [3]. Our contribution is a clear design and a formalizationof a reversible abstract machine for which we will prove that any instruction setthat satisfies certain conditions is reversible.

We are interested in a reversible version of the von Neumann architecture,a classic computer design with a processing unit (with registers) and randomaccess memory, instead of more theoretical models, such as Turing machines. Astandard abstract machine performs one-directional execution of machine code,while a reversible abstract machine allows bidirectional (forward and backward)execution of reversible machine code.

The challenge of reversibility for an abstract machine is two-fold. First, theinstruction execution must be reversible. This places restrictions on the instruc-tions possible in such a reversible architecture. Specifically, they must be injectivewhen considered as functions on machine states. Second, the control logic mustbe reversible. With control logic, we refer to the part of the processing unit con-trolling the program counter, including any interaction from the instructions. Toensure reversibility, this must also be an injective function on machine states.

Control Logic. The most difficult of these challenges is good design for control.At any point of program execution, the computation direction of a reversiblemachine can be switched (forward, backward). In a standard machine model, we

58 H.B. Axelsen, R. Gluck, and T. Yokoyama

constantly face the orthogonality problem. In general, we cannot know whetherwe have arrived at the current state by a jump or by sequential execution. Thus,we cannot reverse program execution and return to exactly the state that led tothe current state. A classic solution to this problem is the generation of a trace[13,2,3]. For practical purposes, however, this is unsatisfactory, as the trace growsproportionally to the length of the computation.

A good design for a reversible processor has to take a trace-free approach. Thiscan be accomplished in an architecture that has three special-purpose registersinvolved in the control logic (Fig. 1):

– A program counter (pc) for pointing to the current instruction.– A branch register (br) for jumps.– A direction bit (dir ) for specifying execution direction.

Between instruction executions, we update the control state by the followingtwo rules: (1) If the branch register is zero, add the direction bit to the programcounter. The direction bit has the value 1 or −1, and thus the program counter iseither incremented or decremented. This achieves sequential forward or backwardexecution of a program. (2) If the branch register is non-zero, add that (timesthe direction bit) to the program counter. A non-zero branch register indicatesthat a jump is to be performed. Instructions that require jumps will thus modifythe branch register and not the program counter directly. The effect of thisis to make the control logic reversible by solving the orthogonality problem:the branch register is preserved after modifying the program counter. This issufficient to determine where a jump came from. We will come back to thisimportant point after formalizing the state model and the execution semantics.

State Model. We model the set of machine states, Σ = M×R× C, as follows.A machine state σ ∈ Σ is a triple σ = (M, R, C) such that

Memory: M � M : Z32 → Z32

Registers: R � R : RegNames → Z32

Control: C � C : Z32 × Z32 × {1,−1}where Z32 is the set of 32-bit integers (or any set of n-bit integers) and RegNamesis the set of register names reg0 to reg31 (written $0 to $31 in machine code). Ina state, M and R describe the contents of the memory and the registers (eachis a function from addresses or register names to 32-bit integers), respectively,and tuple C = (pc, br , dir ) encapsulates the control registers. We do not modelinput/output facilities. It is assumed that program and data are entered intomemory before the machine starts and that the results are read from mem-ory after the machine stops (if it stops). Before loading program and data, allregisters and the entire memory are zero-cleared.

Instructions. The design of the abstract machine is closely tied to the design ofits reversible instruction set. The instructions fall into the two general classes ofdata modification and control flow instructions. As an example of a reversibledata modification instruction, consider the addition instruction

ADD $3 $4 .

Reversible Machine Code and Its Abstract Processor Architecture 59

Reversible execution step:

σ →ie σ′′ σ′′ →pc σ′

σ →1 σ′

Instruction execution:

σ = (M, R, (pc, br , dir)) I(M(pc), dir) = i 〈σ, i〉 →inst σ′

σ →ie σ′

Control logic:

br = 0

(M, R, (pc, br , dir)) →pc (M, R, (pc +32 dir , br , dir))

br �= 0

(M, R, (pc, br , dir)) →pc (M, R, (pc +32 br · dir , br , dir))

Fig. 2. Semantics of a reversible execution step

The effect of executing this instruction is to add to the value in register $3 thevalue in register $4. This instruction has an inverse interpretation: subtract thevalue of $4 from $3. A reversible architecture must provide two interpretationsof the same instruction depending on the direction bit: the standard semanticsand the inverse semantics. A standard instruction usually has the effect of over-writing the destination register irreversibly: the original value of the registercannot be recovered from the resulting state. Such irreversible instructions arenot allowed in a reversible architecture.

As outlined above, control flow instructions interact with the control state innon-trivial ways. The unconditional jump instruction

BRA 15

has the effect of adding 15 · dir to the branch register br . It is important thatbranch instructions use relative offsets for jumps, and not absolute addresses.If br �= 0, the control logic adds br · dir to the program counter pc, instead ofirreversibly overwriting the value of pc with an absolute address to perform thejump. We illustrate programming principles for the abstract machine in Sect. 4.

3 Reversible Instruction Set

The small-step operational semantics shown in Fig. 2 describes the workings ofthe machine code after program and data have been entered into memory. Wetreat each instruction as atomic, regardless of the actual processor design. Eachstep updates the machine state σ = (M, R, C). Below, we will explain the rulesand state the main theorems. As an example of a reversible instruction set, weuse the Pendulum Instruction Set Architecture, PISA [17,7]. The meanings ofthe instructions are defined by structural operational semantics, cf. [18].

60 H.B. Axelsen, R. Gluck, and T. Yokoyama

Reversible Execution Step. An execution step is described by a relation→1⊆ Σ × Σ. The single judgment form shows explicitly how an execution stepconsists of two parts: (i) instruction execution (→ie) and (ii) control logic (→pc).This separation is important when we consider the reversibility properties later,as the details are more subtle than one would initially assume.

Control Semantics. The relation →pc ⊆ Σ × Σ formalizes the control logic asdescribed in Sect. 2. The program counter pc is updated, while all other partsof the state are unchanged. The choice between the two rules depends on thecontents of branch register, br . Operation a +32 b is defined as (a + b) mod 232.

Instruction Execution Semantics. The relation →ie ⊆ Σ × Σ is a single judg-ment form that defines instruction execution. We will need the direction bit diras well as the current instruction M(pc). The instruction interpretation functionI has type (Z32 × {1,−1}) ⇀ Inst , where Inst is a fitting (abstract) descrip-tion of the instruction set. If the bit pattern does not define a legal instruction,its interpretation is undefined. An abstract instruction i ∈ Inst will consist ofan instruction name and up to three arguments, which can be either registernames or immediate values (i.e., integer constants contained in the instruction).Depending on dir , the current instruction M(pc) is mapped into an abstractinstruction i implementing its standard or its inverse semantics. This mappingis local program inversion performed on-the-fly at execution time [10]. It is im-portant that the inversion of an instruction depends only on the local context ofthe instruction (‘peephole’) and, unlike other program inversion methods [11,14],does not require global analysis or transformation of the program. This is keyto efficient reversible execution.

Local program inversion is the only feature of I in which we are interested—the actual bit patterns of the instructions do not concern us. Thus, we onlyassume that I(b, d) = i ⇔ I(b,−d) = inv(i). The inverse instruction inv(i) ofan instruction i is specified by its effect on the state such that ∀σin , σout ∈ Σ:

〈σin , i〉 →inst σout ⇐⇒ 〈flip(σout ), inv(i)〉 →inst flip(σin )

where flip((M, R, (pc, br , dir))) = (M, R, (pc, br ,−dir)) flips the direction bit.Suppose bit pattern b represents instruction ADD $2 $3, then I(b, 1) = ADD reg2

reg3 and I(b,−1) = SUB reg2 reg3. We use the self-inverse function inv definedby the following table. Unless indicated in this table, we have inv(i) = i. In-structions RL, RLV , RR, RRV rotate the bit pattern of a register regsd by aspecified number of places to the left or right.

i inv (i)ADD regsd regt SUB regsd reg t

ADDI regsd imm ADDI regsd −immRL regsd amt RR regsd amtRLV regsd regt RRV regsd reg t

Reversible Machine Code and Its Abstract Processor Architecture 61

And-xor:

σ = (M, R,C) regd �= regs regd �= reg t

〈σ,ANDX regd regs regt〉 →inst (M, R[regd �→ R(regd) ⊕ (R(regs) ∧ R(regt))], C)

Branch-if-equal:

σ = (M, R, (pc, br , dir)) R(rega) = R(regb)

〈σ,BEQ rega regb off 〉 →inst (M, R, (pc, br +32 off · dir , dir))

σ = (M, R, C) R(rega) �= R(regb)

〈σ, BEQ rega regb off 〉 →inst σ

Unconditional-branch:

〈(M, R, (pc, br , dir)),BRA off 〉 →inst (M, R, (pc, br +32 off · dir , dir))

Reverse-unconditional-branch:

〈(M, R, (pc, br , dir)),RBRA off 〉 →inst (M, R, (pc,−(br +32 off · dir),−dir))

Swap-branch-register:

〈(M,R, (pc, br , dir)),SWAPBR regb〉 →inst (M, R[regb �→ br ], (pc, R(regb), dir))

Memory-register-exchange:

σ = (M, R, (pc, br , dir)) pc �= R(rega)

〈σ,EXCH regd rega〉 →inst (M [R(rega) �→ R(regd)], R[regd �→ M(R(rega))], C)

Fig. 3. Excerpt of the instruction semantics of PISA (→inst)

Instruction Semantics. The relation →inst⊆ (Σ × Inst) × Σ is a judgmentform for updating the state by executing an abstract instruction. Except for theprogram counter, all parts of a state may be reversibly updated by →inst . Aswill be explained below, the relation →inst may be extended with instructionsthe execution semantics of which are reversible updates (with the restrictionthat pc and M(pc) must not be changed). The concept of a reversible update isintroduced below. An excerpt of the semantics for PISA is shown in Fig. 3. Weshall now describe the semantics of the selected instructions.

Data Modification. And-xor (ANDX ) updates the register regd with the resultof R(regs)∧R(reg t). Memory M and control C are unchanged. The update a⊕bis defined as bitwise exclusive-or on the binary representation of values a and b.Similarly, ∧ is bitwise and. Conditions regd �= regs and regd �= regt ensure thatregd is not an operand of ∧, which would be generally irreversible.

Branch Instructions. Branch-if-equal (BEQ) depends on the contents of registersrega and regb : if they are equal, off ·dir is added to branch register br ; otherwise,state σ is unchanged. Unconditional-branch (BRA) is similar to BEQ except that

62 H.B. Axelsen, R. Gluck, and T. Yokoyama

�� �x x f(y)

f

�

�� �y y

g

forward

�� �x x f(y)

f

�

���y y

g−1

backward

Fig. 4. Logically reversible update

br is unconditionally updated. Reverse-unconditional-branch (RBRA) flips thesign of the direction bit and the sign of the branch register after adding off · dirto it.1 Swap-branch-register (SWAPBR) exchanges the contents of register regb

and branch register br . The branch instructions modify the branch register br ,but never the program counter pc, which is only updated by the control logic.This is the way in which instruction execution and control logic cooperate.

Memory Access. Memory access can be performed reversibly by allowing onlyan exchange (EXCH ) between a register regd and a memory cell pointed to byrega (regardless of whether the memory cell holds an instruction or data). Thiscombines the conventional irreversible load and store instructions that overwritevalues into a single reversible instruction.

Reversible Updates. The conditions of an instruction reversibly updating val-ues are as follows. We say that a partial function, written as an infix binaryoperator � : (A×B) ⇀ C, is injective in its first argument, if ∀a, a′ ∈ A, ∀b ∈ B:if a � b and a′ � b are defined then

a � b = a′ � b ⇒ a = a′ .

For any operator � injective in its first argument there exists an operator � :(C × B) ⇀ A such that ∀a ∈ A, ∀b ∈ B:

((a � b) � b) = a .

For example, n + c = m + c implies n = m and we have (n + c) − c = n for anyinteger c. On the other hand, n · 0 = m · 0 does not imply n = m, and thus theoperator · is not injective in its first argument (in fact, it is not injective in anyargument). Bitwise exclusive-or, ⊕, has the useful property that ((a⊕b)⊕b) = a.

1 The operational meaning of RBRA given in [7] is incorrect in that it either breaksthe reversibility of the control logic, or does not work as intended in uncalls ofsubroutines. The semantics shown in Fig. 3 rectifies these problems.

Reversible Machine Code and Its Abstract Processor Architecture 63

Every injective operator is also injective in its first argument, but the converseneed not hold. Note that (a � b) � b = a does not imply (c � b) � b = c, so �and � are not necessarily exchangeable.2

Given a partial function f : D ⇀ B and operator � : (A × B) ⇀ C injectivein its first argument, we call a partial function g : (A×D) ⇀ (A×D) such that

g(x, y) = (x � f(y), y) ,

a reversible update wrt its first argument. There always exists a left inverse

g−1(x, y) = (x � f(y), y) .

A reversible update g is necessarily injective. It is bijective if A × D is finite,and g is total. The second argument of g and g−1 is returned unchanged. Notethat f does not need to be injective and that parameters x and y may be tuples(x1, . . . , xn) and (y1, . . . , ym), n, m ≥ 0. Clearly, the above can be stated for anyargument, and not only for the first. Reversible updates are illustrated in Fig. 4.It is useful to know that a reversible update with ⊕ is self-inverse for any f :

g(x, y) = g−1(x, y) = (x ⊕ f(y), y)

Reversible updates are particularly well suited to model changes of a compu-tation state where one part of the state, x, is updated using another part of thestate, y, that is not changed. As an example, consider the instruction ANDX theeffect of which is described by the reversible update

gANDX(x, (y1, y2)) = (x ⊕ (y1 ∧ y2), (y1, y2)) .

A particular instruction, say ANDX $2 $5 $7, can thus be viewed as a reversibleupdate of register $2 by gANDX($2, ($5, $7)). It is self-inverse: gANDX = g−1

ANDX.It is essential for the reversibility of the entire machine architecture that all

modifications of the machine state, be it by instructions or the control logic, arereversible updates regardless of whether they change memory M , registers R, orcontrol C. For example, BEQ is a reversible update of branch register br andrelation →pc is a reversible update of program counter pc. This is a requirementfor any machine architecture to be truly reversible.

The concept of reversible updates provides a generic instruction format for areversible instruction set architecture (ISA). Reversible updates are particularlywell suited for implementation in reversible hardware or reversible programminglanguages (e.g., a self-interpreter for a reversible language [19]). As f is generallyirreversible, a realization in reversible hardware usually requires the addition ofgarbage bits to the output and constant presets to the input. For reversible imple-mentation, there is a direct parallel to the Bennett trick [2] in which a circuit f ′

computing f(y) with garbage bits and constant presets can be inverted to yieldy again and no garbage bits. Fig. 5 shows the general implementation strategy2 For example, with integer multiplication * and integer division / defined on Z\{0},

we have (a * b) / b = a, but (c / b) * b �= c if b does not divide c.

64 H.B. Axelsen, R. Gluck, and T. Yokoyama

�� �x x f(y)

f ′�y f ′−1 � y��

��

f(y)

garbage

⊕� �0 f(y)

“copy”

f ′�y f ′−1 � y

�

��

f(y) f(y)

garbage

Fig. 5. Reversible implementation of reversible update

for reversible updates (constant presets omitted). Also shown is the case of acopy operator and x = 0, when the strategy defaults to being the Bennett trick.We assume that copy(x, z) = (x � z, z) can be implemented without garbagebits. This assumption is not unreasonable as copy is injective, and in general weexpect injective functions to be implementable without garbage generation. Inthe case of � = ⊕, copy is implementable by a Feynman gate [6].

Formal Properties. Now, we present the main theorems regarding the abstractmachine and its instruction set. The first theorem states that the semanticsof an execution step (Fig. 2) is forward and backward deterministic if everyinstruction in the machine’s instruction set Inst satisfy certain conditions. Thesecond theorem states that an execution step can be reversed in a particularsimple way. The interested reader can find proof sketches in App. A.

Theorem 1 (Forward and Backward Determinism). Assume that the se-mantics of every instruction i ∈ Inst is a reversible update with the restrictionthat pc and M(pc) must be preserved over →inst . Then, the semantics of anexecution step, →1, is forward and backward deterministic:

1. Forward determinism: ∀σ, σ′, σ′′ ∈ Σ . σ →1 σ′ ∧ σ →1 σ′′ ⇒ σ′ = σ′′

2. Backward determinism: ∀σ, σ′, σ′′ ∈ Σ . σ′ →1 σ ∧ σ′′ →1 σ ⇒ σ′ = σ′′.

This corresponds to saying that →1 is an injective function. Similar results applyto →pc and →ie . We define the function rev : Σ → Σ by rev = (→pc) ◦ flip toreverse the execution direction and update the program counter.

Theorem 2 (Local Invertibility). Assume Thm. 1 holds for instruction setInst, and that ∀i ∈ Inst . inv (i) ∈ Inst. Individual execution steps are reversible:

∀σ, σ′ ∈ Σ . σ →1 σ′ ⇒ rev(σ′) →1 rev(σ).

An instruction set for which these two theorems hold is reversible, specificallyreversible on the abstract machine of Sect. 2.

Theorem 3. PISA, as presented here and in [7, App.B], without the I/O in-structions, is a reversible instruction set.

Reversible Machine Code and Its Abstract Processor Architecture 65

Thm. 1 states what is usually meant by reversibility. The restrictions on theinstruction set illustrate a central point of this paper: instruction execution andcontrol logic should be kept separate. Even if an instruction is a reversible updateof the program counter, recovering a unique previous program counter may nolonger be possible. If an instruction modifies either pc or M(pc), we can no longeruniquely identify which instruction was executed from the resulting state. Thismeans backwards non-determinism and irreversibility.

Thm. 1 and 2 guarantee some surprising properties for programs written inreversible machine code. No matter what the program does, regardless of theprogrammer’s intent, execution of the program is guaranteed to be reversible.Furthermore, if the state space is finite, programs either terminate or eventuallyreturn to the precise starting state, looping forever.

4 Programming the Reversible Processor

Rather than giving a general programming methodology, we explain the mainpoints by examining an example program written in PISA (Fig. 6). The pro-gram shows some key aspects of reversible programming. The subroutine Fallimplements a simple discrete physical simulation of an object that falls througha vacuum. The object has two associated variables, h and v, giving its heightin meters and downward velocity in meters per second, respectively. The twovariables are calculated for each second (t = 1, 2, ...) of free fall according to thefollowing equations where g is the gravitational acceleration at sea level (approx.10 m/s2). Initially, v0 = 0 and h0 is the height from which the object is dropped.

vt = vt−1 + g

ht = ht−1 − vt +g

2The simulation is coded as a subroutine, callable from anywhere in the program.For simplicity, the subroutine updates two registers (v, h) instead of recordingthe values of each iteration in an array. We use symbolic names for registers(v, h,...) instead of ($1, $2,...). We will now explain the implementation of thesubroutine (labels 27-36) and then subroutine call and uncall (labels 10-12, 18-21). The subroutine simulates a free fall lasting tend seconds. The program isloaded into memory at the locations indicated by the labels in Fig. 6.

The paired branch approach is used for reversible jumps [12,7]. Jumping fromone branch instruction to another that points back at the calling branch clearsthe branch register and resumes normal sequential execution.

A reversible unconditional jump between labels 27 and 36 is implemented bythe paired branch instructions BRA 9 and BRA -9. To illustrate the reversibilityof this control-flow structure, let control C0 = (36, 0, 1) in a state (M, R, C0). Theexecution of BRA -9 at label 36 with →1 leaves M and R unchanged, but changesC0 to C1 = (27,−9, 1), which is a jump from label 36 to 27. Next, the execution ofBRA 9 at label 27 changes C1 to C2 = (28, 0, 1) and normal sequential executionis resumed. Now, reverse the execution direction: rev((M, R, C2)) = (M, R, C3)

66 H.B. Axelsen, R. Gluck, and T. Yokoyama

Call Fall: Subroutine Fall:

10: ADDI h 1000 27: BRA 9

11: ADDI tend 5 28: SWAPBR rtn ; br <=> rtn

12: BRA 16 ; call 29: NEG rtn ; rtn=-rtn

30: BGTZ t 5 ; t > 0?

Uncall Fall: 31: ADDI v 10 ; v += 10

18: ADDI v 40 32: ADDI h 5 ; h += 5

19: ADDI t 4 33: SUB h v ; h -= v

20: ADDI tend 4 34: ADDI t 1 ; t += 1

21: RBRA 7 ; uncall 35: BNE t tend -5 ; t �= tend?

36: BRA -9

Fig. 6. Example program: free-falling object

where C3 = (27, 0,−1). Executing BRA 9 gives C4 = (36,−9,−1), which is thereverse jump from label 27 to 36, and then BRA -9 gives C5 = (35, 0,−1), andwe return to the initial state: rev((M, R, C5)) = (M, R, C0). This shows howpaired branch instructions implement reversible unconditional jumps.

A reversible loop structure implements the main part of the simulation. Con-ceptually, this control-flow structure has two conditionals to maintain [19]: aloop-entry and a loop-exit conditional. The loop-entry condition must be truewhen entering the loop and false after each subsequent execution of the loopbody. Symmetrically, the loop-exit condition will have to be false in all exceptthe last iteration when it becomes true and the loop is exited. We implement theloop using the paired branch approach (labels 30-35): at loop entry we expectt = 0 and at loop-exit t = tend . When the loop is repeated by jumping from 35to 30, BNE and BGTZ are both executed because 0 < t < tend . The instructions at30 and 35 are negations of the loop-entry and loop-exit conditions, respectively.The paired offsets are 5 and -5. Branch instructions BNE and BGTZ are identicalto BEQ (Fig. 3), except that they branch on �= and > 0 instead of =.

A reversible subroutine should be callable from different places in a program.For this purpose, the paired branch approach does not suffice as a “callee branch”can only point back to a single “caller branch”. When a non-recursive subroutineis called, the “return address” in the guise of the branch register is swappedwith a zero-cleared return register (here, rtn), using instruction SWAPBR andchanging the sign using instruction NEG (labels 28-29). After the swap br = 0,which means that normal sequential execution is resumed and the subroutinebody is executed. The body is enclosed in paired branches, as discussed above,so at the end of the subroutine execution we reach the same SWAPBR instructionat which we entered the subroutine. The effect of this will be return to the caller.Recursive subroutines are implemented by maintaining a call stack with “returnaddresses” instead of a single return register rtn.

We can now solve the following simulation problem: an object is dropped fromthe top of a tower 1000 m in height. What is the height of the object after a free

Reversible Machine Code and Its Abstract Processor Architecture 67

fall of 5 s? This can be calculated (labels 10-12) by initializing registers h andtend with the corresponding values and calling the subroutine, implemented byan unconditional jump BRA to the procedure entry (label 28). Recall that allregisters are initially zero-cleared so register v already has the required value.

With the same subroutine, we can also solve the following inverse simulationproblem: after a free fall of 4 s, an object reaches the ground with a downwardvelocity of 40 m/s. How tall is the tower? To solve this problem, we change theexecution direction and run the forward simulation backwards (labels 18-21).The RBRA instruction (Fig. 3) changes the direction bit and runs the subroutinebackwards, i.e. it uncalls the subroutine. Sharing the forward and backward codeis possible because the abstract machine allows changing the execution direction.Note that forward and backward computation of the subroutine take the samenumber of execution steps, and thus there is no penalty for running the forwardcode backward, or vice versa.

An abstract machine may have a forward and backward deterministic exe-cution relation, which means that no information is lost and the machine canbe implemented on reversible hardware. However, as long as there is no facilityto change the machine’s execution direction while running, we cannot share thecode of a subroutine and its inverse. In this case, it will be necessary to implementtwo subroutines—one for forward and another for backward computation.

5 Related Work

A great deal of the previous work on reversible machine code suffered from defi-ciencies. In [3], a history trace was used for reversibility as suggested earlier [13];in [12] data modification was reversible, but the control logic was unclear andquite probably irreversible; and in [8] the control logic and certain control flowinstructions were irreversible. We stress that even if each instruction is reversible,this is not sufficient to ensure reversibility of the complete architecture.

In contrast, PISA is the newest and most complete design of a reversible ar-chitecture [16]. The description of the instruction set is informal [7], but ourformalization has been shown to be reversible as described in this paper. Thismakes PISA the only truly reversible practical programmable architecture. Re-versible logic gates [9,6] and reversible logic circuits [4,5] have been studied.

A high-level imperative language for reversible programming, Janus, has re-cently been formalized and confirmed to be reversible [19]. One of the earliestworks considering reversible subroutines was [15].

Reversible languages, such as Janus and PISA, allow efficient standard andinverse computation. A general method for inverse computation is the UniversalResolving algorithm [1], which also allows inverse computation of programs thatdo not implement injective functions, but is less efficient due to the search space.

6 Conclusions and Future Work

In this paper, we have formally described an abstract machine suitable for re-versible computing. We clarified that for machine code to be fully reversible both

68 H.B. Axelsen, R. Gluck, and T. Yokoyama

the underlying control logic as well as each instruction must be reversible, andthat forward and backward code can be shared if the machine allows a programto switch between standard (forward) and inverse (backward) computation. Wehave shown a general class of instruction sets that are reversible, building onour concept of reversible updates. We have shown that PISA, as a member ofthis class, is reversible. Finally, we gave programming principles for the abstractmachine architecture formalized in this paper.

We posit that reversible computing is sufficiently different from irreversiblecomputing to warrant consideration as a separate paradigm. As such, we sug-gest a “principles first” approach to reversible machine architectures. Designingand implementing hardware for a minimal instruction set based on the princi-ples outlined in this paper could serve as a first effort in this direction. Workon a translator from the structured high-level reversible programming languageJanus [19] to PISA is currently in progress.

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2. Bennett, C.H.: Logical reversibility of computation. IBM Journal of Research andDevelopment 17(6), 525–532 (1973)

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4. De Vos, A., Van Rentergem, Y., De Keyser, K.: The decomposition of an arbitraryreversible logic circuit. Journal of Physics A: Mathematical and General 39(18),5015–5035 (2006)

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6. Feynman, R.P.: Reversible computation and the thermodynamics of computing(chapter 5). In: Feynman Lectures on Computation, pp. 137–184. Addison-Wesley,Reading, MA, USA (1996)

7. Frank, M.P.: Reversibility for Efficient Computing. PhD thesis, MIT (1999)8. Frank, M.P., Rixner, S.: Tick: A simple reversible processor (6.371 project report).

Online term paper, MIT EECS Department (1996)9. Fredkin, E., Toffoli, T.: Conservative logic. Intl. J. Theor. Phy. 21, 219–253 (1982)

10. Gluck, R., Kawabe, M.: A program inverter for a functional language with equalityand constructors. In: Ohori, A. (ed.) APLAS 2003. LNCS, vol. 2895, pp. 246–264.Springer, Heidelberg (2003)

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A Appendix: Proof Sketches

Proof Sketch for Thm. 1. Each instruction is a reversible update of somepart of the state (e.g., a register), and can therefore be considered an injectivefunction on the state. Thus, →inst is injective for each individual instruction. Therestriction that pc is preserved ensures that the program counter of the previousstate is unique, as →pc is injective by simple case analysis. The restriction thatM(pc) is preserved ensures that the previous instruction executed is also unique,so the injectivity of →inst for this instruction then gives the injectivity of →ie .The composition of two injective functions is itself injective, so →1 is injective.

Proof Sketch for Thm. 2. It can easily be shown that

(→pc)−1 = flip ◦ (→pc) ◦ flip and (→ie)

−1 = flip ◦ (→ie) ◦ flip.

Note that flip and rev are self-inverse functions Σ → Σ. In the equation sequencebelow, the term to be reduced/expanded in each successive equation is underlinedto make it easier to understand. This is equivalent to the claim of Thm. 2.

(→1)−1 = (→ie)

−1 ◦ (→pc)−1 = (→ie)

−1 ◦ flip ◦ (→pc) ◦ flip

= (→ie)−1 ◦ flip ◦ rev = id ◦ (→ie)

−1 ◦ flip ◦ rev

= (→pc) ◦ (→pc)−1 ◦ (→ie)

−1 ◦ flip ◦ rev

= (→pc) ◦ flip ◦ (→pc) ◦ flip ◦ (→ie)−1 ◦ flip ◦ rev

= rev ◦ (→pc) ◦ flip ◦ (→ie)−1 ◦ flip ◦ rev

= rev ◦ (→pc) ◦ flip ◦ flip ◦ (→ie) ◦ flip ◦ flip ◦ rev

= rev ◦ (→pc) ◦ (→ie) ◦ rev = rev ◦ (→1) ◦ rev

Proof Sketch for Thm. 3. By case analysis on →inst , each instruction inPISA (without the four I/O instructions READ, SHOW, EMIT, TAKE ) canbe shown to be a reversible update. No instruction in PISA can modify pc andmemory access is specifically restricted from modifying the current instruction,M(pc). Thus, Thm. 1 holds for PISA. The inverse of each instruction is easilyspecified by the reversible update as instruction in PISA, and so Thm. 2 holds.