Characterization of CapacitorsWhat characterizes a capacitor?1.) Dissipation (quality factor) of a capacitor is
Q = CRp = C
Rs
where Rp is the equivalent resistance in parallel with the capacitor, C, and Rs is the electrical series resistance (ESR) of the capacitor, C.
2.) Parasitic capacitors to ground from each node of the capacitor.3.) The density of the capacitor in Farads/area.4.) The absolute and relative accuracies of the capacitor.5.) The Cmax/Cmin ratio which is the largest value of capacitance to the smallest when
the capacitor is used as a variable capacitor (varactor).6.) The variation of a variable capacitance with the control voltage.7.) Linearity, q = Cv.
PN-Junction Capacitors – ContinuedThe anode should be the floating node and the cathode must be connected to ac ground.Experimental data (Q at 2GHz, 0.5μm CMOS)†:
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00.5
1
1.52
2.5
3
3.54
0 0.5 1 1.5 2 2.5 3 3.5
CA
node
(pF
)
Cathode Voltage (V)
Large Islands
Small Islands
Cmax Cmin
0
20
40
60
80
100
120
0 0.5 1 1.5 2 2.5 3 3.5
QA
node
Qmin Qmax
Large Islands
Small Islands
Cathode Voltage (V)
R-XBridge
Anode Cathode
CathodeVoltage
C
R-XBridge
Anode Cathode
CathodeVoltage
C
Small Islands (598 1.2μm x1.2μm) Large Islands (42 9μm x 9μm)TerminalUnder Test Cmax/Cmin Qmin Qmax Cmax/Cmin Qmin Qmax
† E. Pedersen, “RF CMOS Varactors for 2GHz Applications,” Analog Integrated Circuits and Signal Processing, vol. 26, pp. 27-36, Jan. 2001.
Electrons as majority carriers lead to higher Q because of their higher mobility.The resistance, Rwj, is reduced in small islands compared with large islands higher Q
MOSFET GATE CAPACITORSMOSFET Gate Capacitor StructureThe MOSFET gate capacitors have the gate as one terminal of the capacitor and somecombination of the source, drain, and bulk as the other terminal.In the model of the MOSFET gate capacitor shown below, the gate capacitance is reallytwo capacitors in series depending on the condition of the channel.
Conditions:• Remove p+ drain and source and put n+ bulk contacts instead.• Implements a variable capacitor with a larger transition region between the maximum
and minimum values.• Reasonably linear capacitor for values of VGB > 0
Metal-Insulator-Metal (MiM) CapacitorsIn some processes, there is a thin dielectric between a metal layer and a special metallayer called “capacitor top metal”. Typically the capacitance is around 1fF/μm2 and isat the level below top metal.
Metal-Insulator-Metal Capacitors – Lateral and Vertical FluxCapacitance between conductors on the same level and use lateral flux.
These capacitors are sometimes called fractal capacitors because the fractal patterns arestructures that enclose a finite area with a near-infinite perimeter.The capacitor/area can be increased by a factor of 10 over vertical flux capacitors.
Some of the possible metal capacitor structures include:1.) Horizontal parallel plate (HPP).
2.) Parallel wires (PW):
† R. Aparicio and A. Hajimiri, “Capacity Limits and Matching Properties of Integrated Capacitors, IEEE J. of Solid-State Circuits, vol. 37, no. 3, March
Horizontal Metal Capacitors - ContinuedExperimental results for a CMOS process with 3 layers of metal, Lmin =0.5μm, tox =0.95μm and tmetal = 0.63μm for the bottom 2 layers of metal.
Experimental results for a digital CMOS process with 7 layers of metal, Lmin =0.24μm,tox = 0.7μm and tmetal = 0.53μm for the bottom 5 layers of metal. All capacitors = 1pF.
Horizontal Metal Capacitors - ContinuedHistogram of the capacitance distribution forthe above case (1 pF):
Experimental results for a digital CMOSprocess with 7 layers of metal, Lmin =0.24μm, tox = 0.7μm and tmetal = 0.53μm forthe bottom 5 layers of metal (all capacitors =10pF):
DEVIATION FROM IDEAL BEHAVIOR IN CAPACITORSCapacitor Errors1.) Dielectric gradients2.) Edge effects3.) Process biases4.) Parasitics5.) Voltage dependence6.) Temperature dependence
Capacitor Errors - Oxide GradientsError due to a variation in dielectric thickness across the wafer.Common centroid layout - only good for one-dimensional errors:
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2C C 2C CNo common centroid layout Common centroid layout
An alternate approach is to layout numerous repetitions and connect them randomly toachieve a statistical error balanced over the entire area of interest.Improved matching of three components, A, B, and C:
Capacitor Errors - Edge EffectsThere will always be a randomness on the definition of the edge.However, etching can be influenced by the presence of adjacent structures.For example,
AC
A BC
B
Matching of A and B are disturbed by the presence of C.
Improved matching achieve by matching the surroundings of A and B.
Process Bias on CapacitorsConsider the following two capacitors:
If L1 = L2 = 2μm, W2 = 2W1 = 4μm andx = 0.1μm, the ratio of C2 to C1 can
be written as,C2C1
= (2-.2)(4-.2)(2-.2)(2-.2) =
3.81.8 = 2.11 5.6% error in matching
How can this matching error be reduced?The capacitor ratios in general can be expressed as,
C2C1
= (L2-2 x)(W2-2 x)(L1-2 x)(W1-2 x) =
W 2W 1
1 -2 xW 2
1 -2 xW 1
W 2W 1
1 -2 xW 2
1 +2 xW 1
W 2W 1
1 -2 xW 2
+2 xW 1
Therefore, if W2 = W1, the matching error should be minimized. The best matchingresults between two components are achieved when their geometries are identical.
Replication PrincipleBased on the previous result, a way to minimize the matching error between two or moregeometries is to insure that the matched components have the same area to peripheryratio. Therefore, the replication principle requires that all geometries have the same area-periphery ratio.Correct way to match the previous capacitors (the two C2 capacitors are connectedtogether):
If L1 = L2 = 2μm, W2 = 2W1 = 2μm and x = 0.1μm, the ratio of C2 to C1 can be writtenas,
C2C1
= 2(2-.2)(2-.2)(2-.2)(2-.2) =
2·1.81.8 = 2 0% error in matching
The replication principle works for any geometry and includes transistors, resistors aswell as capacitors.
Capacitor Errors - Relative AccuracyCapacitor relative accuracy is proportional to the area of the capacitors and inverselyproportional to the difference in values between the two capacitors.For example,
Accurate matching of capacitors depends on the following influence:1.) Mismatched perimeter ratios2.) Proximity effects in unit capacitor photolithography3.) Mismatched long-range fringe capacitance4.) Mismatched interconnect capacitance5.) Parasitic interconnect capacitanceLong-range fringe capacitance:
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Shield to collect long-range fringe fields? ? ? ?
Obviously there will be a tradeoff between matching and speed.
† M.J. McNutt, S. LeMarquis and J.L.Dunkley, “Systematic Capacitance Matching Errors and Corrective Layout Procedures,” IEEE J. of Solid-StateCircuit, vo. 29, No. 5, May 1994, pp. 611-616.
ShieldingThe key to shielding is to determine and control the electric fields.Consider the following noisy conductor and its influence on the substrate:
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Substrate
Noisy Conductor
SubstrateShield
SeparateGround
Noisy Conductor
Increased Parasitic Capacitance
Use of bootstrapping to reduce capacitor bottom plate parasitic:
Definition of Temperature and Voltage CoefficientsIn general a variable y which is a function of x, y = f(x), can be expressed as a Taylorseries,
y(x) y(x0) + a1(x- x0) + a2(x- x0)2+ a3(x- x0)3 + ···where the coefficients, ai, are defined as,
a1 = df(x)dx
|x=x0 , a2 =
12
d2f(x)dx2
|x=x0 , ….
The coefficients, ai, are called the first-order, second-order, …. temperature or voltagecoefficients depending on whether x is temperature or voltage.Generally, only the first-order coefficients are of interest.
In the characterization of temperature dependence, it is common practice to use a termcalled fractional temperature coefficient, TCF, which is defined as,
TCF(T=T0) = 1
f(T=T0) df(T)dT
|T=T0 parts per million/°C (ppm/°C)
or more simply,
TCF = 1
f(T) df(T)dT parts per million/°C (ppm/°C)
A similar definition holds for fractional voltage coefficient.
Future Technology Impact on CapacitorsWhat will be the impact of scaling down in CMOS technology?• The capacitance can be divided into gate capacitance and overlap capacitance.
Gate capacitance varies with external voltage changesOverlap capacitances are constant with respect to external voltage changes
As the channel length decreases, the gate capacitance becomes less of the totalcapacitance and consequently the Cmax/Cmin will decrease. However, the Q of thecapacitor will increase because the physical dimensions are getting smaller.
• For UDSM, the gate leakage current will eliminate gate capacitors from being useful.Best capacitor for future scaled CMOS?
Polysilicon-polysilicon or metal-metal (too much leakage current in gatecapacitors)Best varactor for future scaled CMOS?
The standard mode CMOS depletion capacitor because Cmax/Cmin is larger thanthat for the accumulation mode and Q should be sufficient. The pn junction will bemore useful for UDSM.
• Capacitors are characterized by:- Q, a measure of the loss- Density- Parasitics- Absolute and relative accuracies
• Deviations from ideal capacitor behavior include;- Dielectric gradients- Edge effects (etching)- Process biases- Parasitics- Voltage and temperature dependence
