Lecture Outline - Penn Engineeringese570/spring2018/... · Lec 13: February 27, 2018 Combination...

1

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

Lec 13: February 27, 2018 Combination Logic: CMOS (con’t), Ratioed

and Pass Logic

Penn ESE 570 Spring 2018 – Khanna

Lecture Outline

!  CMOS Worst Case Analysis !  Driving a large load !  Ratioed Logic Gates !  Pass Transistor Gates

3 Penn ESE 570 Spring 2018 – Khanna

Parasitic Caps for NOR2 (worst case)

4

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd

Csb1p = Csb2p = Cd Cd

Cd

Cd

Cd Cd



5

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD



6

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd




7

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = VDD-> 0 @t=0 & Vx ≈ Vout = 0 -> VDD Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg

RpEQV = Rp2+Rp1 Lumped Model Penn ESE 570 Spring 2018 – Khanna

2


8

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd


Elmore Model? Cload-NR2 ≈ 2Cd + 3Cd + Cint + 2Cg

RpEQV = Rp2+Rp1



9

Vx

2Cg

Cd

Cd

Cd

Cd Cd



10

Vx

2Cg

Cd

Cd

Cd

Cd Cd


τ = (2Cd)(Rp2)+(3Cd+Cint+2Cg)(Rp1+Rp2)


11

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd



12

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd

V1 = 0, V2 = 0 ->VDD @t=0 & Vx ≈ Vout=VDD-> 0



13

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd



3


14

Vx

2Cg

Cdbn1 = Cdbn2 = Cd

Cdbp1 = Cdbp2 = Cd


Cd

Cd

Cd Cd


Elmore Model? Penn ESE 570 Spring 2018 – Khanna


15

Vx

2Cg

Cd

Cd

Cd

Cd Cd



16

Vx

2Cg

Cd

Cd

Cd

Cd Cd


τ = (2Cd)(Rp1+Rn2)+(3Cd+Cint+2Cg)(Rn2)

17

Vx

V1

V2

2Cg

Cdbp1 = Cdbp2 = Cdbp

Cdbn1 = Cdbn2 = Cdbn

Csb1n = Csb2n = Csbn = Cdbn

Parasitic Caps for NAND2 (worst case)


18

Vx

V1

V2

2Cg






19

Vx

V1

V2

2Cg





V1 = VDD, V2 = VDD-> 0 @t=0 & Vx ≈ Vout= 0 ->VDD


4

20

Vx

V1

V2

2Cg






21

Vx

V1

V2

2Cg





V1 =VDD, V2 = 0 ->VDD @t=0 & Vx≈ Vout=VDD-> 0


Driving Large Load


Driving large load

23

CLOAD

standard CMOS logic on

die

INV1


Driving large load

24

CLOAD


die

INV1

A DESIGN STRATEGY: Make buffer (W/L)n and (W/L)p sufficiently large to drive CLOAD with a specified τP.

Buffer

How do you feel about this design strategy?


Super-Buffer to Drive Large CLOAD

25

CLOAD

CLOAD

PROBLEM: A minimum sized inverter drives a large load CLOAD, leading to

excessive delay, even with a large buffer (large W/L). SOLUTION: Insert N inverter stages in cascade with

increasing W/L between INV1 and load CLOAD. The total delay through N smaller stages will be less than the delay

through a single large stage driving CLOAD.

VDD

VDD N = 3


die

INV1

CLOAD


5


26

INV1

Stage-0

a -> stage scale factor > 1

NOTE for CMOS INV: Cd = Cdbn + Cdbp Cg = Cgbn + Cgbp

CLOAD



27

INV1

Stage-0


Wn1 = aWn0, Ln1 = Ln0 and Wp1 = aWp0, Lp1 = Lp0


CLOAD



28

INV1

Stage-0


Wn2 = aWn1, Ln2 = Ln1 and Wp2 = aWp1, Lp2 = Lp1


CLOAD



29

INV1

Stage-0


Wni = aiWn0, Lni = Ln0 and Wpi = aiWp0, Lpi = Lp0 for i = 0, 1, 2, ..., N


CLOAD



30

INV1

Stage-0



Stage load capacitances Cloadi are also scaled by a

Cloadi = ai Cload0


CLOAD



31

INV1

Stage-0




Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N


CLOAD


6


32

INV1

Stage-0




Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg


CLOAD



33

INV1

Stage-0




Cloadi = ai Cload0 = ai (Cd + aCg) for i = 0, 1, 2, .., N when i = N: CloadN = aN Cload0 = aN (Cd + aCg) => let CLOAD = aN(aCg) = aN+1Cg

CLOAD/Cg = aN+1 =>

NOTE for CMOS INV:

N is rounded up to nearest integer value.

Cd = Cdbn + Cdbp Cg = Cgbn + Cgbp

CLOAD

N =ln(CLOAD Cg )

lna−1


34

NOTE: ALL inverters Stage-0 through Stage-N have the same gate delay

CLOAD

CLOAD

τ p =τ PHL +τ PLH

2= Γ

Cload

W



35


Let τ0 = gate delay for INV1 (with a = 1) with load Cload = Cd + Cg

CLOAD

CLOAD


2= Γ

Cload

W


τ0 = (Cd +Cg ) W0


36


CLOAD

CLOAD


2= Γ

Cload

W


τ p0

τ 0=

Cload0 W0

(Cd +Cg ) W0

=Cd + aCg

Cd +Cg

⇒ τ p0 = τ 0Cd + aCg

Cd +CgFor Stage-0:


τ0 = (Cd +Cg ) W0

37

CLOAD

CLOAD


τ p0

τ 0=

Cload0 W0

(Cd +Cg ) W0

=Cd + aCg

Cd +Cg


Cd +CgFor Stage-0:

For Stage-1:

For Stage-N:

τ p1

τ 0=

Cload1 aW0

(Cd +Cg ) W0

=aCd + a

2Cg( ) / aCd +Cg


Cd +Cg

= τ p0

τ pN

τ 0=CloadN aNW0

(Cd +Cg ) W0

=aNCd + a

N+1Cg( ) / aNCd +Cg

⇒ τ pN = τ 0Cd + aCg

Cd +Cg

= τ p0


7

38

CLOAD

CLOAD


τ p0

τ 0=

Cload0 W0

(Cd +Cg ) W0

=Cd + aCg

Cd +Cg


Cd +CgFor Stage-0:

For Stage-1:

For Stage-N:

τ p1

τ 0=

Cload1 aW0

(Cd +Cg ) W0

=aCd + a

2Cg( ) / aCd +Cg


Cd +Cg

= τ p0

τ pN

τ 0=CloadN aNW0

(Cd +Cg ) W0

=aNCd + a

N+1Cg( ) / aNCd +Cg

⇒ τ pN = τ 0Cd + aCg

Cd +Cg

= τ p0

τ total = (N +1)τ p0 = (N +1)τ 0Cd + aCg

Cd +Cg

Choose N and a to minimize τtotal Penn ESE 570 Spring 2018 – Khanna


39

Wni = aiWn0 Wpi = aiWp0


Cd +Cg

N =ln(CLOAD Cg )

lna−1

τ total =ln(CLOAD Cg )

lnaτ 0Cd + aCg

Cd +Cg



40


TO MINIMIZE τtotal:


Cd +Cg

N =ln(CLOAD Cg )

lna−1


lnaτ 0Cd + aCg

Cd +Cg

dτ totalda

= τ 0 ⋅ lnCLOAD

Cg

⋅−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

#

$%%

&

'((= 0

−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

= 0

aopt lnaopt −1#$ &'=Cd

Cg



41


TO MINIMIZE τtotal:


Cd +Cg

N =ln(CLOAD Cg )

lna−1


lnaτ 0Cd + aCg

Cd +Cg

dτ totalda

= τ 0 ⋅ lnCLOAD

Cg

⋅−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

#

$%%

&

'((= 0

−1/ alna( )2

Cd + aCg

Cd +Cg

+1lna

Cg

Cd +Cg

= 0

aopt lnaopt −1#$ &'=Cd

Cg

Cd = 0 is only an academic special case. Penn ESE 570 Spring 2018 – Khanna

42

EXAMPLE: Design a Buffer using a scaled cascade of inverters to achieve minimum total delay ttotal when CLOAD = 100 Cg. Consider the case where Cd = 2Cg.

e

Cd = 2Cg => plot aopt as function of Cd/Cg: aopt = 4.35 => ln aopt = 1.47

CLOAD≈ 100Cg

CdCg

= aopt [ln aopt− 1]Cd

Cd/Cg = 2

aopt= 4.35


N =ln(CLOAD Cg )

lna−1= 2.13→ N = 3


Ratioed Logic


8

Previously

!  Restoration and Noise Margins "  Allows for gate abstraction

!  CMOS Gates "  Drive outputs rail-to-rail "  Only one network turned on in steady state

"  Only subthreshold leakage current in steady state


Today

!  Ratioed Gates "  Break all the rules… (nice properties)

"  No rail-to-rail outputs, steady-state-current is not subthreshold…

"  Logic correctness "  Performance "  Power "  Implications


Idea

!  Building both pull-up and pull-down can be expensive – many gates

!  Seems wasteful to build logic function twice "  Once in pullup, once in

pulldown "  Large gate capacitance


Idea

!  Maybe only need to build one !  Build NFET pulldown

"  Exploit high N mobility "  traditional


Ratioed Inverter

!  Does this work? "  What is Vout for Vin=Gnd ? "  What is Vout for Vin=Vdd ?

48

WP=1

WN=1


Ratioed Inverter in 22nm


9



DC Transfer Function


Ratioed Inverter

!  How do we need to size P to make it work?

52

WN=1




P vs. N

!  Conclude: still prefer N to P for ratioed logic


Noise Margin Tradeoff

!  What is impact of increasing noise margin? "  On size "  On input capacitance


10

Pass Transistor Logic


Teaser

!  What does this do?


Identify Function

!  What function is this?


Output

!  What is Vout if A=1, B=1?

59

A B Y

0 0

0 1

1 0

1 1


Output


60

A B Y

0 0

0 1

1 0

1 1 0


Output


61

A B Y

0 0

0 1

1 0

1 1 0


11

Output


62

A B Y

0 0

0 1 1

1 0

1 1 0


Output

!  What is Vout if A=0, B=0? if A=1, B=0?

63

A B Y

0 0

0 1 1

1 0

1 1 0


Output

!  What is Vout if A=0, B=0? if A=1, B=0?

64

A B Y

0 0 0

0 1 1

1 0 1

1 1 0


Area

!  Compare PT with CMOS circuit?


Output

!  Is this a regenerating/restoring gate?

66

A B Y

0 0 0

0 1 1

1 0 1

1 1 0


Output

!  What does output look like (DC transfer)? "  (B=1, notB=0, sweep A, notA=CMOS inv(A))


12

Pass TR transfer (B=1)

68 Sweep A


CMOS Inverter Transfer


Reasonable Input to CMOS Inverter?


Pass Transistor xor2 with inv restore


Compare CMOS

!  Is this a fair comparison?


Required to use?

!  What should we add to make substitutable with CMOS?


13

Restore Output


Restore Output

!  Area? (compare to CMOS)


Chain Together


Analyze Stage


Delay A=1, B=0, Cdiff≠0?



!  What’s the equivalent RC circuit?


14

80




Rup Run




82




Bonus

!  What does this do?

83

A

B

A B Y

0 0

0 1

1 0

1 1


Idea

!  CMOS Logic "  Complimentary dual pull-up/down networks "  Drive large load in scaled stages

!  There are other logic disciplines "  We have the tools to analyze

!  Ratioed Logic "  Tradeoff noise margin for

"  Reduced area? Capacitive load?

"  Dissipates static power in one mode

!  Can use pass transistors for logic "  Sometimes gives area or delay win


Midterm Exam

!  Midterm – 3/13 "  During class

"  Starts at exactly 1:30pm, ends at exactly 2:50pm (80 minutes)

"  Location LRSM Auditorium "  Old exams posted on old course websites "  Covers Lec 1- 13 "  Closed book, no notes or cheat sheets "  Calculators allowed and recommended, no smart phones "  Review Session by TA TBD (likely 3/11) "  Tania Office hours moved to Monday (3/12) 2-4:30pm


15

Admin

!  HW 5 due Thursday, 3/1 !  Quiz 2

"  VERY leniently graded "  Q4 not graded, everyone got full credit for it "  Not enough perfect scores, no oral makeups

"  However, I will include extra credit question on midterm exam "  STUDY FOR THE MIDTERM!


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Lecture Outline - Penn Engineeringese570/spring2018/... · Lec 13: February 27, 2018 Combination...

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