lecture6_FPGA

7/31/2019 lecture6_FPGA

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George Mason UniversityECE 545 Introduction to VHDL

FPGA Devicesand

FPGA Design Flow

ECE 545Lecture 6


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2ECE 545 Introduction to VHDL

Resources

Xilinx, Inc.Spartan-3 FPGA Introduction

Features

Architectural Overview

Spartan-3 FPGA Functional Description

CLB Overview,

Block RAM Overview

Dedicated Multipliers

http://direct.xilinx.com/bvdocs/publications/ds099.pdf
http://direct.xilinx.com/bvdocs/publications/ds099.pdfhttp://direct.xilinx.com/bvdocs/publications/ds099.pdf


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Resources

Integrated Interfaces: Active-HDL with Synplify

Integrated Synthesis and Implementation

Movie Demos

Active-HDL Help
http://www.aldec.com/products/active-hdl/multimediademo/movies/active_hdl_with_synplify/http://www.aldec.com/products/active-hdl/multimediademo/movies/fpga_synth_implement/http://www.aldec.com/products/active-hdl/multimediademo/movies/fpga_synth_implement/http://www.aldec.com/products/active-hdl/multimediademo/movies/fpga_synth_implement/http://www.aldec.com/products/active-hdl/multimediademo/movies/active_hdl_with_synplify/http://www.aldec.com/products/active-hdl/multimediademo/movies/active_hdl_with_synplify/http://www.aldec.com/products/active-hdl/multimediademo/movies/active_hdl_with_synplify/


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designs must be sentfor expensive and timeconsuming fabricationin semiconductor foundry

bought off the shelfand reconfigured bydesigners themselves

Two competing implementation approaches

ASICApplicationSpecificIntegratedCircuit

FPGAFieldProgrammableGateArray

designed all the wayfrom behavioral descriptionto physical layout

no physical layout design;design ends witha bitstream usedto configure a device


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Which Way to Go?

Off-the-shelf

Low development cost

Short time to market

Reconfigurability

High performance

ASICs FPGAs

Low power

Low cost inhigh volumes


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7/1047ECE 545 Introduction to VHDL

FPGA vendors

and

FPGA families



1945 1950 1955 1960 1965 1970 1975 1980 1985 1990 1995 2000

FPGAs

ASICs

CPLDs

SPLDs

Microprocessors

SRAMs & DRAMs

ICs (General)

Transistors

The Design Warriors Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043

Copyright 2004 Mentor Graphics Corp. (www.mentor.com)

Technology Timeline



Major FPGA vendors

SRAM-based FPGAsXilinx Inc. www.xilinx.com

Altera Corp. www.altera.com

Atmel Corp. www.atmel.com

Lattice Semiconductor Corp.

www.latticesemi.com

Antifuse and flash-based FPGAsActel Corp. www.actel.com

QuickLogic Corp.www.quicklogic.com
http://www.xilinx.com/http://www.altera.com/http://www.atmel.com/http://www.latticesemi.com/http://www.actel.com/http://www.quicklogic.com/http://www.quicklogic.com/http://www.actel.com/http://www.latticesemi.com/http://www.atmel.com/http://www.altera.com/http://www.xilinx.com/



State-of-the-art

Feature

Technology node

SRAM AntifuseE2PROM /

FLASH

One or more

generations behind

One or more

generations behind

Fast

Reprogrammingspeed (inc.

erasing)----

3x slower

than SRAM

Yes

Volatile (must

be programmedon power-up)

NoNo

(but can be if required)

MediumPower

consumptionLow Medium

Acceptable(especially when using

bitstream encryption)

IP Security Very Good Very Good

Large

(six transistors)

Size ofconfiguration cell

Very smallMedium-small

(two transistors)

NoRad Hard Yes Not really

NoInstant-on Yes Yes

YesRequires external

configuration fileNo No

Yes

(very good)

Good forprototyping

NoYes

(reasonable)

Yes

(in system)Reprogrammable No

Yes (in-system

or offline)





The Programmable MarketplaceQ1 Calendar Year 2005

Source: Company reportsLatest information available; computed on a 4-quarter rolling basis

XilinxAltera

LatticeActel

QuickLogic: 2% Xilinx

All Others

Two dominant suppliers, indicating a maturing market

PLD Segment FPGA Sub-Segment

Other: 2%

51%33%

5% 7%

Altera

58%

31% 11%



PLD Market Share

Source: Gartner Dataquest

$2.3B$2.6B$4.1B$2.6B$2.1B $2.6B $3.1B

31% 33% 34% 32% 31% 32% 32%

39%32%

28% 24% 20% 18% 17%

49%50%

44%38%

35%30%

51%

0%

20%

40%

60%

80%

100%

Calendar year 1998 1999 2000 2001 2002 2003 2004

MarketSha

re(%)

Xilinx Altera All Others



FPGA families

Spartan 3 Virtex 4 LX / SX / FXSpartan 3E Virtex 5 LXSpartan 3L

Low-cost High-performance

Xilinx

Altera Cyclone II Stratix II

Stratix II GX



Xilinx

Primary products: FPGAs and the associated CAD

software

Main headquarters in San Jose, CA

Fabless* Semiconductor and Software Company

UMC (Taiwan) {*Xilinx acquired an equity stake inUMC in 1996}

Seiko Epson (Japan)

TSMC (Taiwan)

ProgrammableLogic Devices ISE Alliance and Foundation

Series Design Software

Source: [Xilinx Inc.]



Xilinx FPGA Families

Old families

XC3000, XC4000, XC5200 Old 0.5m, 0.35m and 0.25m technology. Not

recommended for modern designs.

Low Cost Family

Spartan/XL derived from XC4000

Spartan-II

derived from Virtex Spartan-IIE derived from Virtex-E

Spartan-3, Spartan 3E, Spartan 3L

High-performance families

Virtex (220 nm)

Virtex-E, Virtex-EM (180 nm) Virtex-II, Virtex-II PRO (130 nm)

Virtex-4 (90 nm)

Virtex 5 (65 nm)

Source: [Xilinx Inc.]

P i f h f ili f



Prices of the most recent families ofXilinx FPGAs

Spartan 3 Virtex II, Virtex II-Pro

< $130* < $3,000*

Spartan 3E Virtex 4

< $35* < $3,000*

* approximate cost of the largest device per unit for

a batch of 10,000 units

Low-cost High-performance



Xilinx FPGAs



BlockRAMs

BlockRAMs

ConfigurableLogicBlocks

I/OBlocks

Xilinx FPGA

Block

RAMs



CLB CLB

CLB CLB

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Logic cell

Slice

Logic cell

Configurable logic block (CLB)



Xilinx CLB



16-bit SR

flip-flop

clock

mux

y

qe

a

b

c

d

16x1 RAM

4-input

LUT

clock enable

set/reset



Simplified view of a Xilinx Logic Cell



LUT (Look-Up Table) Functionality

Look-Up tablesare primaryelements forlogic

implementation Each LUT can

implement anyfunction of 4

inputs

x1 x2 x3 x4

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

x1 x2 x3 x4

y

x1 x2 x3 x4

y

x1 x2

y

x1 x2

y

LUT

x1x2x3x4

y

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

0100010

101001100

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000

0

x10

x2 x3 x40 0

0 0 0 10 0 1 00 0 1 10 1 0 00 1 0 10 1 1 0

0 1 1 11 0 0 01 0 0 11 0 1 01 0 1 11 1 0 01 1 0 11 1 1 01 1 1 1

y

1111111

111110000


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5-Input Functions implemented using two LUTs

LUTLUT

X5 X4 X3 X2 X1 Y

0 0 0 0 0 0

0 0 0 0 1 1

0 0 0 1 0 0

0 0 0 1 1 0

0 0 1 0 0 1

0 0 1 0 1 1

0 0 1 1 0 0

0 0 1 1 1 0

0 1 0 0 0 1

0 1 0 0 1 0

0 1 0 1 0 0

0 1 0 1 1 1

0 1 1 0 0 1

0 1 1 0 1 1

0 1 1 1 0 1

0 1 1 1 1 1

1 0 0 0 0 0

1 0 0 0 1 0

1 0 0 1 0 0

1 0 0 1 1 0

1 0 1 0 0 0

1 0 1 0 1 0

1 0 1 1 0 01 0 1 1 1 1

1 1 0 0 0 0

1 1 0 0 1 1

1 1 0 1 0 0

1 1 0 1 1 1

1 1 1 0 0 0

1 1 1 0 1 1

1 1 1 1 0 0

1 1 1 1 1 0

LUTLUT

OUT


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RAM16X1S

O

D

WE

WCLKA0

A1

A2

A3

RAM32X1S

O

DWE

WCLKA0A1A2A3A4

RAM16X2S

O1

D0

WE

WCLKA0A1A2A3

D1

O0

=

=

LUT

LUT or

LUT

RAM16X1D

SPO

D

WE

WCLK

A0

A1

A2

A3

DPRA0 DPO

DPRA1

DPRA2

DPRA3

or

Distributed RAM

CLB LUT configurable asDistributed RAM A LUT equals 16x1 RAM

Implements Single and Dual-

Ports Cascade LUTs to increaseRAM size

Synchronous write

Synchronous/Asynchronousread Accompanying flip-flops used

for synchronous read


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D QCE

D QCE

D QCE

D QCE

LUT

INCE

CLK

DEPTH[3:0]

OUTLUT =

Shift Register

Each LUT can beconfigured as shift register Serial in, serial out

Dynamically addressabledelay up to 16 cycles

For programmablepipeline Cascade for greater cycle

delays Use CLB flip-flops to add

depth


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Shift Register

Register-rich FPGA Allows for addition of pipeline stages to increase

throughput

Data paths must be balanced to keep desiredfunctionality

64

Operation A

4 Cycles 8 Cycles

Operation B

3 Cycles

Operation C

64

12 Cycles

3 Cycles

9-Cycle imbalance


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16-bit SR

16 x 1 RAM

4-input LUT



Xilinx Multipurpose LUT


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16-bit SR

flip-flop

clock

mux

y

qe

a

b

c

d

16x1 RAM

4-input

LUT

clock enable

set/reset



Simplified view of a Xilinx Logic Cell


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COUT

D Q

CK

S

REC

D Q

CK

REC

O

G4G3G2G1

Look-UpTable

Carry

&

Control

Logic

O

YB

Y

F4F3F2F1

XB

X

Look-UpTable

F5IN

BY

SR

S

Carry

&

Control

Logic

CINCLKCE

SLICE

Carry & Control Logic


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Each CLB contains separatelogic and routing for the fastgeneration of sum & carrysignals

Increases efficiency andperformance of adders,subtractors, accumulators,comparators, and counters

Carry logic is independent ofnormal logic and routingresources

Fast Carry Logic

LSB

MSB

CarryLog

ic

Routing


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Accessing Carry Logic

All major synthesis tools can infer carrylogic for arithmetic functions

Addition (SUM


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CLB Slice Structure

Each slice contains two sets of the

following: Four-input LUT

Any 4-input logic function,

or 16-bit x 1 sync RAM (SLICEM only)

or 16-bit shift register (SLICEM only)

Carry & Control Fast arithmetic logic

Multiplier logic

Multiplexer logic

Storage element Latch or flip-flop Set and reset

True or inverted inputs

Sync. or async. control


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Block RAM(BRAM)


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Block RAM

Spartan-3Dual-Port

Block RAM

PortA

P

ortB

Block RAM

Most efficient memory implementation

Dedicated blocks of memory

Ideal for most memory requirements

4 to 104 memory blocks

18 kbits = 18,432 bits per block (16 k without parity bits)

Use multiple blocks for larger memories

Builds both single and true dual-port RAMs

RAM Blocks and Multipliers in Xilinx


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RAM blocks

Multipliers

Logic blocks

RAM Blocks and Multipliers in XilinxFPGAs




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Spartan-3 Block RAM Amounts


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Block RAM Port Aspect Ratios

0

16,383

1

4,095

4

0

8,191

2

0

2047

8+1

0

1023

16+2

0

16k x 1

8k x 2 4k x 4

2k x (8+1)

1024 x (16+2)


37/104


Block RAM Port Aspect Ratios


38/104


Single-Port Block RAM


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RAMB4_S16_S8

Port A Out18-Bit Width

Port B In2k-Bit Depth

Port A In1K-Bit Depth

Port B Out9-Bit Width

DOA[17:0]

DOB[8:0]

WEA

ENA

RSTA

ADDRA[9:0]

CLKA

DIA[17:0]

WEB

ENB

RSTB

ADDRB[10:0]

CLKB

DIB[8:0]

Dual-Port Bus Flexibility

Each port can be configured with a different data buswidth

Provides easy data width conversion without anyadditional logic


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0, ADDR[12:0]

1, ADDR[12:0]

RAMB4_S1_S1

Port B Out1-Bit Width

DOA[0]

DOB[0]

WEAENA

RSTA

ADDRA[12:0]

CLKA

DIA[0]

WEB

ENB

RSTB

ADDRB[12:0]

CLKB

DIB[0]

Port B In

8K-Bit Depth

Port A Out

1-Bit Width

Port A In8K-Bit Depth

Two Independent Single-Port RAMs

To access the lower RAM

Tie the MSB address bit toLogic Low

To access the upper RAM Tie the MSB address bit to

Logic High

Added advantage of True Dual-

Port No wasted RAM Bits

Can split a Dual-Port 16K RAM intotwo Single-Port 8K RAM

Simultaneous independent accessto each RAM


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Embedded Multipliers


43/104


18 x 18 Embedded Multiplier

Fast arithmetic functions Optimized to implement

multiply / accumulate modules

18 x 18 signed multiplier

Fully combinational

Optional registers with CE & RST (pipeline)

Independent from adjacent block RAM


44/104


18 x 18 Multiplier

Embedded 18-bit x 18-bit multiplier

2s complement signed operation

Multipliers are organized in columns

18 x 18Multiplier

Output(36 bits)

Data_A(18 bits)

Data_B(18 bits)

P iti f M lti li


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Positions of Multipliers


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Asynchronous 18-bit Multiplier


47/104


18-bit Multiplier with Register


48/104


Input/Output Blocks(IOBs)

Basic I/O Block Structure


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D

EC

Q

SR

D

EC

Q

SR

D

EC

Q

SR

Three-StateControl

Output Path

Input Path

Three-State

Output

Clock

Set/Reset

Direct Input

RegisteredInput

FF Enable

FF Enable

FF Enable

IOB F ti lit


50/104


IOB Functionality

IOB provides interface between thepackage pins and CLBs

Each IOB can work as uni- or bi-directional

I/O Outputs can be forced into High Impedance

Inputs and outputs can be registered

advised for high-performance I/O

Inputs can be delayed


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Spartan-3 Family Attributes

S t 3 FPGA F il M b


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Spartan-3 FPGA Family Members


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FPGA Design Flow


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Design process (1)

Design and implement a simple unit permitting to

speed up encryption with RC5-similar cipher with

fixed key set on 8031 microcontroller. Unlike in

the experiment 5, this time your unit has to be able

to perform an encryption algorithm by itself,

executing 32 rounds..

LibraryIEEE;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity RC5_core is

port(clock, reset, encr_decr: in std_logic;

data_input: in std_logic_vector(31downto0);

data_output: out std_logic_vector(31downto0);

out_full: in std_logic;

key_input: in std_logic_vector(31downto0);

key_read: out std_logic;

);

end AES_core;

Specification

VHDL description (Your VHDL Source Files)

Functional simulation

Post-synthesis simulationSynthesis


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Design Process control from Active HD


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Design Process control from Active-HD

Logic Synthesis


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architecture MLU_DATAFLOW of MLU is

signal A1:STD_LOGIC;

signal B1:STD_LOGIC;

signal Y1:STD_LOGIC;

signal MUX_0, MUX_1, MUX_2, MUX_3: STD_LOGIC;

begin

A1


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Synthesis Tools

and others

Features of synthesis tools


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Features of synthesis tools

Interpret RTL code

Produce synthesized circuit netlist in

a standard EDIF format Give preliminary performance

estimates

Some can display circuit schematicscorresponding to EDIF netlist

Timing report after s nthesis


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Timing report after synthesis

Performance Summary

*******************

Worst slack in design: -0.924

Requested Estimated Requested Estimated

Clock ClockStarting Clock Frequency Frequency Period Period Slack

Type Group-------------------------------------------------------------------------------------------------------exam1|clk 85.0 MHz 78.8 MHz 11.765 12.688 -0.924

inferred Inferred_clkgroup_0System 85.0 MHz 86.4 MHz 11.765 11.572 0.193

system default_clkgroup===========================================================

Implementation


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Implementation

After synthesis the entire implementationprocess is performed by FPGA vendor

tools


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Mapping


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Mapping

LUT2

LUT3

LUT4

LUT5

LUT1FF1

FF2

LUT0

Placing FPGA


64/104


Placing

CLB SLICES

FPGA

Routing FPGA


65/104


Routing

Programmable Connections

FPGA

Map report header


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Map report header

Release 7.1.03i Map H.41Xilinx Mapping Report File for Design 'exam1'

Design Information------------------Command Line : c:\Xilinx\bin\nt\map.exe -p 2S200FG256-6 -o map.ncd -pr b -k

4-cm area -c 100 -tx off exam1.ngd exam1.pcfTarget Device : xc2s200Target Package : fg256Target Speed : -6Mapper Version : spartan2 -- $Revision: 1.26.6.4 $

Mapped Date : Wed Nov 02 11:15:15 2005

Map report


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Map reportDesign Summary--------------

Number of errors: 0Number of warnings: 0Logic Utilization:Number of Slice Flip Flops: 144 out of 4,704 3%Number of 4 input LUTs: 173 out of 4,704 3%

Logic Distribution:Number of occupied Slices: 145 out of 2,352 6%Number of Slices containing only related logic: 145 out of 145 100%Number of Slices containing unrelated logic: 0 out of 145 0%

*See NOTES below for an explanation of the effects of unrelated logicTotal Number 4 input LUTs: 210 out of 4,704 4%

Number used as logic: 173Number used as a route-thru: 5Number used as 16x1 RAMs: 32

Number of bonded IOBs: 74 out of 176 42%Number of GCLKs: 1 out of 4 25%Number of GCLKIOBs: 1 out of 4 25

Place & route report


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Place & route report

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.

This may be due to a setup or hold violation.

--------------------------------------------------------------------------------

Constraint | Requested | Actual | Logic

| | | Levels--------------------------------------------------------------------------------

TS_clk = PERIOD TIMEGRP "clk" 11.765 ns | 11.765ns | 11.622ns | 13

HIGH 50% | | |

--------------------------------------------------------------------------------

OFFSET = OUT 11.765 ns AFTER COMP "clk" | 11.765ns | 11.491ns | 1

--------------------------------------------------------------------------------

OFFSET = IN 11.765 ns BEFORE COMP "clk" | 11.765ns | 11.442ns | 2--------------------------------------------------------------------------------

Post layout timing report


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Post layout timing report

Timing summary:---------------

Timing errors: 0 Score: 0

Constraints cover 42912 paths, 0 nets, and 1038 connections

Design statistics:

Minimum period: 11.622ns (Maximum frequency:86.044MHz)

Minimum input required time before clock: 11.442ns

Minimum output required time after clock: 11.491ns


70/104

Configuration of SRAM based FPGAs


71/104


Configuration data inConfiguration data out

= I/O pin/pad

= SRAM cell



Configuration of SRAM based FPGAs


72/104


Configuration times

of selected FPGAdevices


73/104


Timing of digital circuits

Timing Characteristics of Combinational


74/104


Circuits

Combinational Circuits AreCharacterized by Propagation Delays

through logic components (gates, LUTs)

through interconnects (routing delays)

tp LUT tp routing

LUT LUT LUT

Total propagation delay through combinational logic

Timing Characteristics of CombinationalCi it (2)


75/104


Circuits (2)

Total Propagation Delay of LogicDepends on the Number of Logic Levelsand Delays of Logic Components

Number of logic levels is the number oflogic components (gates, LUTs) the signalpropagates through

Routing Delays Depend on:

Length of interconnects Fanout



76/104


Circuits (3)

Fanout Number of Inputs Connectedto One Output

Each inputs has its capacitance

Fast switching of outputs with high fanoutrequires higher currents and strong drivers

LUT LUT

LUT

LUT



77/104


Circuits (4)

In Current Technologies Routing DelaysMake 45-65% of the Total PropagationDelays

Timing Characteristics of Sequential


78/104


Circuits (1)

Timing Features of Flip-flops Setup time tS minimum time the input has

to be stable before the rising edge of theclock

Hold time tH minimum time the input hasto be stable after the rising edge of theclock

Propagation delay tP time to propagate

input to output after the rising edge of theclock

Timing Characteristics of Sequential


79/104


Circuits (2)

D Q

clk

clk

D

Q

tS tH

tP

Input D must remainstable during

this interval

Input D can freelychange during

this interval

Critical Path (1)


80/104


Critical Path (1)

Critical Path The Longest Path FromOutputs of Registers to Inputs ofRegisters

D Qin

clk

D Qout

tlogic

tCritical = tFF-P + tlogic + tFF-setup

Critical Path (2)


81/104


Critical Path (2)

Min. Clock Period = Length of TheCritical Path

Max. Clock Frequency = 1 / Min. ClockPeriod


82/104


n+m

n+m

Clock Jitter


83/104


Clock Jitter

Rising Edge of The Clock Does NotOccurPrecisely Periodically

May cause faults in the circuit

clk

Clock Skew


84/104


Clock Skew

Rising Edge of the Clock Does Not Arrive atClock Inputs of All Flip-flops at The SameTime

D Qin

clk

D Qout

delay

D Qin

clk

D Q out

delay

Clock skew


85/104


Clock skew

H-clock tree used to minimize clock skew


86/104


H clock tree used to minimize clock skew

Dealing With Clock Problems


87/104


Dealing With Clock Problems

Use Only Dedicated Clock Nets for ClockSignals

Do Not Put Any Logic in Clock Nets



88/104


DEC

Q

SR

D

EC

Q

SR

D

EC

Q

SR

Three-StateControl

Output Path

Input Path

Three-State

Output

Clock

Set/Reset

Direct Input

RegisteredInput

FF Enable

FF Enable

FF Enable

IOB Functionality


89/104


IOB Functionality

IOB provides interface between thepackage pins and CLBs

Each IOB can work as uni- or bi-directional

I/O Outputs can be forced into High Impedance

Inputs and outputs can be registered

advised for high-performance I/O Inputs can be delayed


90/104


Timing simulation afterimplementation

Timing vs. functional simulation


91/104


g s u c o a s u a o

Simulation before synthesis is used to verifycircuit functionality and may differfrom the oneafter synthesis and implementation

Implementation tool generates SDF (StandardDelay Format) as a standard delay file and thenetlist for synthesized VHDL code with delays.

Generated netlist contains many componentinstantiation statements with library references

SDF file


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( DELAYFILE

( CELL( CELLTYPE XOR)

( INSTANCE U34.Z_VTX)

( DELAY( INCREMENT

( DEVICE 01(0.385090:0.385090:0.385090)(0.235177: 0.235177: 0.235177)

) ) ) )

A part of the SDF file is shown below.It indicates XOR gate delays (low to high, high tolow) of minimum, typical and worst case timing

Netlist from the synthesis tool


93/104


y

library IEEE;

library TC200G;use IEEE.std_logic_1164.all;

use TC200G.components.all;

entity CONSYN is

port( RSTn, CLK, D0, D1, D2, D3, D4, D5,

D6, D7 : in std_logic; FF_OUT,

COMB_OUT, FF_COMB_OUT : out

std_logic);end CONSYN;

architecture structural of CONSYN is

signal XOR8, FF, n70, n71, n72, n73, n74, n75,

n76, n67, n68, n69 : std_logic;

begin

FF_OUT n75,

D => XOR8, CP => CLK, CD => RSTn) ;

U30 : MUX21L port map( Z => n71, A => n67, B =>

n68, S => n69);

U31 : EN port map( Z => n67, A => D1, B => D0);

U32 : IV port map( Z => n68, A => n67);

U33 : EOP port map( Z => n69, A => D6, B => D7);

U34 : EO3 port map( Z => n70, A => D3, B => D2,

C => D4);

U35 : EO port map( Z => n72, A => D5, B => n70);U36 : EOP port map( Z => XOR8, A => n72,

B => n71);

U37 : FA1A port map( S => n73, CO => n76, CI => D3,

A => D2, B => FF);

U38 : EO3 port map( Z => n74, A => n68, B => n73,

C => D4);

U39 : EOP port map( Z => FF_COMB_OUT, A => D5,B => n74);

end structural;


94/104


Timing parameters

Timing parameters


95/104


definition units pipelining

delay

clock period

clock frequency

time pointpoint

rising edgerising edge

of clock

1clock period

ns

ns

MHz

good

good

latency

throughput

time inputoutput

#output bits/time unit

ns

Mbits/s

bad

good

Basic iterative architectureof the encryption/decryption unit


96/104


register

combinational

logic

one round

multiplexer

of the encryption/decryption unit

round keys

enc_dec

Basic iterative architecture: Timing


97/104


IN

OUT

M1

C1

M2

C2

M3

k clock_period

CLK

Latency

Increasing throughput using pipelining


98/104


round 1

round 16

. . .

Throughput =

target_clock_period

block sizetarget

clock

period,

e.g., 20 ns


99/104


Optimizationcriteria

Degrees of freedom and possible trade-offs


100/104


g p

speed area

power testability

Degrees of freedom and possible trade-offs


101/104

101ECE 545

Introduction to VHDL

speed

area

latency

throughput

g p


102/104

102ECE 545


Optimizationmethods

Speed optimization methods (1)


103/104

103ECE 545


better architecture (e.g., CLA vs. ripplecarry adder)

pipelining

parallel processing

optimization options of synthesis andimplementation tools

Speed optimization methods (2)


104/104

reducing fanout of control signals

better state encoding

registered outputs from the state machine

Date post:	05-Apr-2018
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