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EE141
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EE141 EECS141 1 Lecture #7
EE141 EECS141 2 Lecture #7
No lab next week Midterm on Fr Febr 19 6:30-8pm in 2060 Valley
LSB Review Session: TBA (most likely on Th)
EE141
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EE141 EECS141 3 Lecture #7
Last lecture Optimizing complex logic
Todays lecture Applying what we learned on memory
decoders Reading (Ch 6.2, 12.1,12.3)
EE141 EECS141 4 Lecture #7
Measure everything in units of tinv (divide by tinv):
p intrinsic delay (kg) - gate parameter f(W) LE logical effort (k) gate parameter f(W) f electrical effort (effective fanout)
Normalize everything to an inverter: LEinv =1, pinv =
tpgate = tinv (p + LEf)
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EE141 EECS141 5 Lecture #7
Compute the path effort: PE = (LE)BF Find the best number of stages N ~ log4PE Compute the effective fanout/stage EF = PE1/N Sketch the path with this number of stages Work either from either end, find sizes:
Cin = Cout*LE/EF
Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.
EE141 EECS141 6 Lecture #7
LE=10/3 1 LE = 10/3 P = 8 + 1
LE=2 5/3 LE = 10/3 P = 4 + 2
LE=4/3 5/3 4/3 1 LE = 80/27 P = 2 + 2 + 2 + 1
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EE141 EECS141 7 Lecture #7
Branching effort:
EE141 EECS141 8 Lecture #7
5 15
15
90
90
LE = FO = PE = SE1 = SE2 = PE =
1 90/5 = 18 18 (wrong!) (15+15)/5 = 6 90/15 = 6 36, not 18!
Introduce new kind of effort to account for branching:
Branching Effort:
Path Branching Effort:
Con-path + Coff-path Con-path
b =
bi B = Now we can compute the path effort: Path Effort: PE = LEFOB
Branching Example 1
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EE141 EECS141 9 Lecture #7
Select gate sizes y and z to minimize delay from A to B
Logical Effort: LE =
Electrical Effort: FO =
Branching Effort: B =
Path Effort: PE =
Best Stage Effort: SE =
Delay: D =
(4/3)3
Cout/Cin = 9
23 = 6
LEFOB= 128
PE1/3 5
35 + 32 = 21
Work backward for sizes:
5 z = 9C(4/3) = 2.4C
5 y = 3z(4/3) = 1.9C
Branching Example 2
EE141 EECS141 10 Lecture #7
Compute the path effort: PE = (LE)BF Find the best number of stages N ~ log4PE Compute the effective fanout/stage EF = PE1/N Sketch the path with this number of stages Work either from either end, find sizes:
Cin = Cout*LE/EF
Reference: Sutherland, Sproull, Harris, Logical Effort, Morgan-Kaufmann 1999.
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EE141 EECS141 11 Lecture #7
EE141 EECS141 12 Lecture #7
Physical Schematic
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EE141 EECS141 13 Lecture #7
All-inclusive model Capacitance-only
EE141 EECS141 14 Lecture #7
Interconnect and its parasitics can affect all of the metrics we care about Cost, reliability, performance, power consumption
Parasitics associated with interconnect: Capacitance Resistance Inductance
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EE141 EECS141 15 Lecture #7
From Magen et al., Interconnect Power Dissipation in a Microprocessor
SLocal = STechnology
SGlobal = SDie
EE141 EECS141 16 Lecture #7
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EE141 EECS141 17 Lecture #7
EE141 EECS141 18 Lecture #7
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EE141 EECS141 19 Lecture #7
EE141 EECS141 20 Lecture #7
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EE141 EECS141 21 Lecture #7
EE141 EECS141 22 Lecture #7
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EE141 EECS141 23 Lecture #7
EE141 EECS141 24 Lecture #7
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EE141 EECS141 25 Lecture #7
EE141 EECS141 26 Lecture #7
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EE141 EECS141 27 Lecture #7
EE141 EECS141 28 Lecture #7
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EE141 EECS141 29 Lecture #7
EE141 EECS141 30 Lecture #7
Use Better Interconnect Materials e.g. copper, silicides
More Interconnect Layers reduce average wire-length
Selective Technology Scaling (More later)
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EE141 EECS141 31 Lecture #7
Silicides: WSi 2, TiSi 2 , PtSi 2 and TaSi Conductivity: 8-10 times better than Poly
EE141 EECS141 32 Lecture #7
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EE141 EECS141 33 Lecture #7
EE141 EECS141 34 Lecture #7
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EE141 EECS141 35 Lecture #7
Analysis method: Break the wire up into segments of length dx Each segment has resistance (r dx) and capacitance (c dx)
EE141 EECS141 36 Lecture #7
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EE141 EECS141 37 Lecture #7 37
Model the wire with N equal-length segments:
For large values of N:
EE141 EECS141 38 Lecture #7
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EE141 EECS141 39 Lecture #7