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2Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Talk Outline Introduction
Buffer insertion Van Ginneken dynamic programming Extensions
Interconnect planning
3Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Simple Buffer Insertion ProblemGiven: Source and sink locations, sink capacitancesand RATs, a buffer type, source delay rules, unit wire resistance and capacitance
Buffer
RAT1
RAT2
RAT3RAT4
s0
4Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Simple Buffer Insertion ProblemFind: Buffer locations and a routing tree such that slack at the source is minimized
RAT2
RAT3RAT4
RAT1
s0
)},()({min)( 0410 iii ssdelaysRATsq
5Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Slack Example
RAT = 400delay = 600
RAT = 500delay = 350
RAT = 400delay = 300
RAT = 500delay = 400
slack = -200
slack = +100
6Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Elmore Delay
22211 )()( CRCCRCADelay
A B CR1 R2
C1 C2
7Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Common Approaches Iteratively insert buffers Closed-form solutions (2 pin nets) Dynamic programming Simultaneous constructions
8Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Van Ginneken’s Classic Algorithm
Optimal for multi-sink nets Quadratic runtime Bottom-up from sinks to source Generate list of candidates at each
node At source, pick the best candidate in
list
9Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Key Assumptions Given routing tree Given potential insertion points
10Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Generating Candidates
(1)
(2)
(3)
11Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Pruning Candidates
(3)(a) (b)
Both (a) and (b) “look” the same to the source.Throw out the one with the worst slack
(4)
12Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Candidate Example Continued
(4)
(5)
13Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Candidate Example ContinuedAfter pruning
(5)
At driver, compute which candidate maximizesslack. Result is optimal.
14Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Merging Branches
Right Candidates
Left Candidates
15Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Pruning Merged Branches
Critical
With pruning
16Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Van Ginneken Example
(20,400)
(20,400)(30,250)(5, 220)
WireC=10,d=150
BufferC=5, d=30
(20,400)
BufferC=5, d=50C=5, d=30
WireC=15,d=200C=15,d=120
(30,250)(5, 220)
(45, 50)(5, 0)(20,100)(5, 70)
17Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Van Ginneken Example Cont’d
(20,400)(30,250)(5, 220)
(45, 50)(5, 0)(20,100)(5, 70)
(5,0) is inferior to (5,70). (45,50) is inferior to (20,100)
(20,400)(30,250)(5, 220)
(20,100)(5, 70)(30,10)
(15, -10)
Pick solution with largest slack, follow arrows to get solution
Wire C=10
18Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Van Ginneken Recap
Generate candidates from sinks to source
Quadratic runtime Adding a buffer adds only one new candidate Merging branches additive, not multiplicative
Optimal for Elmore delay model
19Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Optimal Extensions Multiple buffer types Inverters Polarity constraints Controlling buffer resources Capacitance constraints Blockage recognition Wire sizing
20Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Multiple Buffer Types
(1)
(2)
Time complexity increases from O(n2) to O(n2B2) where B is the number of different buffer types
21Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Inverters
(1)
(2)
• Maintain a “+” and a “-” list of candidates• Only merge branches with same polarity• Throw out negative candidates at source
22Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Polarity Constraints Some sinks are positive, some negative Put negative sinks into “-” list
“-” list
“-” list “+” list
23Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Controlling Buffering Resources
3210
(C1, q1, 3), (C2, q2, 3), (C3, q3, 3)(C4, q4, 2), (C5, q5, 2)(C6, q6, 1), (C7, q7, 1), (C8, q8, 1)(C9, q9, 0)
(C1, q1), (C2, q2), (C3, q3) (C4, q4), (C5, q5) (C6, q6), (C7, q7), (C8, q8) (C9, q9)
Before, maintain list of capacitance slack pairs
Now, store an array of lists, indexed by # of buffers
Prune candidates with inferior cap, slack, and #buffers
24Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Buffering Resource Trade-off
-4000
-3000
-2000
-1000
0
1000
0 1 2 3 4 5 6 7
# of Buffers
Slac
k (p
s)
25Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Capacitance Constraints Each gate g drives at most C(g)
capacitance When inserting buffer g, check
downstream capacitance. If bigger than C(g), throw out candidate
Total cap = 500 ff
26Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Blockage Recognition
Delete insertion points that run over blockages
27Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Other Extensions Simultaneous driver sizing Modeling effective capacitance Higher-order interconnect delay Slew constraints Noise constraints
29Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Driver Sizing Driver behaves like buffer Pick driver with the best slack Implications upstream in timing graph Delay penalty for large input
capacitance
30Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
-Models Van Ginneken candidate: (Cap, slack)
C Cn
R
Cf
Replace Cap with -model (Cn, R, Cf) Total capacitance preserved: Cn + Cf = C R represents degree of resistive shielding
31Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Computing Gate Delay When inserting buffer, compute
effective capacitance from -modelCeff
Use effective instead of lumped capacitance in gate delay equation
Optimality no longer guaranteed
32Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Higher-order Interconnect Delay
Moment matching with first 3 moments Previously: candidate (-model, slack) Now: candidate (-model, m1, m2, m3) Given moments, compute slack on the fly Bottom-up, efficient moment computation Problem: guess slew rate
33Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Slew Constraints When inserting buffer, compute
slews to gates driven by buffer If slew exceeds target, prune
candidate Difficulty: unknown gate input
slew Slew 300 ps
Slew 350 ps?
34Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Noise Constraints Each gate has acceptable noise
threshold Compute cumulative noise for each
wire via Devgan noise metric Throw out candidates that violate
noise Not in production code
35Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Extensions Recap Multiple buffer types, including inverters Polarity constraints Controlling buffer resources Slew, capacitance, and noise constraints Blockage recognition Driver sizing Higher-order delay modeling Wire sizing
36Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Talk Outline Introduction Buffer insertion
Van Ginneken dynamic programming Extensions
Interconnect planning
37Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
What is the Problem? DSM timing closure
Squeeze buffers into tight spaces Alleviate hot spots, local wire congestion Getting worse
Handle wire congestion, buffering resources early
Acknowledge these constraints when floorplanning
38Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Which Floorplan Is Better?
Timing analysis worthless Interconnect synthesis, electrical
correction, routing, extraction Days to find answer
39Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Buffer Explosion
Past Present Number of buffers triples each
generation 800K buffers in 0.05 micron
technology
40Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Buffer Block Planning Create blocks between macros just for
holding buffers Adjust floorplan accordingly Computing size/#/location of blocks
Analyze 2-pin nets Find feasible regions Assign buffers with smallest region Combine buffers into blocks
41Optimization Strategies for Physical Synthesis and Timing ClosureICCAD-2001
Feasible Regions
feasible region