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Lab 3

Jorge Crichigno

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Half-adder

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Half-adder Testbench

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Waveform for half-adder simulation tb

stimulus

10 ns

testbench

ha

x_signal

y_signal

x

y

s

c

s_signal

c_signal

0

0

0

0

0

1

1

0

1

0

0

0

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Full-adder

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Full-adder Testbench

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Waveform for full-adder simulation tb

testbench

fa

x_signal

y_signal

x

y

s

c

s_signal

c_signal

z_signal z

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Process. Type of processes. Process with sensitivity list. Processwith wait statement. Example.

Sequential Signal Assignment Statement. Syntax. Examples.Pitfall. Intermediate value. Conceptual implementation

Variables. Syntax. Intermediate value. Example. Conceptualimplementation

Case statement. Syntax. Example. Multiplexor. Conceptual

implementation.

Lab 3 - Sequential Statements

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Process

Contains a set of sequential statements to be executed sequentially

The whole process is a concurrent statement

Can be interpreted as a circuit part enclosed inside of a black box

Two types: with sensitive list and with wait statement

Lab 3 - Sequential Statements

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A process with a sensitivity list

Syntax

process (sensitivity_list)

declarations;

begin

sequential statement;

sequential statement;

. . .

end process;

Lab 3 - Sequential Statements

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Lab 3 - Sequential StatementsProcess with sensitivity list.Interpretation: black box, indivisible circuit part.

Sensitivity list

The execution of the process is initiatedwhenever an event occurs on any of the signalsin the sensitivity listFor practical purposes, you can regards aprocess as a big concurrent signal

assignment statement

Note:

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Waveform for Example 1

000

011

0

00

0

10

0

00

0

10Process not

activated on B

change

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A Process With waitStatement

Process has no sensitivity list

Process continues the execution until a wait statement is reached and

then suspended Forms of wait statement:

waitonsignals;

waituntilboolean_expression;

waitfortime_expression;

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Sequential Signal Assignment Statement

Signal_name

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Sequential Signal Assignment Statement

If all assignments are within DELTA-delay, only the last

assignment takes effect. You can think as the signals are notupdated until the end of the process (i.e., it neverassumes anyintermediate value).

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Variable Assignment Statement

Variable_name := value_expression;Syntax:

Used inside processes. The assignment takes effect immediately.

Easy to understand, but not clear hardwaremapping!Use signal always you can; rely on variablesonly for the characteristics that cannot bedescribed by signals

Note:

0 tmpA

B

C

Conceptual

implementation

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Case Statement

Syntax: Example:

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Introduction to Multiplexers

Example of case statement: Multiplexor

S Y

0 I0

1 I1

Truth Table

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4-to-1 multiplexer VHDL Implementation

EntityENTITYmux4x1 IS

PORT(S : IN STD_LOGIC_VECTOR (1 downto 0);

D0 : IN STD_LOGIC;

D1 : IN STD_LOGIC;

D2 : IN STD_LOGIC;

D3 : IN STD_LOGIC;

Y : OUT STD_LOGIC);

ENDmux4x1;

ARCHITECTURE multiplexor4x1 OF mux4x1 IS

BEGIN

PROCESS(S, D0, D1, D2, D3)

BEGINCASE S IS

WHEN "00"=> Y Y