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Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g...

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Lectures 5: Seq. and Lectures 5: Seq. and comb logic comb logic comb. logic, comb. logic, statements, generics statements, generics TKT TKT-1212 Digitaalijärjestelmien toteutus 1212 Digitaalijärjestelmien toteutus Erno Salminen Erno Salminen Erno Salminen Erno Salminen Tampere Tampere university university of of technology technology Spring Spring 2012 2012 Spring Spring 2012 2012 Seq. logic D Q Comb. logic foo_r a_in b_in c_in n 1 n n logic Department of Computer Systems
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Page 1: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Lectures 5: Seq. and Lectures 5: Seq. and comb logic comb logic comb. logic, comb. logic, statements, genericsstatements, generics, g, gTKTTKT--1212 Digitaalijärjestelmien toteutus1212 Digitaalijärjestelmien toteutusErno SalminenErno SalminenErno SalminenErno SalminenTampere Tampere universityuniversity of of technologytechnologySpringSpring 20122012SpringSpring 20122012

Seq. logic

D QComb. logic

foo_ra_inb_in

c_in

n

1

n

nlogic

Department of Computer Systems

Page 2: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

AcknowledgementsAcknowledgementsProf. Pong . P. Chu provided ”official” slides

for the book which is gratefully aknowledgedg y g See also: http://academic.csuohio.edu/chu_p/

Most slides were made by Ari Kulmalay and other previous lecturers (Teemu Pitkänen,

Konsta Punkka, Mikko Alho…)

#2/55 Department of Computer Systems

Page 3: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

ContentsContentsComb and seq. logic from VHDLStatements of VHDLStatements of VHDLCommon pitfalls

#3/55 Department of Computer Systems

Page 4: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Recap: Combinatorial vs. sequential Recap: Combinatorial vs. sequential circuitcircuit Combinatorial circuit:

No internal state Sequential circuit:

With internal state Output is a function of

inputs only No latches/FFs

Output is a function of inputs and internal state

Synchronous design Described with

processes or concurrentstaments

y gstyle with DFFs Includes also comb.logic

Described withsta e tsprocesses

Comb. logic

Comb. logic

n n

#4/55 Department of Computer Systems

Page 5: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Concurrent vs. sequential Concurrent vs. sequential statements in HDLstatements in HDLstatements in HDLstatements in HDLMost programming languages are sequential

but digital logic operates is parallelg g p pHW designers need a bit different frame of

mind to take parallelism into accountpVHDL is a parallel language but some things

are better captured with sequentialdescriptionHence, there are 2 types of statements

1. Concurrent2. Sequential

#5/55 Department of Computer Systems

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Category1: Concurrent Category1: Concurrent statementsstatementsDefine interconnected blocks and processes

that jointly define the behaviour or structure of a design – inside the architecturea design – inside the architecture

Are executed in parallel and asynchronously with respect each others PROCESS COMPONENT INSTANTIATION GENERATE CONCURRENT SIGNAL ASSIGNMENT CONDITIONAL SIGNAL ASSIGNMENT SELECTED SIGNAL ASSIGNMENT CONCURRENT ASSERTION CONCURRENT PROCEDURE CALL BLOCK

All t t t t b l b l d#6/55 Department of Computer Systems

All concurrent statements can be labeled

Page 7: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Category2: Category2: SequentialSequential statementsstatementsExecuted in order in which they appearsCan be used inside processes, procedures

and functionsand functions SIGNAL ASSIGNMENT VARIABLE ASSIGNMENT IF CASE ASSERTIONLOOP LOOP

NEXT EXIT WAIT WAIT PROCEDURE CALL RETURN NULL

#7/55 Department of Computer Systems

NULL

Page 8: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Sequential Statements vs. LogicSequential Statements vs. Logic

Sequential VHDL statements do not necessarily represent synchronous

ti l di it l l i i itsequential digital logic circuits They can describe both combinatorial and

synchronous logic circuitssynchronous logic circuitsModeling combinatorial logic with sequential

statements:statements: Sensivity list of process statements must contain

all inputs used in VHDL statements Conditional & selected signal assignments (also

if and case statements) most cover all possible branches (to avoid inferring unintentional

#8/55 Department of Computer Systems

( glatches)

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Seq. statements: Seq. statements: IFIF Inside processes, procedures and functions only

Like in conventional programming languages Priority encoded (if tested first, then elsif, then else).

IF condition THENIF condition THENsequence of statements

[ ELSIF condition2 sequence of statements ]

[ ELSE[sequence of statements ]

END IF;

Example of incrementing and clipping values within ll dallowed range:

IF a > upper_limit_c THENa <= upper_limit_c;

ELSIF a < lower_limit_ca <= lower_limit_c;

ELSEa <= a+1;

END IF;

#9/55 Department of Computer Systems

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Example: Comb. Example: Comb. muxmux using IFusing IF---- Synthesis example: Multiplexer using IF statement--ENTITY ifmultiplexer ISENTITY ifmultiplexer IS

port (a, b, sel : IN STD_LOGIC;z : OUT STD_LOGIC);

END ifmultiplexer;p ;

ARCHITECTURE syn OF ifmultiplexer ISBEGIN – Syn

PROCESS (a, b, sel)BEGIN -- PROCESSIF (sel = ’1’) THEN

z <= b;ELSEELSE

z <= a;END IF;

END PROCESS;END syn;

#10/55 Department of Computer Systems

y ;

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Sequential Statements vs. Sequential Sequential Statements vs. Sequential LogicLogicgg The two basic types of synchronous

elements are D Q

1. D-type latch (level sensitive memory cell)2. D-type flip-flop (edge-triggered memory cell) D Q

ena

The main disadvantage of latches(instead of flip-flops) is that static timing

l i (STA) f th i d i it

clk

analysis (STA) of synthesized circuits canbe very complex Do not use latches! => Inferred latches Do not use latches! => Inferred latches

indicate very likely a bug They also complicate manufacturing tests

#11/55 Department of Computer Systems

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Sequential Statements vs. Sequential Sequential Statements vs. Sequential Logic (2)Logic (2)g ( )g ( ) Flip-flops are inferred by signal

assigment in a process that detectsassigment in a process that detectssome signal’s edge (using wait or if) Note! Assigning in reset branch creates DFF as g g

well, even if the clk’event branch does not touchthat signal

Example of rising edge detection:IF (clk’EVENT AND clk=’1’) THEN

statementsstatements...END IF;

D Qinput ports, assigned signals

#12/55 Department of Computer Systems

D Qstatementsput po ts,

signals,generics, constants

clk

assigned signalsand output ports

Page 13: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

ExampleExample: : SynchronoursSynchronours designdesign

Example: design a single rising-edge triggered D flip-flop

Process activated when there is a change in value f t lk

If reset is active

of reset or clk

No code before if

If reset was not active

Or after end if

#13/55 Department of Computer Systems

If reset was not active AND we have a rising edge in signal ‘clk’

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Designing Synchronous CircuitsDesigning Synchronous Circuits All signals and ports that are assigned a value in process

containing[ELS]IF (clk’EVENT AND clk=’1’) THEN[ ] ( )

(or similar) are implemented as registers! Note that a register consists of several flip-flops

This is because these assignments take place only at clock This is because these assignments take place only at clockedge This is exactly how the flip-flops work: they load the input

value on clock edgevalue on clock edge Explicit usage of flip-flop components is not recommended Many signal types can infer registers. Integers become

registers (32b) as well as std logic vectors and own definedregisters (32b) as well as std_logic_vectors and own definedtypes. A flip-flop is instantiated for each bit Integer ranges should be defined

#14/55 Department of Computer Systems

Integer ranges should be defined

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DesigningDesigning synchronoussynchronous circuitscircuits (2)(2)

Remember the concept of RTL designWith VHDL synchronous design style, this is y g y ,

actually just what you do Define what happens before a register and

where that data goes...ELSIF clk'event AND clk = '1' THEN -- rising clock edge

result r <= (a in XOR b in) + c in;result_r <= (a_in XOR b_in) + c_in;END IF;... Do this operation and move the

result to result registerInputs may come

D QComb.result_r

a_inb i

Inputs may comefrom registers orother comb logic, but example code

does not show

The code shows that result_r is a register, postfix

#15/55 Department of Computer Systems

D QComb. logicb_in

c_inwhere

g , p_r is meant for human reader

clk

Page 16: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

ExampleExample: : MultiplyMultiply--accumulateaccumulate, , stepstep 1 1 definedefine the the entityentityEntity is the same for all architecture variants

However, Clk and rst_n are ignored in combinatorial

entity mac isgeneric (d id h i 4)

Data width is parametrized, we’llreturn to this this…

data_width_g : integer := 4);

port (clk : in std_logic;rst n : in std logic;

4-1 downto 0 = 4 bits

rst_n : in std_logic;a_in : in std_logic_vector(data_width_g-1 downto 0);b_in : in std_logic_vector(data_width_g-1 downto 0);c_in : in std_logic_vector(data_width_g-1 downto 0);mac out : out std logic vector(data width g*2-1 downto 0)_ _ g _ ( _ _g ));

end mac;

D bl idth d t lti li ti4*2-1 = 7, 7 downto 0 = 8 bits

#16/55 Department of Computer Systems

Double width due to multiplication(in numeric_std, two 4-bit number addition results in 4-bit result, not 5-bit.)

Page 17: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

MAC: 3 MAC: 3 possiblepossible architecturesarchitectures1) Combinatorial circuit:

*A_inB in

M t+_

C_inMac_out

2) S h i it

*A_inB_in

Mac out

2) Synchronous circuit:

+C_inMac_out

D Q

3) Pipelined synchronous circuit:

*+

A_inB_in

Mac_outD Q

3) Pipelined synchronous circuit:

#17/55 Department of Computer Systems

+C_in

_D Q

D Q

Page 18: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

MAC: MAC: combcomb. . archarch*

A_inB in

Combinatorial circuit hasno flip-flops

+B_in

C_inMac_out

architecture rtl of mac is

begin -- rtl

b ( i b i i )mac_comb: process (a_in, b_in, c_in)variable result_v : unsigned(data_width_g*2-1 downto 0);

begin -- process mac_comb-- note that result_v does not depend on its previous value-- => this is safe usage of variable to beautify the codeg y

result_v := unsigned(a_in)*unsigned(b_in)+unsigned(c_in);mac_out <= std_logic_vector(result_v);

end process mac comb;

Could be combined

end process mac_comb;

end rtl;Multiplication precedes addition, but parentheses would make that

b i W d ’t

#18/55 Department of Computer Systems

more obvious. We don’t careabout overflow in the sum.

Page 19: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

MAC: MAC: synchsynch. . archarch Synchronous circuit with

single output flip-floparchitecture rtl of mac is

*+

A_inB_in

C_inMac_out

D Q

begin -- rtl

mac_sync : process (clk, rst_n)variable result_v : unsigned(data_width_g*2-1 downto 0);

begin -- process mac_combif rst_n = '0' then -- asynchronous reset (active low)mac_out <= (others => '0');

elsif clk'event and clk = '1' then -- rising clock edge Calculation insideresult_v := unsigned(a_in)*unsigned(b_in)+unsigned(c_in);mac_out <= std_logic_vector(result_v);

end if;end process mac_sync;

Calculation inside the ”clock region”

end rtl;A register is generated for mac_outsince:•It is a signal (port out)•It is assigned a value within the

Result_v is not implemented as register since

it i i bl th t d t

#19/55 Department of Computer Systems

gclock region• it is a variable that does not

depend on its previous value

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MAC: MAC: pipelinedpipelined *+

A_inB_in

Mac_outD Q

D Q

Pipelined version hastwo register stages

+C_in

D QD Q

architecture rtl of mac issignal mul_r : unsigned(data_width_g*2-1 downto 0);signal c_r : unsigned(data_width_g-1 downto 0);

begin -- rtl

Internal signals

mac_pipe : process (clk, rst_n)begin -- process mac_comb

if rst_n = '0' then -- asynchronous reset (active low)mac_out <= (others => '0');

elsif clk'event and clk = '1' then -- rising clock edgec_r <= unsigned(c_in);mul_r <= unsigned(a_in)*unsigned(b_in);mac_out <= std_logic_vector(mul_r + c_r);

end if;

Calculation inside the ”clock region”

end if;end process mac_pipe;

end rtl;

R i t i l t d f

The mul_r is updated in previous statement. However, signal values do not change until the next clock edge with the clock region (unlike variables).Therefore mac out functions correctly

#20/55 Department of Computer Systems

Registers implemented for each signal. Order of assigments doesnot matter here

Therefore, mac_out functions correctly as it uses mul_r(t) while the preceding statement produced mul_r(t+1).

Page 21: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

MAC: MAC: secondsecond pipelinedpipelined versionversion

A in

4) Pipelined Synchronous circuit without out-register:

* D Q architecture rtl of mac isA_inB_in

C_in

*+ Mac_out

D Q

D Q

architecture rtl of mac issignal mul_r : unsigned(data_width_g*2-1 downto 0);signal c_r : unsigned(data_width_g-1 downto 0);

begin -- rtl

mac_pipe : process (clk, rst_n)begin -- process mac_comb

if rst_n = '0' then-- Note that intermediate pipeline registers do -- not have to be nullified under reset

< ( th > '0')c_r <= (others => '0');mul_r <= (others => '0');

elsif clk'event and clk = '1’c_r <= unsigned(c_in);mul r <= unsigned(a in)*unsigned(b in);

Continous signal assignment to mac_out so it must not be reset

mul_r < unsigned(a_in) unsigned(b_in);end if;

end process mac_pipe;

mac_out <= std_logic_vector(mul_r + c_r);Mac_out moved out of the clockregion causes that no register

t d f it b t j t i

#21/55 Department of Computer Systems

end rtl;generated for it but just a wirecoming from an adder

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ExampleExample: : SignalSignal vsvs variablevariableP i t i d t l k d

architecture rtl of ac issignal x_r : integer;signal y_r : integer;signal z : integer;

Process is triggered at clock edge.Variable is updated instantly.Signal is updated just after the clock edge Simulator view:

g gbegin -- rtl

value: process (clk, rst_n)variable k_v : integer;

begin -- process valueg pif rst_n = '0' thenx_r <= 0;y_r <= 0;

elsif clk'event and clk = '1' thenk_v := to_integer(unsigned(a_in));x_r <= to_integer(unsigned(a_in));

y_r <= k_v + x_r; y_r(t) = k_v (t) + x_r(t), i.e. a_in(t)+a_in(t-1)

end if;end process value;

z <= y_r;

z <= y_r is a continuous assignment, happens instantly (not within the clock region)

Note: variables are not necessarily visible older simulator’s

#22/55 Department of Computer Systems

end rtl;: y

wave window! Debugging may be complicated…

Page 23: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Signal vs variable value update (2)Signal vs variable value update (2)architecture rtl of ac issignal x_r : integer;signal y_r : integer;signal z : integer;

Note that variable is usedwithin clock sensitiveprocessg g

begin -- rtl

value: process (clk, rst_n)variable k_v : integer;

begin -- process value

It’s value is updatedonly when there’s eventon clock (in simulator!)g p

if rst_n = '0' thenx_r <= 0;y_r <= 0;

elsif clk'event and clk = '1' then

However, whenimplemented, k_v is part of the comb. logic ”cloud” thatconstantly executesk_v := to_integer(unsigned(a_in));

x_r <= to_integer(unsigned(a_in));

y_r <= k_v + x_r;

constantly executes Short-hand notation for

part of the comb. logic I di t lend if;

end process value;

z <= y_r;

Immediate valueassignment

+ D Q

a_ink_v

#23/55 Department of Computer Systems

end rtl; + D QD Qx_r

Page 24: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Signal vs variable value update (3)Signal vs variable value update (3)architecture rtl of ac issignal x_r : integer;signal y_r : integer;signal z : integer;

architecture rtl of ac issignal x_r : integer;signal y_r : integer;signal z : integer;g g

begin -- rtl

value: process (clk, rst_n)variable k_v : integer;

begin -- process value

g gbegin -- rtl

value: process (clk, rst_n)

begin -- process valueg pif rst_n = '0' thenx_r <= 0;y_r <= 0;

elsif clk'event and clk = '1' then

g pif rst_n = '0' thenx_r <= 0;y_r <= 0;

elsif clk'event and clk = '1' then

equivalent

=k_v := to_integer(unsigned(a_in));x_r <= to_integer(unsigned(a_in));

y_r <= k_v + x_r;

-- var removedx_r <= to_integer(unsigned(a_in));

y_r <= unsigned(a_in) + x_r;

end if;end process value;

z <= y_r;

end if;end process value;

z <= y_r;

h h bl

#24/55 Department of Computer Systems

end rtl; end rtl;In this case, the variable is notvery useful, but used for demonstration purposes only.

Page 25: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Ex. (4): Ex. (4): SimSim vs. vs. realreal HWHWarchitecture rtl of ac issignal x_r : integer;signal y_r : integer;signal z : integer;

In HW:

Input changes and internalsignal k_v has the exactlythe same value.

g gbegin -- rtl

value: process (clk, rst_n)variable k_v : integer;

begin -- process valueg pif rst_n = '0' thenx_r <= 0;y_r <= 0;

elsif clk'event and clk = '1' thenk_v := to_integer(unsigned(a_in));x_r <= to_integer(unsigned(a_in));

y_r <= k_v + x_r; Timing of signals is the samei i l tiend if;

end process value;

z <= y_r;

as in simulation.

Note: simulator’s view does not fully match real world, although the results y_r and z are the

#25/55 Department of Computer Systems

end rtl;

g ysame!

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DetectingDetecting concurrentconcurrent and and sequentialsequential codecode

Concurrent:1. Sync_procbegin -- rtl y2. Comb_proc3. z <= y_r;

sync_proc: process (clk, rst_n)variable k_v : integer;

begin -- process sync_procif rst_n = '0’x_r <= 0;y_r <= 0;

elsif clk'event and clk = '1' thendy sequential

4. m_out <= ...;Sequential

k_v := to_integer(unsigned(a_in));x_r <= to_integer(unsigned(a_in));y_r <= k_v + x_r;

end if;end process sync_proc;

comb_proc: process (a_in, c_in)variable inter v : std logic;te

ctur

e bo

1. Sync_procinternals

2 Comb proc

variable inter_v : std_logic;begin -- process comb_procinter_v := a_in(0) and c_in(0);if inter_v = '1' thenres <= a_in xor c_in;

else res <= a_in;

end if;end process comb proc;

Arc

hit

sequential

2. Comb_procinternals

end process comb_proc;

z <= y_r;

m_out <= res when b_in(0) = '1' elsestd_logic_vector(to_unsigned(z, data_width_g));

end rtl;

#26/55 Department of Computer Systems

Quiz: which signals implement a register? A: x_r, y_r

Page 27: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

Generic parametersGeneric parameterspp

Department of Computer Systems

Page 28: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

GenericsGenerics Pass instance-specific information to an entity. Ability to parameterize models using generics. The values of generic parameters must be The values of generic parameters must be

computable at design time. Dynamic changes are not possible

Use generics instead of hard coded values in Use generics instead of hard-coded values in interface!

Example:

entity mac isgeneric (data_width_g : integer := 4);

t (port (clk : in std_logic;rst_n : in std_logic;a_in : in std_logic_vector(data_width_g-1 downto 0);b_in : in std_logic_vector(data_width_g-1 downto 0);c_in : in std_logic_vector(data_width_g-1 downto 0);mac out : out std logic vector(data width g*2 1 downto 0)

#28/55 Department of Computer Systems

mac_out : out std_logic_vector(data_width_g*2-1 downto 0));

end mac;

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Generics (2)Generics (2)

architecture testbench of tb_mac is

component macgeneric (

begin -- testbench

-- component instantiationclar

atio

n

dygeneric (data_width_g : integer :=4);

port (clk : in std_logic;rst_n : in std_logic;a_in : in std_logic_vector(data_width_g-1 downto 0);b_in : in std_logic_vector(data_width_g-1 downto 0);c in : in std logic vector(data width g-1 downto 0);

pDUT: macgeneric map (data_width_g => data_width_c)

port map (clk => clk,rst_n => rst_n,a_in => a_to_mac,m

pone

nt d

ec

ectu

re b

od

c_in : in std_logic_vector(data_width_g 1 downto 0);mac_out : out std_logic_vector(data_width_g*2-1 downto 0));

end component;

-- values to assign for component genericsconstant data_width_c : integer := 8;

-- Internal signals to/from DUT

b_in => b_to_mac,c_in => c_to_mac,mac_out => mac_result);

...

end testbench;

Com

Arc

hit

Internal signals to/from DUTsignal clk : std_logic;signal rst_n : std_logic;signal a_to_mac : std_logic_vector(data_width_g-1 downto 0);signal b_to_mac : std_logic_vector(data_width_g-1 downto 0);signal c_to_mac : std_logic_vector(data_width_g-1 downto 0);signal mac_result : std_logic_vector(data_width_g*2-1 downto 0);

Component instantiation. Define the value of generic(s) and attach the interface signals

Local constant

We define the signals th t tt h d t th

Note: By using generic, this same code for mac can be used for

any data_width_g and it works without modifications If i l i t ifi d i th i t ti ti th

#29/55 Department of Computer Systems

that are attached to the component in instantiation

If generic value is not specified in the instantiation, the default is used (in this case 4, as shown in previous slide’s entity declaration). Danger danger.

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Summary of genericsSummary of genericsThey are great! Use them.

#30/55 Department of Computer Systems

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Other statementsOther statementsOther statementsOther statements

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Statements: AssertionStatements: Assertion Checks a specific condition and gives message. Simplify checking in simulation (not synthesizable) Also as checkers inside the module Also as checkers inside the module

E.g. If we assume that always input a < 10, we put an assertion

Use assertions to verify the initial assumptions (e.g. generic value range, input value range, known properties and relations)!

General form:ASSERT condition [REPORT s expr] [SEVERITY sl expr]_ p _ p

Examples:ASSERT word_count_g < 10REPORT “Parameter word count too big. (word_count_g > 9)”SEVERITY warning;

NOTE: Output device for report is implementation dependent.

Concurrent assertion is similar to sequential assertion

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Concurrent assertion is similar to sequential assertion it can be used inside or outside a process in a similar manner

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Statements: Statements: WAITWAIT Inside processes, procedures and functions only

Stops execution of a process or procedureGeneral form:

WAIT [on sensitivity_list] [UNTIL b_expr] [FORt_expr]

Examples:pWAIT ON a;WAIT UNTIL a = ‘1’;WAIT FOR 10 ns;WAIT ON a UNTIL b = ‘1’ FOR 100 ns;;WAIT UNTIL Clk’EVENT AND Clk = ‘1’;

Another way to do clock-triggered process y gg p(not recommended)Reserve usage for testbenches only

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Statements: Statements: CASECASE Inside processes, procedures and functions only

All possible choices must be considered or the last choice must contain others clause

CASE expression ISpWHEN choice1 =>

statementsWHEN choice2 =>

statementsWHEN others =>

statementsEND CASE;

Example problem with DesignCompiler synthesis tool (from Synopsys):synthesis tool (from Synopsys): “Error: All possible string values of selector type not

covered by choices.” signal sel : std logic;signal sel : std_logic;...

CASE sel ISWHEN “0” => result <= a;WHEN “1” => result <= b;

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WHEN 1 > result < b;END CASE;

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Statements: Statements: CASECASE (2)(2) Inside processes, procedures and functions only

Example:CASE state IS

WHEN “000” =>output <= 0;

WHEN “001”=>output <= 1;

WHEN “010”=>output <= 2;

WHEN “011”=>output <= 3;

WHEN OTHERS =>output <= 4;

END CASE;

Use h th > with caseUse when others => with case Otherwise, some tools want you to specify also

what happens with other std_logic_values, e.g.

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”X11”, ”1Z1,” ”WHH”, ”UUU”

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Statements: Statements: LOOPLOOPA way to represent iteration. 3 different forms

possible.General form:General form:

[label:] [iteration_scheme] LOOP{sequential_statement}

END LOOP [label];

E lExamples:FOR i IN 10 DOWNTO 0 LOOPa(i) := b(i);

END LOOP;

WHILE i < 10 LOOP

Preferred loops •The bounds are easily seen

Inside processes, procedures and functions

WHILE i < 10 LOOPa(i) := a(i) + 1;i := i+1;END loop;

LOOPclock <= not clock;

i i /2

Also in concurrent

wait for ClockPeriod/2;IF error = ‘1’ THEN

EXIT; END IF;

END LOOP;

part

example of clock generation in simulation testbenches

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Statements: Statements: EXITEXITExit statement is used to jump out from loops

during execution and complete current loop Problem: the exit points in arbitrary locations make Problem: the exit points in arbitrary locations make

the code very hard to comprehend later Note! Hardware implemented for worst case anyway You cannot have any speed advantage with early You cannot have any speed advantage with early

exists or suchExample:

outer_loop:FOR j IN 0 TO data_width_g-1 LOOPinner_loop:FOR i IN 0 TO n_cpu_c-1 LOOP

IF exit_cond = true THENEXIT inner_loop;

ELSEcounter :=counter +1;

END IF;END LOOP inner_loop;

END LOOP outer_loop;

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Statements: Statements: NEXTNEXT

Next statement is used to stop execution of statements in the loop for this iteration and pgo to the next iteration Same obfuscation problem as with exit

Example:outer_loop:FOR j IN 0 TO data_width_g-1 LOOP

inner loop:FOR i IN 0 TO n cpu c-1 LOOPe _ oop: O 0 O _cpu_c OOIF next_cond = true THENNEXT inner_loop;

ELSEcounter := counter +1;counter := counter +1;

END IF;END LOOP inner_loop;

END LOOP outer_loop;

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Statements: Statements: NULLNULL

Performs no action. Is used to explicitly show that no action is to be p y

performed when certain conditions are true. Example

CASE state ISCASE state ISWHEN “000” =>output <= 1;

WHEN “001”=>output <= 2;

WHEN “010”=>output <= 3;

WHEN OTHERS =>WHEN OTHERS >NULL;

END CASE;NOTE: be careful with NULL statement. In

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asynchronous/combinatorial processes it may generate latches (prob. unintentional)

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Statements: Statements: GENERATEGENERATE Very important for hierarchical designGenerate statement makes possible to replicate

(FOR GENERATE)(FOR GENERATE) Component instantiations Concurrent statements

Also conditional replication/instantiation is possible (IF GENERATE) Whether a component is instantiated or not Whether a component is instantiated or not Whether concurrent statement/process is implemented or

not Note that there is no ELSE GENERATE Note that there is no ELSE GENERATE

Example: DMA – direct memory access Parametrized amount of DMA channels

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Real code example from a research project

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Idea of DMA componentIdea of DMA component

DMA copies data to/from dual-port memory from/to network Much faster than CPU-contolled communication

CPU provides: src addr, dst addr, data amount, and command

Example TX: Send 100 bytes starting from 0x100 in DPRAM to network addr 0x5000

Example RX: If there’s data coming from network with addr0xF000, put it to addr on 0x164 in DPRAM. Interrupt CPU when 50 bytes have been received.

There can be multiple RX transfers (=channels) pending

CPU d Mdual-port RAM

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DMA Network IF Networkinstr.memoryrxc rxc rxc…

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Example of forExample of for--generate componentgenerate component-- Componentchannels : for i in 0 to n_chans_g-1 generate

n2h2_rx_chan_1 : n2h2_rx_changeneric map ( Channel 0ta

_wid

th

= 0

_add

r_p_

hi_g

Parameters:

Mem_addr_r(0)…

HW: Ports:

data_width_g => data_width_g,id_g => i,...addr_cmp_hi_g => hibi_addr_cmp_hi_g)

port map (clk > clk

Channel 0

Channel 1

Dat Id

hi

bi_

cmp…

Dat

a_w

idth

Id =

1hi

bi_a

ddr_

cmp_

hi_g

Irq_chan_r(0)

Mem_addr_r(1)

Irq_chan_r(1)

clk => clk,rst_n => rst_n,avalon_addr_in => mem_addr_r(i),...irq_out => irq_chan_r(i));

ta_w

idth

d =

ans_

g-1

_add

r__h

i_g Mem_addr_r

(n_chans_g-1)…… Channel );

end generate channels;

Dat Id

n_ch

ahi

bi_

cmp_

Irq_chan_r(n_chans_g-1)

Hardware parameterized with generics, same ”base” for all In example, for each channel has

…n_chans_g-1

Different identifier id_g Same signal widths data_width_g and addr_cmp_hi_g

I/Os can be mapped to different signals Outputs must always be mapped to different signals!

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In example, for each channel has Different mem_addr_r and irq_chan_r (std_logic_vector position in 2D-array) Same clk and rst_n

Page 43: Lectures 5: Seq. and comb logic comb. logic, statements… · comb logic comb. logic, statements,,g generics ... The main disadvantage of latches (instead of flip-flops) is that static

ForFor--generategenerate Note that the generic parameters can be result of a

function, from a table etc Very powerful Very powerful Statically computed values, no dynamic parameters

i_nios_agent : hibi_wrapper_r4generic map (

id g => get prior(i),

-- purpose: To determine proper relative frequencies -- depending on the syncmode

id_g > get_prior(i),-- …

base_id_g => 2**id_width_c-1,id_width_g => id_width_c,addr_g => get_addr(i),rel_bus_freq_g => determine_clk_freq(true,

fifo sel g bus freq c)

function determine_clk_freq (constant device_is_bus : boolean;constant syncmode : integer range 0 to 3;constant frequency : integer)return integer is

begin -- determine clk freqfifo_sel_g, bus_freq_c),rel_agent_freq_g => determine_clk_freq(false,

fifo_sel_g, cpu_freq_c),prior_g => get_prior(i),arb_type_g => arb_type_c(i),fifo_sel_g => fifo_sel_g,inv addr en g > 0

begin determine_clk_freqcase syncmode is

when 1 =>--asyn fastif device_is_bus then

return bus_freq_c;elseinv_addr_en_g => 0,

-- …)

elsereturn hibi_sync_freq_c;

end if;when others =>

--syncreturn frequency;

d

a) Generic value determined with function Get_prior(i)

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end case;return 0;

end determine_clk_freq;

Determine_clk_freq(..)b) Generic value determined with table

Arb_type_c(i)

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Example of forExample of for--generate statementgenerate statementtype chan_addr_array is array (n_chans_g-1 downto 0) of std_logic_vector(addr_width_g-1 downto 0);type chan_be_array is array (n_chans_g-1 downto 0) of std_logic_vector(be_width_c-1 downto 0);signal current_mem_addr_r : chan_addr_array;signal current_be_r : chan_be_array;type chan_addr_switched is array (addr_width_g-1 downto 0) of std_logic_vector(n_chans_g-1 downto 0);type chan be switched is array (be width c-1 downto 0) of std logic vector(n chans g-1 downto 0);

-- STATEMENT (example: transpose)ava temp: for i in 0 to n chans g-1 generate

type chan_be_switched is array (be_width_c-1 downto 0) of std_logic_vector(n_chans_g-1 downto 0);signal avalon_addr_temp : chan_addr_switched;signal avalon_be_temp : chan_be_switched;

Browse through n_chans_g values (i)

ava_temp: for i in 0 to n_chans_g 1 generate

j: for j in 0 to addr_width_g-1 generateavalon_addr_temp(j)(i) <= current_mem_addr_r(i)(j);

end generate j; Browse through dd id h l (j)k: for k in 0 to be_width_c-1 generate

avalon_be_temp(k)(i) <= current_be_r(i)(k);end generate k;

end generate ava_temp;

addr_width_c values (j)

Browse through be_width_c values (k)

E.g. bit 0,2 to position 2,0 etcThen we can use or reduce

0 0 11 1 1

001

111

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Then we can use or_reduce 1 1

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SubprogramsSubprogramsVariables inside subprograms are localVariables are valid only during subprogram

executionexecutionContain sequential statementsFunctions:

can return one argument (can be compound type) all parameters are input parameters

FUNCTION n one bits(vec : BIT VECTOR) RETURN INTEGER IS_ _ _VARIABLE tmp : INTEGER;

BEGINtmp := 0;FOR i IN vec’RANGE LOOPIF vec(i) = ‘1’ THENtmp := tmp+1;

ELSEtmp := tmp;

END IF;END LOOP;RETURN tmp;

END n one bits;

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_o e_b ts;

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Subprograms (2)Subprograms (2)Procedures: can contain several input, output and inout

parameters

PROCEDURE n_one_bits (SIGNAL vec : IN BIT_VECTOR;VARIABLE int : OUT INTEGER) ISVARIABLE int : OUT INTEGER) IS

BEGINint := 0;FOR i IN vec’range LOOP IF vec(i) = ‘1’ THENIF vec(i) 1 THENint := int+1;

ELSEint := int;

END IF;END IF;END LOOP;

END n_one_bits;

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Procedure and function Call and ReturnProcedure and function Call and Return Procedure and function call statements:

procedure_name([actual parameters]);

Parameters can be positional or named associationmyproc1(formal1 => ‘1’,

formal2 => ”111”,formal3 => 1);

myprocedure3; --No parametersmyprocedure3; --No parameters

-- Avoid positional assignment:myproc1(my_signal,my_variable,1);

RETURN statement completes execution of innermostRETURN statement completes execution of innermost procedure or function

RETURN statement can be used only in body of procedure or functionp

ExamplesRETURN(“1111”);

RETURN

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RETURN;

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Simple mistakes one usually Simple mistakes one usually doesdoesdoes…does…

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VHDL PitfallsVHDL Pitfalls1. Identifiers

VHDL isn’t case sensitive (e.g. Input and input are the same)the same) (But some tool’s are…)

2. Misspelled If statement ELSIF written as ELSE IF ELSIF written as ELSE IF

3. Wrong string delimiters ‘0001’ instead of “0001”, or “0” instead of ‘0’

4. Misused reserved words reserved words used as object names: IN, OUT,

BUFFER, AND, NAND, OR, , , 5. Incomplete case statement

VHDL requires all conditions to be presented

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VHDL Pitfalls (2)VHDL Pitfalls (2)6. Expression evaluation following operations have equal precedenceAND, OR, NAND, NOR, XOR

following expression is illegala OR b AND c

example of correct expressiona OR (b AND c)

7. Signal assignment from multiple sources E.g. signal is reset in sequential process, but it is

assigned outside the processassigned outside the process Define only one driver for a signal!

A process, a concurrent statement …

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Three-state/Weak logic are exceptions at chip I/O

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Typical mistakes with syntaxTypical mistakes with syntax Signal assignment is <=, variable assignment :=

Depends on the object on the left hand side (signal <= variable, variable := signal)

Entity ports and generic declarations Lines end with ”;” except the last one is left without ”;”

Component instantiationp Assignments end with comma, except the last one is

without comma Mapping symbols points to right: ”=>”

n2h2_rx_chan_1 : n2h2_rx_changeneric map (

data_width_g => data_width_g,...addr_cmp_hi_g =>

hibi_addr_cmp_hi_g)port map (

clk => clk,rst_n => rst_n,

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_ _avalon_addr_in => mem_addr_r(i),...irq_out => irq_chan_r(i));

No comma allowed

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Mistakes in sim. vs. synthesisMistakes in sim. vs. synthesis

The process sensitivity list is incomplete! May hide bugs in the designy g g Synthesis ignores sensitivity list but simulation

relays on its completeness Always use compile option –check_synthesis

Using non-synthesizable structures ord t tdatatypes

E.g. Using don’t care-operator:E h ”1 ” E.g. when ”1--” => …

May simulate well (Modelsim supports) but doesnot synthesize!

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not synthesize!

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Top 20 Errors in VHDLTop 20 Errors in VHDL This is a list of the most common VHDL errors. The

Top 10 account for about 40% of all errors. The Top 20 account for about 60% of all errors.p

Source: Doulous VHDL Golden reference guide

!!

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VHDL Pitfall: NullVHDL Pitfall: Null--Statement in Statement in CASECASE

---- Null statement in case statement-- at combinatorial processat combinatorial process-- produces latch in synthesis to hold the last value.--ENTITY null_statement IS

PORT (l (1 0)sel : IN STD_LOGIC_VECTOR(1 DOWNTO 0);

output : OUT STD_LOGIC);END null_statement;ARCHITECTURE example OF null_statement ISBEGIN -- Example

PROCESS (sel)BEGIN -- PROCESS

CASE sel ISWHEN "00" => output <= ’0’;WHEN "10" => output <= ’1’;WHEN 10 => output <= 1 ;WHEN OTHERS => NULL;

END CASE;END PROCESS;

END example;

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SummarySummaryComb logic described with concurrent

statements and processes. Seq. logic onlyp q g ywith processesGenerics, if-generate, for-generate and g g

assertions are greatLoop bounds, signal widths, signals slicingg g g

indices, and generic values must be knownat compile-time (=synthesis-time)

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