Lee et al. [45] Date of Patent: Dec. 8, 1998 - prsmip.com · Lee et al. [45] Date of Patent: Dec....

US005 848000A

United States Patent [19] [11] Patent Number: 5,848,000 Lee et al. [45] Date of Patent: Dec. 8, 1998

[54] FLASH MEMORY ADDRESS DECODER 5,485,423 1/1996 Tang et a1. ............................ .. 365/185 WITH NOVEL LATCH STRUCTURE

[75] Inventors: Peter W. Lee, Saratoga, Calif.; Hsing-Ya Tsao; Fu-Chang Hsu, both of Taipei, Taiwan

[73] Assignee: Aplus Flash Technology, Inc., Santa Clara, Calif.

[21] Appl. No.: 819,323

[22] Filed: Mar. 18, 1997

Related US. Application Data

[63] Continuation-in-part of Ser. No. 624,322, Mar. 29, 1996, Pat. NO. 5,646,890, Ser. NO. 645,630, May 14, 1996, Pat. NO. 5,687,121, Ser. NO. 676,066, Jul. 5, 1996, Ser. NO. 726,670, OCL. 7, 1996, Pat. NO. 5,682,350, and Ser. NO. 779,765, Jan. 7, 1997, abandoned.

[51] Int. Cl.6 ................................................... .. G11C 16/06

[52] US. Cl. ............................... .. 365/185.23; 365/189.04

[58] Field of Search ....................... .. 365/18523, 185.33, 365/230.06, 189.04, 230.03, 185.11

[56] References Cited

U.S. PATENT DOCUMENTS

4,599,708 7/1986 Schuster ........................... .. 365/189.04

5,077,691 12/1991 Haddad et al. ..... .. 365/218

5,233,565 8/1993 Wang .............. .. 365/230.06 5,337,281 8/1994 Kobayashi et al. ..... .. 365/218

5,361,343 11/1994 Kosonocky et al. 365/189.04 5,369,619 11/1994 Ohba ............... .. 365/230.06

5,416,738 5/1995 Shrivastava ...... .. 365/185

5,469,384 11/1995 Lacey ............................... .. 365/185.13

m WORDLINE DECODER

xT1]'-]xTn 208a —> BLOCK1, WORDLINE1

202 — 130a — XD1 ORDLINE BLOCK’I, WORDLINEZ/

SELECT ; -

CIRCUIT ' '

—-> BLOCK‘I, WORDLINEn

I"I w —> 510cm, WORDL|NE1

BLOCK XDz WORDLINE_’ 510cm, WORDLINEZ 13gb DECODER SELECT : - /

CIRCUIT ' '

—> BLOCK 2, WORDLINE n

I I m —» BLOCK m, WORDL|NE1

XDm ORDL|NE—' BLOCKm, WORDLINEZ 130C SELECT ' ' -/

CIRCUIT '

BLOCKm, WORDLINEn

Primary Examiner—Tan T. Nguyen Attorney, Agent, or Firm—Flehr Hohbach Test Albritton & Herbert LLP

[57] ABSTRACT

A ?ash memory address decoder includes a plurality of voltage terminals to receive a plurality of voltages, an address terminal to receive a plurality of address signals and a procedure terminal to receive a procedure signal. A block decoder is coupled to the address terminal and con?gured to decode a portion of the address signals to provide a block select signal. A Wordline decoder is coupled to the address terminal and con?gured to decode a portion of the address signals to provide a Wordline select signal. A Wordline selector circuit is coupled to the block decoder and the Wordline decoder and con?gured to receive the block select signal and the Wordline select signal and to activate addressed Wordlines, Where the Wordline selector is con?g ured to selectively activate addressed Wordlines in the ?ash transistor array and to provide at least tWo different opera tional voltages simultaneously on different Wordlines in the ?ash transistor array to accomplish a predetermined proce dure responsive to the procedure signal. In one embodiment, a the address decoder includes a latch structure that latches addressed Wordlines and provides operational voltages to the Wordlines. In another embodiment, the block decoder and Wordline decoder include latch structures that latch the block select signal and the Wordline select signal to provide operational voltages to the Wordline selector. Advantages of the invention include high accuracy and ?exibility to read, erase and program the ?ash memory.

38 Claims, 19 Drawing Sheets

LOGICAL BLOCK 1

' 0100161‘, ‘VIII: '1' '

BLOCK 1, WL 2

SELECT BLOCK 1, WL a CIRCUIT

BLOCK 1, WL 4 .

.

BLOCK 1, WL n

LOGICAL BLOCK 1

.........

E BLOCK m, WL 1 l

BLOCK m, WL 2

SELECT CIRCUIT

BLOCK m, m 3

BLOCK m, WL 4 O

-

.

BLOCK m, WL n

U.S. Patent Dec. 8, 1998 Sheet 1 0f 19

SELECTED

+ LV

DETECT VT MAX. RAMP

FOR OPTIMIZING FROM GND ERASE CONDITION To + W

GND

FIG.1A

FLOATING

OPTIMAL OPTIMAL ERASE _Hv —I| CONDITION

+ MV

FIG.1B

+ LV

DETECT VT MIN. RAMP OF OVER-ERASED FROM -Hv _I CELLS TO GND

GND FIG.1C

5,848,000

DESELECTED

+LV/GND

GND

GND

FLOATING

GND

+MV/GND

+LV/GND

GND

GND

U.S. Patent Dec. s, 1998 Sheet 2 0f 19

SELECTED

+ LV

ERASE-VERIFY

(4) CONDITION V9(EV) GND

F|G.1D

+ MV

OPTIMAL

(5) NEGATIVE-VT (finch/‘AL PROGRAM

CONDITION GND

F|G.1E

+ LV

(6) NEGATIVE-VT PROGRAM-VERIFY Vg(|\|p) _|| CONDITION

GND

5,848,000

DESELECTED

+ LV/GND

GND

GND

+ MV/GND

GND

GND

+ LV/GND

GND

GND

U.S. Patent Dec. s, 1998 Sheet 3 0f 19 5,848,000

SELECTED DESELECTED

+ LV + LV/ GND

DETECT VT MIN. RAMP

(7) FOR OPTIMIZING FROM GND GND PROGRAM TO + W

CONDITION GND GND

F|G.1 G

+ W + MV / GND

OPTIMAL OPTIMAL GND/

PROGRAM + W

CONDITION GND GND

F|G.1H

+LV/GND +LV/GND

POSITIVE-VT

(9) PROGRAM-VERIFY V9(PP) GND CONDITION

GND GND

F|G.1| '

U.S. Patent Dec. s, 1998

SELECTED

(1) DETECT VT MAX. FOR OPTIMIZING ERASE CONDITION

+ LV RAMP FROM ONO

To + MV GND

F|G.2A

(2) OPTIMAL ERASE

CONDITION FLOATING

OPTIMAL _ Hv —|l

+ MV

F|G.2B

(3) DETECT VT MIN. OF OVER~ERASED CELLS

+ LV

RAMP

FROM -HV TO ONO

ONO

FIG.2C

Sheet 4 0f 19

DESELECTED (POSITIVE VT)

ONO

GND

FLOATING

GND

+MV/GND

+LV/GND

ONO

GND

5,848,000

DESELECTED (NEGATIVE VT)

+LV/GND

AI GND

FLOATING

—||

GND

U.S. Patent

ERASE-VERIFY CONDITION

OPTIMAL NEGATIVE-VT

) PROGRAM CONDITION

NEGATIVE-VT

Dec. 8, 1998

SELECTED

V9(EV) GND

FIG.2D

OPTIMAL + MV

(6) PROGRAM-VERIFY CONDITION

GND FIG.2F

Sheet 5 0f 19

DESELECTED (POSITIVE VT)

+LV/GND

IQ GND

+MV/GND

GND

GND

GND

GND

5,848,000

DESELECTED (NEGATIVE VT)

+LV/GND

—II GND

+MV/GND

GND

—II GND


SELECTED DESELECTED (POSITIVE VT)

+ LV + LV / GND

DETECT vT MIN. RAMP

FOR OPTIMIZING FROM GND GND PROGRAM TO + Mv

CONDITION GND GND FlG_2G

+ Mv + Mv / GND

OPTIMAL GND ,

POSITIVE-VT OZII'MAL OPTIMA|__|| PROGRAM + +HV

CONDITION GND GND

FIG.2H

+LV/GND +LV/GND

POSITIVE-VT

PROGRAM-VERIFY V9(PP) GND CONDITION

GND GND FIG.2|


0 START /5

‘

ERASE /52

N0 54 PASS ERASE

VERIF

PASS V

PROGRAM /56 LOW

HIGH

U.S. Patent Dec. s, 1998 Sheet 8 0f 19

START J50

i 72 _ Detect Positive Vt max.

i Erase #52

ii Detect negative Vt min. J4 (most negative Vt)

Program negative Vt J56 to low positive Vt

. . . 82 _

Detect positive Vt min. -/

i Program positive Vt 60 to high positive Vt "J

Complete all

END

selected addresses ?

5,848,000

Erase Procedure

Program Low Vt Procedure

Program High Vt Procedure

FIG.3B


E WORDLINE DECODER

XT1 " XTn

208a = BLOCK 1, WORDLINE 1 202 130a — X01 WORDLINE = BLOCK 1, WORDLINE 2 -/

‘ SELECT ; ;

CIRCUIT ' '

> BLOCK ‘I, WORDLINE n

V. ‘V 20gb = BLOCK 2, WORDLINE 1

BLOCK X02 WORDLINI; = BLOCK 2, WORDLINE 2 13gb DECODER ‘ SELECT : ; /

CIRCUIT ' '

> BLOCK 2, WORDLINE n

208m ‘ BLOCK m, WORDLINE 1

XDnlWORDUNE BLOCK m, WORDLINE 2 130C SELECT E : CIRCUIT '

BLOCK m, WORDLINE n

FIG.4


,[| LOGICAL BLOCK1 ' /

208a HE EBLOCK1, WL1 I

H[ BLOCK1,WL2 WORDLINE _

g9; ‘ SELECT M BLOCK1, WL3 CIRCUIT

Hr BLOCK1 WL4

HL]_ I O

O

__r' . HLL BLOCK 1, WL n

BLOCK 0 O O

DECODER O O O

O O

15‘ LOGICAL BLOCK1 ' /

208m H FB'L'OEK'IHW'L‘I'E

H BLOCK m, WL 2 WORDLINE :

= SELECT H BLOCK m, WL s

CIRCUIT _j BLOCK m, WL 4

O

O

O

I] BLOCK m, WL n

IILL

FIGURE 48


212a LATCH "

OPTIO

206a XT(m) 208a \ V

D

OPT'O = SELECT ———>|| CIRCUIT S

A

XTB(m)

LATCH /214a OPTIO

LATCH OPTION:

(1)No latch (2) Single (multiple-select) latch (3) Double (three-output-voltage) latch


204 WORDLINE DECODER A"

V ... V

212n 212a\ LATCH LATCH J

OPTIO OPTIO

202 XT1 Ll ‘—] XTn \ IQ‘,

206a 208a ~ BLOCK1, WL1

LATCH X01 WORDLINE _ BLOCK1, WL2 130a —>OPT|O SELECT : ; /

CIRCUIT '

~ BLOCK1, WLn

206b 208b BLOCK 2, WL1 13Gb

LATCH X02 WORDLINE BLOCK2, WL2 / BLOCK > ; DECODER OPT'O SELECT ' :

CIRCUIT '

~ BLOCK 2, WLn

206m 208m BLOCK m, WL1

LATCH )(Dm WORDLINE _ BLOCK m, WL 2n “*opno _"’ SELECT : : j3°m

CIRCUIT -

BLOCK m, WLn A

XTB1l-—— L‘XTBn 214a \ LATCH - LATCH /214n

OPTIO OPTIO A u L

210 WORDLINE DECODER Br’


365x EVNEX A5 5; £8; 5%; A: E; A: Ex 208a

' BLOCK 1, WL 1

' BLOCK 1, WL n

208m

I’ BLOCK m, WL 1

' BLOCK rn, WL n

I-——————-‘

EVE; A58? A5 5? £8? 5%; 3 :Ex


WORDLINE DECODER A WORDLINE DECODER C

212a1 212n1 212a2 212n2 \LATCH LATCH’ \LATCH LATCH/

XT1|— XTn XT1 [- —————J XTn ‘[- IV ‘pd!

20631 20881 ‘ BLOCK 1, WL 1 = 20882 20632

SE'— 1 : : SEL L LATCH

‘ BLOCK 1, WL n 4 All I. M M u 1

206b1 2O8b1 : BLOCK 2, WL1 = 22392 206b2

XD2~ WL . BLOCK 2, WL2 . WL ‘x02 LATCH SEL ; z : SEL ~ LATCH

CKT ' CKT ‘ BLOCK 2, WL n =

‘ H ‘ ‘P H l 206m1 208m1 ~ BLOCK m, WL 1 < 208m2 206m2

XDm_ W|_ _ BLOCK m, WL2 _ WL )(Dm LATCH SEL : : : SEI- ‘ LATCH

CK ' CKT

‘ BLOCK m, WL n k

T 000 T I.- A

WORDLINE DECODER B WORDLINE DECODER D


UPDATE INITIAL SELECTION SELECTION LATCH LATCH

TO LOCOAL XDECODER

LATCH1 LATCH2 ml Ls u \_/_?= \@

ERASEINITIALIZATION L L H GND VDD GND GND

ERASESELECT H H L GND VDD GND GND

ERASE L L L GND GND <min.VTCe|| -HV

PROGRAM INITIALIZATIO L L H VDD VDD GND GND

PROGRAM H H L VDD +HV GND GND

READ INITIALIZATION L L H v00 VDD GND GND

READ H H L V00 V00 GND GND

TABLE 2


.- -------------------------------------------- --; 50o

. ISO 5

FROM/TO t ; ,Ji. 5 WORDLINE : ‘—|——' ;

; ISOB f

. vs 5

1 SE“ 504 502 5

FIG. 12

ISO 1808 SET1 SET2 v_s v_1 Q E

ERASE RESET H L H H VDD v00 GND GND

ERASE SELECT H L H H GND VDD GND GND

ERASE L H L L GND GND <Vt min. -HV

PROGRAM SELECT H L H H VDD VDD GND GND

PROGRAM L H L L VDD + HV VDD VDD

READ H L L L GND VDD GND GND

TABLE 3

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