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Leo Greiner PIXEL Hardware meeting 2007-12-13
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HFT PIXEL detector LVDS Data Path Testing
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Outline
• Review of RDO design.
• LVDS Data Path test design
• Status
For more information, please see:http://rnc.lbl.gov/hft/hardware/docs/LVDS/index.html
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Phase-1 Sensor characteristics
•640 x 640 array – 30 micron pixels•On-chip CDS and discriminators•4 LVDS outputs / sensor •Rolling shutter readout – binary digital data per pixel•640 microsecond integration time•160 MHz LVDS RDO clock speed (this is configurable)
The Ultimate sensor will have on chip zero-suppression and 1 output / sensor. The readout clock can be slower than the 160 MHz required for the Phase-1.
Leo Greiner PIXEL Hardware meeting 2007-12-13
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RDO System Design – System Blocks• This is a highly parallel system – a schematic representation is shown
below.
Carrier X10
Ladder X 4
Sensor X 10 LU protectedVoltageRegulators
X 40
LVDS, signal,controlMass TerminationPatch
PowerSupplies
RDO Boards
RDO PCs
Trigger,Control,Monitor
DAQ,Control,Monitor
X 10? TBD
X TBD
Leo Greiner PIXEL Hardware meeting 2007-12-13
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1 m – Low mass twisted pair
6 m - twisted pair
RDO System Design – Physical Layout
Sensors, Ladders, Carriers(interaction point)
LU Protected Regulators,Mass cable termination
RDO Boards DAQ PCs
Magnet Pole Face(Low Rad Area)
DAQ Room
PowerSupplies
Platform
30 m
100 m - Fiber optic cables
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Detailed RDO System Structure – Sensors and Cables
PIXEL Ladder
40 LVDS Sensor output pairs clock, control, JTAG, power,ground.
10 MAPS Detectors
low mass / stiffnesscables
to motherboard
LVDS drivers
Early prototype cable with 40 differential pair output, clock and control routed under sensorarea.
•4 LVDS outputs / sensor
Cable•4 layer - 150 micron thickness•Aluminum Conductor•Radiation Length ~ 0.1 %•40 LVDS pair signal traces•Clock, JTAG, sync, marker
Fine twisted pair cables125 micron diameter wireSoldered directly to cableLow stiffness / mass
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Detailed RDO System Structure – LU Protection and Mass Termination
Power Reg.LU detection
Power Reg.LU detection
Power Reg.LU detection
Power Reg.LU detection
1 ladder of 10 sensorssignal, pwr, gnd, clk, etc.Signal + misc. 150 micron dia wirepower, gnd = larger dia.
Main Board
Cable to RDOBoard
Molex typePower connection soldered
connection
mass terminationconnectors to RDOBoard
mass terminationconnector to MainBoard
Connector toMain Board
1 Main Boardper carrier
10 carriers inthe PIXELdetector
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Detailed RDO System Structure – RDO Board(s)
New motherboard
Two board System – Virtex-5 Development board mated to a new HFT motherboard
Xilinx Virtex-5 Development Board
•Digital I/O LVDS Drivers•4 X >80 MHz ADCs•PMC connectors for SIU•Cypress USB chipset•SODIMM Memory slot•Serial interface•Trigger / Control input
•FF1760 Package•800 – 1200 I/O pins•4.6 – 10.4 Mb block RAM•550 MHz internal clock
Note – This board is designed for development and testing.Not all features will be loadedfor production.
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Data Path LVDS Test Block Diagram
Virtex-5interfaceboard
CLK 3
CLK 2
CLK 1
1=>41=>41=>41=>41=>41=>41=>41=>41=>41=>4LVDS Buffers
Mass termination board
16 x CLK 1
12 x CLK 2
12 x CLK 3
1 => 4 LVDS fan-outs
Multi-drop LVDS CLKs
All signals carried between mass termination boardand ladder are carried via fine twisted pair wire witha length of 1m.
All signals carried between mass terminationboard and Virtex-5 interface board are carried
LG - 10/29/2007
Parallel but buffered signal pathfor all signals on the same masstermination board. This allows fortesting with LVDS buffers insertedinto the signal path at the masstermiation board by moving the connection cables to the alternatepath.
Virtex-5interfaceboard
CLK 3
CLK 2
CLK 1
1=>41=>41=>41=>41=>41=>41=>41=>41=>41=>4LVDS Buffers
Mass termination board
16 x CLK 1
12 x CLK 2
12 x CLK 3
1 => 4 LVDS fan-outs
Multi-drop LVDS CLKs
All signals carried between mass termination boardand ladder are carried via fine twisted pair wire witha length of 1m.
All signals carried between mass terminationboard and Virtex-5 interface board are carried via twisted pair cables.
LG - 10/29/2007
Parallel but buffered signal pathfor all signals on the same masstermination board. This allows fortesting with LVDS buffers insertedinto the signal path at the masstermiation board by moving the connection cables to the alternatepath.
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Testing PlanBit Error Rate and Eye Pattern Plots for
combinations of:
1. Different cable types from the Mass-termination board to the V5 interface board.
2. Different cable lengths from the Mass-termination board to the V5 interface board.
3. Range of clock RDO frequencies including pseudo random data and clock data.
4. Hardware configuration either straight path through Mass-termination board or through buffers.
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Status• Virtex-5 Development Board – in hand and
ready for testing.
• Ladder test board – Layout completed. Soliciting quotations for PCB fabrication.
• Mass-termination board – in Layout.
• V5 interface board – Schematic complete. Ready for layout.
We anticipate being ready to begin testing in mid January.
Leo Greiner PIXEL Hardware meeting 2007-12-13
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fin
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Detailed System Structure – RDO Functional Data Path – Phase 1
AddressCounter
Run LengthEncoding?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
EventBufferX10?
ONE UNIT PER SENSOR STREAM
EventBuilder
DDL SIUFiber OpticModule
RDOBuffer
ONE UNIT PER MOTHERBOARD
ControlLogic
Motherboard / VIRTEX-5
160 MHz LVDSSensor Data4 Streams / Sensor
Events to DAQ PC
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Data Rates - Parameters
• Rates as per Jim Thomas, L = 3 x 1027 for Phase-1, L = 8 x 1027 for Ultimate.
• 2.5 hits / cluster.• 1 kHz average event rate.• 10 inner ladders, 30 outer ladders.• Factor of 1.6 for event format overhead (can be
lowered).• No run length encoding.
61.5 6.0
157.0 15.0
R = 2.5 R = 8.0
200 us
640 us
Hits / Sensor at L = 8 x 1027.
IntegrationTime
Radius
Leo Greiner PIXEL Hardware meeting 2007-12-13
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Data Rates
• Ultimate => 49.7 MB / s raw addresses.
=> 79.5 MB / s data rate.
• Phase–1 => 59.6 MB / s raw addresses
=> 95.4 MB / s data rate.
The dead-time is primarily limited by the number of externally allocated readout buffers!