IHPIm Technologiepark 2515236 Frankfurt (Oder)
Germany
IHP Im Technologiepark 25 15236 Frankfurt (Oder) Germany www.ihp-microelectronics.com © 2006 - All rights reserved
LEON-2: General Purpose Processorfor a Wireless Engine
Z. Stamenković
IHP Innovations for High Performance Microelectronics Slide 2 © 2006 - All rights reserved
Concept
• To realize a vertical strategy from application to silicon
ApplicationLocation Aware Service Platform
picoJava
Java VMApplicationPresentationSession
Transport (TCP)Network (IP)
Data Link ControlPhysical
Management:
• Power consumption
• Performance
IHP Innovations for High Performance Microelectronics Slide 3 © 2006 - All rights reserved
Wireless Engine
RFBasebandDLC
Application
Engine
Protocol
Engine
Power
Management
Test
Engine
RFBasebandDLC
ApplicationEngine
ProtocolEngine
PowerManagement
TestEngine
• Vertical approach from application to silicon can significantly improve the inter-layer performance characteristics
• Wireless engine is a system-on-chip solution for mobile computing terminals based on the vertical approach
IHP Innovations for High Performance Microelectronics Slide 4 © 2006 - All rights reserved
• Wireless Broadband Network (WBN)
Single chip communication system for wireless data transfer in the 5GHz band with a rate of about 6 to 54 Mbit/s
• Wireless Internet (WI)
Vertical protocol optimization: power efficiency, performance
• Mobile Computing (MoCo)
Service platform:
Location aware
Java based
Wireless Engine Projects
PHY
DLC
IP
TCP
App
Man
agem
ent
IHP Innovations for High Performance Microelectronics Slide 5 © 2006 - All rights reserved
CPU
I-Cache
D-Cache
AHB Controller
DCLDSU
AHB
AHB/APBBridge
Memory Controller
APB
SRAM Flash
IO PortIrq Ctrl
TimersUARTs
LEON-2 Processor System
IHP Innovations for High Performance Microelectronics Slide 6 © 2006 - All rights reserved
• Installation of the release
• Adaptation of the configuration tool (to include IHP’s library)
• Implementation of data and instruction caches
• Implementation of BIST logic for SRAMs
• Logic synthesis of the design
• Implementation of scan chain
• Generation of the chip layout
• Simulation (functional, post-synthesis and post-layout net-list)
• Scan test vectors generation (ATPG)
• BIST and scan test simulation
• Adaptation of testbenches (SPARC CC installed)
• EVCD test vectors generation (with and without timing data)
• Test specification
• Documentation
Implementation of LEON-2 Processor System
IHP Innovations for High Performance Microelectronics Slide 7 © 2006 - All rights reserved
Chip Features
LEON-2
Area (mm2) 27
Number of signal ports 111
Number of power ports 16
Number of BIST ports 16
Number of scan ports 1 (3)
Transistors (x106) 1.5
Cache Memory (kB) 20
Scanable Flip-Flops (x103) 11.2
Power/Frequency (mW/MHz) 8.9
Max Frequency (MHz) 83
Cache Array
Size (KB)
No. of Words
Data Width
Address Width
I/D Data 8 2048 32 11
I/D Tag 2 512 23 of 32 9
